In the past twenty years, progress in intrusion detection has been steady but slow. The biggest challenge is to detect new attacks in real time. In this work, a deep learning approach for anomaly detection using a Restricted Boltzmann Machine (RBM) and a deep belief network are implemented. Our method uses a one-hidden layer RBM to perform unsupervised feature reduction. The resultant weights from this RBM are passed to another RBM producing a deep belief network. The pre-trained weights are passed into a fine tuning layer consisting of a Logistic Regression (LR) classifier with multi-class soft-max. We have implemented the deep learning architecture in C++ in Microsoft Visual Studio 2013 and we use the DARPA KDDCUP'99 dataset to evaluate its performance. Our architecture outperforms previous deep learning methods implemented by Li and Salama in both detection speed and accuracy. We achieve a detection rate of 97.9% on the total 10% KDDCUP'99 test dataset. By improving the training process of the simulation, we are also able to produce a low false negative rate of 2.47%. Although the deficiencies in the KDDCUP'99 dataset are well understood, it still presents machine learning approaches for predicting attacks with a reasonable challenge. Our future work will include applying our machine learning strategy to larger and more challenging datasets, which include larger classes of attacks.

In embedded systems and application specific integrated circuits (ASICs) that typically do not have a floating-point processor, measured data or function-sampled data is commonly described by means of an analytic function derived using standard numerical methods. The resultant errors are not caused by rounding the coefficients but by translating a real solution to a restricted fixed-point environment. A genetic algorithm has been constructed that discovers a superior piecewise polynomial approximation with coefficients restricted to the integer target space. This paper discusses the problem being solved and presents an overview of the implemented solution.

No abstract available.

We propose a behavioral approach to designing MEMS devices. This approach differs from much current research in that this approach would not require dimensional parameters for the device, but instead would require a high level, functional or behavioral description. This paper examines how such an approach would work using a case study of an optical processor manually designed using the MUMP's process.

Because so many important problems arising in VLSI design are NP-hard, VLSI algorithms must employ randomization techniques or heuristics. Thus the process of analyzing a new algorithm or of comparing two algorithms is at present an experimental one. Consequently, progress in VLSI algorithm development must be based on references to standard benchmarks. Yet examination of literature on specific problems, such as graph partitioning, shows that such standardization is not yet a reality. Here we describe a system, Circuitbase, which we are developing to address the standardization problem. Circuitbase will combine the extensive graph manipulation routines of Knuth's Stanford Graphbase package with actual circuit examples from the Benchmark Archives at CBL, standard routines for generating random examples of circuits, and standard methods for algorithm analysis. We describe Circuitbase versions of example behavioral, structural, and physical views of a VLSI circuit and discuss how Circuitbase can support modern VLSI design environments.

A binary algorithm for division of an (M + N)-bit integer by an N-bit integer is presented. The algorithm produces the (M + 1)-bit quotient and the N-bit remainder in time O(M + N). Two hardware implementations, one using combinational logic in cellular arrays, and one employing systolic arrays, are given. These implementations are designed for modularity and regularity, and thus are suitable for VLSI systems. An important property of these implementations is that decisions are based on only one bit of the operands. Thus, fan-in and length of connecting wires are bounded independently of operand size. In addition, the systolic implementation has area O + N), which is the best possible.