Ensuring correct functional operation of a chip requires extensive testing. Without the constraints of maintaining functional operation conditions, structural (scan-based) tests allow high fault coverage to be achieved efficiently. To cover defects that are only exhibited under functional operation conditions, functional test sequences are used for complementing scan-based tests. One of the limitations of functional test sequences is their length, making it important to apply test compaction. To avoid losing the functional properties of a sequence when test compaction is applied at the gate level, design-for-testability (DFT) logic can be used for keeping the circuit in its functional state space. In this context, this article suggests the new concept of a modular functional test sequence consisting of subsequences that can be plugged in or out to increase the fault coverage or reduce the sequence length. To support modularity at the gate level, DFT logic is used for restoring functional states between subsequences. Modularity offers the key advantage that a single compact functional test sequence can be constructed from a given pool of functional test sequences, and the modular sequence can be updated as additional sequences become available in the pool, or additional fault models are targeted. The article develops a procedure for the generation and compaction of modular sequences using subsequences from a given pool, and presents experimental results for benchmark circuits in an academic simulation environment to demonstrate its effectiveness and limitations.

State-of-the-art technologies exhibit a variety of defects requiring test sets that detect a variety of fault models. Such a test set is large, and tests at the end of the test set detect small numbers of additional faults. Procedures that steepen the fault coverage curve help address constraints on test application time and test data volume of large test sets. Existing steepening procedures move tests detecting more faults to earlier positions of the test set. Such procedures are referred to as forward steepening procedures. This article takes a complementary view that results in a reverse steepening procedure. The procedure moves tests detecting fewer additional faults to later positions. Indirectly, it causes tests detecting more faults to appear in earlier positions. Experimental results for benchmark circuits in an academic simulation environment demonstrate the effectiveness of the reverse steepening procedure as a standalone procedure, and as part of a procedure that reduces the test data volume without reducing the fault coverage.

Advanced delay fault models such as the two-cycle defectaware, cell-aware or gate-exhaustive fault models associate faults with pairs of input patterns of gates (or cells). The large numbers of faults defined for these fault models result in large test sets. This article addresses the need to control the size of a scan-based test set for two-cycle gate-exhaustive faults in two ways: (1) only functionally possible faults, i.e., faults that can cause a circuit to fail during functional operation, contribute new tests to the test set; and (2) multicycle tests are used to increase the number of faults that each test can detect. The effectiveness of multicycle tests for advanced fault models results from the following key observation. Faults that are associated with the same gate cannot be detected by the same two-cycle test, but a multicycle test can detect several faults that are associated with the same gate by activating the faults at different clock cycles. The article describes a test compaction procedure that uses this observation, and presents experimental results for benchmark circuits in an academic simulation environment to demonstrate its effectiveness.

Test data compression supports reductions in test data volume and test application time. The use of multicycle scan-based tests with several functional capture cycles between scan operations supports test compaction beyond that possible with single-cycle or two-cycle tests. Multicycle tests with constant primary input sequences are used for avoiding the need to synchronize the primary input sequence with the functional clock. However, this prevents the detection of delay faults in the output cone of the primary inputs. A different solution is to produce the primary input sequence of a multicycle test by the on-chip decompression logic in addition to the scan-in state. This approach is considered in this article. The key new contribution of the article is to extend the scan chain that drives the primary inputs and add design-for-testability ( DFT ) logic, to ensure that the primary input sequences produced by the decompression logic are suitable for the application of multicycle tests. Experimental results for transition faults in benchmark circuits demonstrate significant fault coverage improvements and significant test compaction.

Chip aging may result in hardware defects whose likelihood of occurrence depends on the layout and functional workload at the defect site. In-field testing is important for the detection of defects that occur because of aging. In-field test periods have different durations, and it is important to utilize every test period for the detection of the defects that are the most likely to occur with aging. This article considers this problem for the first time in the context where a stored deterministic scan-based test set is used for in-field test application. The article formulates the problem as that of steepening the fault coverage curve of the test set by introducing an aging aware steepening metric. Using the suggested metric, the procedure described in this article reorders and modifies a given test set to ensure that every additional test would detect as many additional faults as possible out of the faults that are the most susceptible to aging. The procedure is implemented in an academic simulation environment and applied to benchmark circuits. The results demonstrate its effectiveness in ensuring that each test period would be utilized for detecting the faults that are the most likely to occur with aging.

Chiplet-based designs use large numbers of interconnects that need to be tested thoroughly. Standard isolation logic allows the logic blocks (chiplets) and the interconnects to be tested separately. It was recently suggested for additional defect coverage to use a scan-based test set that tests the interconnects together with the logic blocks in a mode of operation that is closer to functional. In this scenario, a scan-based test set for a logic block targets faults in the logic block as well as the interconnects it drives. An exhaustive static fault model was used earlier for subsets of adjacent interconnects. In the same scenario, this article studies the presence of functionally undetectable interconnect faults, and their relationship to the configuration of the interconnects as a two-dimensional array. The article observes that the specific configuration of the interconnects in the two-dimensional array can affect the number of functionally undetectable faults. Moreover, by modifying the configuration, it is possible to eliminate functionally undetectable faults that are important to consider in other configurations. The article describes a test generation procedure that includes the identification of functionally undetectable interconnect faults, and a procedure for reconfiguring the interconnects to eliminate undetectable faults. The implementation of the procedures was carried out in an academic simulation environment. Experimental results for benchmark circuits demonstrate the effectiveness of the procedures in achieving complete interconnect fault coverage, and eliminating all the undetectable interconnect faults.

Defects may be exhibited during functional operation because of test escapes or chip aging. When the occurrence of defects is detected during functional operation, the defects can be detected and diagnosed using functional sequences. To improve the effectiveness of functional sequences for logic diagnosis, this paper suggests the insertion of observation points on next-state variables. The target faults are functionally possible faults, i.e., faults that can cause a chip to fail during functional operation. The paper describes an efficient diagnostic fault simulation procedure for functional sequences. Using this procedure it describes a procedure for the insertion of observation points. Experimental results for benchmark circuits in an academic simulation environment demonstrate the potential of observation points on next-state variables to improve logic diagnosis.

Chip aging is a reliability concern for systems with long lifetimes. To detect defects that occur during the lifetime of a chip, in-field testing is applied when a system is turned on or off, as well as during idle periods. When in-field tests are designed for target faults, they target single faults, and may be invalidated when multiple faults are present. Although rare in general, this effect becomes more important when it involves defects that are likely to occur with aging. Addressing this situation in its most general form requires large numbers of multiple faults to be analyzed. This article suggests a solution based on a detailed analysis of situations where tests may be invalidated by multiple faults that are likely to occur with aging. The analysis results in small sets of faults and tests to detect them. The article demonstrates this approach by considering a situation involving double transition faults. Experimental results for benchmark circuits demonstrate the numbers of double transition faults that need to be considered and the numbers of tests for detecting them.

Functional test sequences can complement scan-based tests by enhancing the detection of defects that can affect the correct functional operation of a design. A large pool of functional test sequences may already be available for the design. When selecting a subset of the functional test sequences for test application, test compaction procedures select subsequences from the pool to reach the fault coverage of the entire pool using as few clock cycles as possible. However, a large number of clock cycles may be needed for applying the entire pool even after test compaction, exceeding the numbers of clock cycles that can be accommodated during short in-field test periods. Motivated by this observation, the article addresses the following problem: given a bound on the number of clock cycles for test application, which subsequences should be applied to achieve the highest possible fault coverage. The solution suggested in this article takes a fine-grained view of steepening the fault coverage curve of the pool. Compared with a coarse-grained view, experimental results for benchmark circuits show that a higher fault coverage can be achieved with the same number of clock cycles.

Recent studies of silent data errors (SDEs) in mega-scale datacenters indicate that SDEs are caused by small delay defects that escaped detection by manufacturing tests or occurred during the lifetime of the system. A small delay defect is detected by a test that propagates a transition through one of the longest paths that includes the defect site. Once the path is selected, for every gate or cell on the path, ATPG assigns off-path input values to enable the propagation of a transition through the path. For complex gates, such as AOI and XOR, there are multiple sets of possible assignments (or input stimuli) that the ATPG can use, with substantially different propagation delays. Existing test generation procedures do not consider these differences in propagation delays once a path is selected. We propose a new approach to ATPG for small delay defects, called Timing Verification Test or TVT, that selects the off-path input values to maximize the delay of the path. The tests produced by TVT result in path delays that are significantly higher than those obtained when off-path input values are selected arbitrarily by the ATPG if they are not mandated by the propagation conditions. TVT also considers different PVT corners that affect the selection of the longest paths. Experimental results for an industrial core show that TVT increases the path delays by up to 15.91% for a set of the longest paths needed to detect small cell-aware delay faults at different PVT corners.

An important component of ensuring system reliability is the application of functional tests. Functional test sequences are available after simulation-based design verification, they can be extracted from application programs, or generated for target faults. Functional test sequences can be long, and test compaction at the gate-level is important for reducing the test application time without losing fault coverage. Experimental results with several test compaction procedures indicate that test compaction sometimes leads accidentally to an increased fault coverage. Such an increase was observed recently with a gate-level test compaction procedure that has the unique property of restoring functional operation conditions after parts of a sequence are eliminated. The contribution of this article is to use this property of the test compaction procedure to increase the fault coverage directly, in a targeted manner, while compacting the sequence. Experimental results for benchmark circuits in an academic environment demonstrate a significant fault coverage increase combined with significant test compaction.

Comprehensive defect coverage requires test sets that detect faults from several fault models. A test set is typically topped-off to detect faults from an additional fault model that are not already detected. This creates large test sets whose last tests detect small numbers of additional faults. Reducing the storage requirements of topped-off test sets (or test sets for fault models with large numbers of faults) is the topic of this article. Instead of storing the last tests in their entirety, it was shown previously that it is possible to produce the last tests of the test set from tests that appear earlier by complementing single bits. The storage requirements are reduced when only complemented bits are stored; however, the number of applied tests is increased. This article observes that changing the configuration by which decompressed test data are shifted into scan chains produces new tests that are effective in replacing tests at the end of a topped-off test set without increasing the number of applied tests. This approach is developed in this article in an academic environment and implemented using academic software tools. It is applied to benchmark circuits to demonstrate its effectiveness.

In-field testing is important for detecting defects that escaped manufacturing tests or occurred during the lifetime of a chip. When in-field testing is performed periodically, some of the test periods may be shorter than others. Short test periods should focus on the faults that are the most likely to occur with aging, whereas long test periods can apply a more comprehensive test set. This article studies this scenario in the context of a logic built-in self-test (LBIST) approach that partitions compressed tests into subvectors for on-chip storage, and combines subvectors into compressed tests on-chip using counters. This approach has low storage requirements, allows complete fault coverage to be achieved, and uses a moderate number of tests. The problem of applying a small number of tests during a short testing period is formulated as a static problem of rearranging the subvectors (with possible repetitions and modification) such that the first$n_{1}$subvectors are sufficient for detecting a subset of faults$F_{1}$, and$n_{1}$is as small as possible. Experimental results for benchmark circuits in an academic environment demonstrate the number of tests and overall storage requirements.

Defects that are manifested during functional operation, also referred to as functionally possible, have been shown to be responsible for the occurrence of silent data corruption (SDC) in large datacenters. The defects may have occurred because of high workloads that speed up the process of chip aging. This motivated the focus of earlier works on functionally possible faults in sites that are subjected to high functional switching activities. The functional switching activity in earlier works was based on transitions. Pulses were not considered in this context. This article defines the notion of a hazard based functional switching activity that captures the conditions for pulses to occur during functional operation. It then revisits the hazard based detection conditions for transition faults, under which faults are activated using pulses instead of transitions. The article describes a procedure that selects target faults that may be susceptible to aging because of pulses, and a test generation procedure for the target faults. Experimental results for benchmark circuits demonstrate the potential importance of considering hazard based faults. The results also demonstrate that only small numbers of tests need to be added to a conventional transition fault test set for the selected hazard based transition faults.

High reliability requirements in certain systems are combined with constraints on test overheads, including test data volume, test application time and design-for-testability ( DFT ) logic. The overheads can be reduced if they are shared among different types of tests and optimized together. Several observations are combined in this article to allow sharing of overheads when the goal is to produce a compact transition fault test set with a high fault coverage and low storage requirements supported by DFT logic under standard scan. Based on these observations, the iterative procedure described in this article optimizes four parameters together: (1) the transition fault coverage, (2) the number of stored tests, (3) the number of applied tests, and (4) the size of the DFT logic. Experimental results for benchmark circuits in an academic environment demonstrate the effectiveness of the procedure.

Advanced fault models, such as the defect-aware, cell-aware, and gate-exhaustive fault models, associate several faults with each standard cell or gate of a design. Test generation procedures, including ones that target advanced fault models, produce incompletely specified tests, or test cubes, to support test compaction and test data compression. The key contribution of this article is to generalize the concept of a test cube into that of a test template for fault models where several faults are associated with the same standard cell or gate. Considering single-cycle gate-exhaustive faults as an example, a test template π i for a gate G i with a set of faults F i captures input values that are common to all the tests for the faults in F i while allowing other input values to be different for different faults in F i . A new value, denoted by v , designates a value that is not common to all the inputs. A test template is useful, since faults in F i share many of the same activation and propagation conditions, and learning the common input values of their tests can reduce the search space for test generation. The effectiveness of using test templates to guide test generation is demonstrated by considering single-cycle gate-exhaustive faults that are not detected by a given test set. Such faults are hard to detect. As part of the test generation procedure developed in this article, merging of test templates is carried out for increasing the fault coverage, and additional tests are generated by specifying the v values of test templates. The implementation of the test generation procedure was performed in an academic simulation environment using academic software tools, and the results are reported for benchmark circuits.

Logic diagnosis is important for deriving information about defects that are present in fabricated units when they are found to be faulty. This information can assist in yield learning and improvement. When needed, the accuracy of logic diagnosis can be improved by using diagnostic tests to complement fault detection tests. Diagnostic test generation for logic faults is the process that produces diagnostic tests. Diagnostic test generation procedures target fault pairs that are not distinguished by a fault detection test set. However, an improvement in diagnostic accuracy is not guaranteed as diagnostic tests are added to the test set, and some tests may cause the diagnostic accuracy to decrease. This article is the first to suggest a second target for diagnostic test generation based on the results of logic diagnosis for simulated faulty units. The second target attempts to predict when a diagnostic test will have a negative effect on the diagnostic accuracy, and helps exclude such a test from the test set. An attempt to generate an alternate test for the same fault pair is made in a later iteration of diagnostic test generation. The dual target diagnostic test generation procedure suggested in this article was implemented in an academic simulation environment and applied to benchmark circuits. Experimental results demonstrate the ability of the procedure to identify diagnostic tests that should be avoided. The tests typically have alternates that can be found in later iterations.

State-of-the-art designs include identical instances of logic blocks to support parallel computations. Identical logic blocks at close physical proximity can be tested online by comparing their output sequences. This removes the need for known input and output sequences. To use output comparison for two logic blocks,$B_{0}$and$B_{1}$, the logic blocks should be synchronized to the same state, and the same input sequence should be applied to them. Assuming that$B_{0}$performs functional computations and$B_{1}$is idle, a process described earlier synchronizes$B_{1}$to the state of$B_{0}$by using a synchronization period where$B_{1}$receives the input sequence of$B_{0}$, and values of selected state variables are copied from$B_{0}$to$B_{1}$. A single synchronization period was used earlier. The first key contribution of this article is to introduce a retry-based synchronization process with multiple synchronization periods to avoid flagging synchronization failures as faults. The second contribution of this article is to develop the synchronization process in a simulation environment that considers functional operation conditions. Experimental results for benchmark circuits demonstrate the effectiveness of the retry-based process and the importance of the functional simulation environment.

Chip aging is a reliability concern that requires tests to be applied in-field. High workloads that translate into high switching activities during functional operation speed up the process of aging, and may result in defects. With in-field test periods varying in length, shorter in-field test periods should be used for targeting the faults that are more susceptible to aging. To identify such faults, the computation of the functional switching activities for the target faults requires the availability of functional sequences. This article targets the removal of this requirement. This is possible under the premise that the relative switching activities for target faults have a stronger dependence on circuit properties than on the patterns applied to it. Under this premise, the article investigates the possibility of replacing the functional switching activity with the switching activity obtained for a fault under a scan-based test set. Experimental results to demonstrate the accuracy of the new switching activity metric are presented for transition faults in benchmark circuits.

The adverse effects of silent data errors (SDEs) on the operation of large data centers have been reported recently by hyper-scalar companies. SDEs tend to be elusive and are difficult to detect until they affect a particular application after the IC has been deployed in-field. Although the cause of SDEs ranges from manufacturing test escapes and design marginalities to design bugs, experimental data from the industry largely indicate that SDEs can be traced back to timing related issues that become more severe with aging and depend on the operating conditions of process, voltage and temperature (PVT). This paper describes a complete framework for monitoring the timing related issues under different operating conditions for test and functional operation. The framework has three components. The first component is a procedure for the identification of the longest paths that are prone to delay failures under different PVT corners. The second component is a programmable slack monitor design that monitors the changes in path delays within a detection window, and produces an alarm when a path is close to failure, with proximity to failure being a programmable feature. The third component is a procedure that determines the placement of the monitors in the design. Experimental results for an industrial design demonstrate the trade-offs related to the placement of monitors and the scenarios under which the monitors raise alarms.

As fabrication technologies advance and defects become more difficult to detect, fault models evolve to capture detection conditions of hard-to-detect defects. As a result, the number of faults increases, and fault selection becomes necessary. In this case, it is important if among the selected target faults there are faults that can affect the correct functional operation of the circuit. Such faults are referred to as functionally-possible or FP. FP faults can be identified by a type of tests referred to as functional scan-based tests. Once FP faults are identified, it is possible to detect them using the standard types of scan-based tests to increase the fault coverage and ensure that the tests can be compacted and compressed. This article applies such an approach to bridging faults. Experimental results for benchmark circuits demonstrate the discussion.

When LBIST is used for test application in-field, and the presence of a defect is detected by the LBIST test set, it is advantageous if the same LBIST test set is used for diagnosis, either by itself or as part of a diagnostic test set. The goal of this paper is to develop an LBIST scheme for generating a test set that is useful for logic diagnosis. The proposed approach belongs to the class of storage-based LBIST approaches, and has the ability to produce additional (diagnostic) tests from the same type of stored test data entries used for fault detection. The main contributions of the paper are: (1) the derivation of targets for diagnostic tests that are suitable for LBIST, (2) the computation of stored test data for diagnosis to enhance the stored test data used for fault detection, and (3) a logic diagnosis process that is suitable for the LBIST approach. Experimental results for benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor demonstrate the effectiveness of the proposed scheme in producing a diagnostic test set.

Compaction of scan-based test sets is important for reducing the test application time and test data volume. For a circuit with K flip-flops in its longest scan chain, a conventional single-cycle scan-based test starts with a scan-in operation of K scan shift cycles, followed by a single functional capture cycle. The test ends with a scan-out operation of K scan shift cycles that is overlapped with the scan-in operation of the next test. Such a test is referred to as a $(K, 1)$-cycle test. This article defines a $(k, 1)$-cycle test to have $0 \leq k \leq K$ scan shift cycles in its scan-in and scan-out operations. A $(k, 1)$-cycle test is compressed similar to a conventional $(K, 1)$-cycle test, and overlapping of scan-out and scan-in operations can be performed as for conventional tests. The advantage of using $(k, 1)$-cycle tests with $0 \leq k\lt K$ is that they require fewer clock cycles, thus contributing to test compaction by reducing the number of clock cycles required for test application. This article describes a test generation procedure that produces a compressed test set based on the use of $(k, 1)$ cycle tests. Experimental results for single stuck-at faults in benchmark circuits demonstrate the effectiveness of $(k, 1)$-cycle tests for test compaction.

VLSI design flows improve design parameters (performance, power, area, and testability) iteratively. Whereas the “shift left” trend implies that changes at the RTL are preferred for improving the design, it is sometimes necessary to make gate-level changes, e.g., because of layout changes or ECO. In an iterative design flow, repeated ATPG to evaluate the testability of a design after design changes have been made creates a bottleneck. The goal of this article is to address this bottleneck considering two-cycle tests for transition faults. The test generation procedure described in third article transforms an LOC test set generated for an earlier version of the design into an LOC test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design, taking into consideration that RTL resynthesis may produce a new gate-level netlist, with new signal names and different input and output orders. To address two-cycle tests, the mapping is performed over two time frames of the design. Experimental results for industrial circuits with changes made at the RTL as well as gate-level demonstrate significant runtime gains with the test generation procedure described in this article.

Distributed test data compression refers to the scenario where each logic block in a design has its own decompression logic and compact set of compressed tests. A static test compaction procedure for this scenario was described recently. The procedure accepts compact compressed test sets for the logic blocks. It combines the test sets into a single shared test set and optimizes it for all the logic blocks. This article describes a dynamic test compaction procedure for the same scenario. The procedure starts from an empty shared test set and considers the logic blocks one by one. It increases the fault coverage of the shared test set either by adding a compressed test or by extending a compressed test already included in the shared test set. Experimental results presented for groups of benchmark circuits demonstrate significant sharing that leads to a significant reduction in the storage requirements for tests.

Dynamic test compaction techniques are used during test generation to ensure that each test detects as many faults as possible, resulting in the smallest possible number of tests. As additional tests are generated, detected faults are removed from consideration, and it is expected that the number of detected faults per test would decrease. A nonmonotonic decrease in this parameter indicates that the test set may be larger than necessary since tests detect fewer faults than possible. To ensure a monotonic decrease, this article suggests a dynamic test compaction technique that inserts every new test into the test set at a position based on the number of faults it detects. After inserting a test, the procedure adjusts the test and all the tests that follow it to detect more faults. Experimental results to demonstrate the effectiveness of test insertion as a dynamic test compaction technique are presented for single-cycle gate-exhaustive faults in benchmark circuits. The large number of faults brings out the ability of test insertion to contribute to test compaction.

Small delay defects are important to detect after manufacturing and during in-field testing. Small delay defects are detected by tests for path delay faults. Path selection criteria consider the length of a path, the ability to detect a path delay fault, and the need to cover every line in the circuit. The similarity to a functionally-possible path (one that can be activated during functional operation) was also considered as a criterion for the selection of path delay faults. Functional considerations in the selection of path delay faults are important for ensuring the detection of small delay defects that can affect the correct functional operation of the circuit. Especially during in-field testing it is important if defects that can affect the correct functional operation of the circuit are detected since such defects can be responsible for silent data corruption that has been reported recently. This article suggests a path selection criterion and test generation procedure that focus on small delay defects that can affect the correct functional operation of the circuit. Experimental results for benchmark circuits demonstrate the need for this criterion.

Two properties of functional test sequences make them suitable for complementing scan-based tests: they can detect defects whose activation requires large numbers of functional capture cycles while avoiding non-functional operation conditions. However, the gate-level fault coverage achievable with functional test sequences is lower than that of scan-based tests. Design-for-testability logic that increases the fault coverage creates non-functional operation conditions and thus eliminates the advantages of fault detection under functional operation conditions. This article describes a design-for-testability approach that increases the fault coverage of a functional test sequence without creating non-functional operation conditions for the fault-free circuit. The key observation underlying this approach is that faulty circuits traverse different states than the fault-free circuit. By activating design-for-testability logic it is possible to maintain the same fault-free state, but change the faulty state in a way that results in the detection of the fault. Experimental results for benchmark circuits demonstrate the extent of the fault coverage increase possible with this approach.

Functional tests are important for detecting delay faults under functional operation conditions. Functional operation conditions can be created with a scan-based test by ensuring that the test would take the circuit into a reachable state. In this case, the functional capture cycles that follow, where the circuit traverses reachable states, can be used for fault detection. This brief defines a type of scan-based test that is designed to take advantage of the functional capture cycles before the circuit enters a reachable state for activating delay faults. The tests are referred to as unconstrained-activation functional-detection (UAFD) tests. In a c-cycle UAFD test for a fault, the first$c-2$functional capture cycles activate the fault and take the circuit into a reachable state. The last two functional capture cycles detect the fault while taking the circuit through reachable states. Experimental results for benchmark circuits demonstrate the increase in the transition fault coverage achievable when nonreachable states are used for fault activation.

Logic built-in self-test (LBIST) approaches use an on-chip logic block for test generation and thus enable in-field testing. Recent reports of silent data corruption underline the importance of in-field testing. In a class of storage-basedLBISTapproaches, compressed tests are stored on-chip and decompressed by an on-chip decompression logic. The on-chip storage requirements may become a bottleneck when the number of compressed tests is large. In this case, using each compressed test for applying several different tests allows the storage requirements to be reduced. However, producing different tests from each compressed test has a hardware overhead. This article suggests a new on-chip storage scheme for compressed tests that eliminates the additional hardware overhead. Under the new storage scheme, a set ofNB-bit compressed tests targeting a set of faultsF0is translated into a sequenceSofN ⋅ Bbits. EveryBconsecutive bits ofSare considered as a compressed test. The sequenceSthus yields close toN ⋅ Bcompressed tests, magnifying the test data stored inSalmostBtimes. Taking advantage of the extra tests, the article describes a software procedure that is applied offline to reduceSwithout losing fault coverage ofF0. Experimental results for benchmark circuits demonstrate significant reductions in the storage requirements ofSand significant increases in the fault coverage of a second set of faults,F1.

Testing for delay faults after chip manufacturing is critical to correct chip operation. Tests for delay faults are applied using scan chains that provide access to internal memory elements. As a result, a circuit may operate under non-functional operation conditions during test application. This may lead to overtesting. The extraction of broadside tests from functional test sequences ensures that the tests create functional operation conditions. When N functional test sequences of length L +1 are available, the number of broadside tests that can be extracted is N · L . Depending on the source of the functional test sequences, the value of N · L may be large. In this case, it is important to select a subset of n ≤ N sequences and consider only the first l ≤ L clock cycles of every sequence for the extraction of n · l ≪ N · L broadside tests. The two-dimensional N × L search space for broadside tests is the subject of this article. Using a static procedure that considers fixed values of N and l , the article demonstrates that, for the same value of N · L , different circuits benefit from different values of N and l . It also describes a dynamic procedure that matches the parameters N and l to the circuit. The discussion is supported by experimental results for transition faults in benchmark circuits.

Iterative synthesis consists of local design modifications to improve design parameters or correct design errors. Incremental test generation was suggested for evaluating the effects of the modifications on the testability of the design. This brief suggests that a fast (incomplete) procedure for identifying undetectable faults is effective in identifying that the testability will deteriorate because of a local design modification without performing test generation. Two experiments are carried out using a procedure that performs successive local design modifications. A modification is accepted only if it does not result in new undetectable faults, and other modifications are eliminated. The results for single stuck-at faults in benchmark circuits demonstrate that fast identification of undetectable faults is typically sufficient for preventing the fault coverage from decreasing because of the modifications.

The fabrication processes of chips in state-of-the-art technologies may introduce defects of various types, and a large number of tests may be needed for fault detection. However, constraints on the storage requirements of a test set can limit the number of tests and, consequently, the fault coverage. It was shown earlier that reductions in the input storage requirements of a test set can be achieved by using the same stored tests for applying several different tests. One of the operators used for this purpose complements bits of applied tests. The key contributions of this article to this scenario are the following. These issues are considered here for the first time: 1) the use of bit-complemented tests is guided by the fault coverage curve of a complete test set and bit-complementation is applied to tests from the beginning of the fault coverage curve to replace tests at the tail of the curve that detect small numbers of faults; 2) the input and output test data volume are considered together and bit-complementation is used for storing both the tests and their output responses; and 3) the procedure described in this article explores the tradeoff between the storage requirements and the number of applied tests. Experimental results for single-cycle gate-exhaustive faults in benchmark circuits demonstrate the tradeoff.

Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.

Functional broadside tests detect delay faults that can affect the correct functional operation of the circuit without overtesting. When path selection is performed to address the number of path delay faults it is important if among the target faults there are ones that can affect the correct functional operation of the circuit. A large pool of functional broadside tests is obtained when the tests are extracted from available functional sequences. In this case, tests that are extracted later may be effective for test compaction even if they do not detect new faults. This article addresses the problem of test compaction for path delay faults in this scenario. The main contribution of the article is related to the use of clusters of lines satisfying propagation conditions for path delay faults. When a test results in a cluster that is not contained in a cluster obtained for any test considered earlier, the test is potentially important for test compaction. Tests whose clusters are contained in those of other tests are discarded. Experimental results for benchmark circuits demonstrate the importance of considering tests that do not detect new path delay faults, and the effectiveness of clusters.

This paper presents a fully deterministic storage based logic built-in self-test (LBIST) approach that stores, on chip, reduced deterministic uncompressed test data sufficient for achieving complete fault coverage. The goal of this approach is to eliminate the need for pseudo-random tests, thereby reducing the test application time by reducing the number of tests required to achieve complete fault coverage. Under this approach, two types of test data are stored on chip. 1) Subsets of scan vectors obtained from a reduced set of deterministic tests, one subset per test and, 2) permutations of scan vectors stored as sets of indices, to indicate how to combine scan vectors to form tests on chip. The same permutations are applied to all the subsets, magnifying the effectiveness of each stored permutation and each subset, allowing fewer subsets as well as fewer permutations to be used. This helps in reducing the storage requirements. Experimental results are presented for single stuck-at faults in benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor to demonstrate the effectiveness of this approach.

When a pool of functional test sequences is created for simulation-based verification of a design, the same sequences can be used as manufacturing tests to complement scan-based tests. Without otherwise changing the pool, earlier compaction procedures selected sequences or subsequences as manufacturing tests from a given pool. This article is based on the new observation that the pool can be compacted further if it is first expanded by adding new sequences. New sequences are obtained without performing test generation from pairs of sequences in the pool that reach common states. The new sequences preserve functional properties of sequences in the pool. They also combine fault detection capabilities of sequences from the pool, allowing faults to be detected at earlier clock cycles. The ability of the new sequences to contribute to test compaction is evaluated based on their effect on the clock cycles where faults are detected. The article describes a procedure that applies these concepts to a pool iteratively. Experimental results demonstrate significant reductions in the size of an already-compacted pool for benchmark circuits with pools that contain common states.

When a broadside (launch-on-capture) test is extracted from a functional test sequence, the test addresses the need to avoid overtesting the circuit by exercising it under functional operation conditions. A broadside test t is extracted from a functional test sequence A by duplicating two or more functional capture cycles from A between the scan-in and scan-out operations of t. The functional capture cycles in t detect a fault f if it is activated and propagated to an observable output. This is typically a next-state variable whose value is observed during the scan-out operation of t. This article considers the added requirement that an extracted broadside test would propagate fault effects to the primary outputs. This reduces overtesting further by eliminating the detection of effects that cannot be propagated to the primary outputs during functional operation. The article makes several observations about the use of sequential fault simulation for the efficient extraction of a compact set of broadside tests that detect transition faults on the primary outputs. Experimental results for transition faults in benchmark circuits demonstrate an improved fault coverage and a reduced number of clock cycles for test application.

Test sets targeting several fault models are generated to detect defects with various behaviors. Test generation for several fault models can be performed by topping off a test set$T$for one or more fault models with tests for faults from an additional fault model that is not already detected by$T$. This article describes a procedure that tops off a test set$T$for a fault model$F_{0}$to detect faults from a fault model$F_{1}$under bounded transparent scan. Bounded transparent scan is suitable for this application since it allows faults from$F_{1}$to be detected not only by adding new tests to$T$but also by adding clock cycles to existing tests. Both functional capture and scan shift cycles are allowed under bounded transparent scan. The procedure iterates through the addition of clock cycles to existing tests while slowly adding new tests when necessary. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

Functionally possible scan-based tests create functional operation conditions during their functional capture cycles. This is important for avoiding failures that are caused by nonfunctional operation conditions rather than faults. However, the fault coverage achievable by functionally possible scan-based tests is lower than that achieved by unconstrained scan-based tests. In addition, the tests are fully specified, limiting the applicability of both test compaction and test data compression. This article introduces an approach, where a multicycle functionally possible scan-based test set is obtained from a compressed test set$S$as a dual of the unconstrained multicycle scan-based test set that$S$produces. A dual functionally possible scan-based test is obtained by replacing the scan-in state of an unconstrained test with the all-zero state (or the initial state of the circuit for functional operation). The procedure described in this article modifies a given compressed multicycle test set to improve the fault coverage achieved by the dual functionally possible scan-based test set. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

Cell-aware and gate-exhaustive faults are used for modeling defects whose activation requirements are more complex than those of stuck-at or transition faults. The number of cell-aware or gate-exhaustive faults targeted for test generation has to be bounded to avoid the generation of excessive numbers of tests. In this context, it is advantageous to be able to estimate the number of tests in advance based on the number of target faults, and avoid targeting an excessive number of faults that will result in an excessive number of tests. This article suggests such an estimate for the scenario where test generation is applied iteratively using subsets of single-cycle gate-exhaustive faults such that the detection of every additional subset will provide a meaningful increase in the coverage of the test set. Based on the results of iteration$I-1$, the estimate predicts the number of tests that will be obtained in iteration$I$. Test generation can terminate, without generating additional tests, when the estimate indicates that the number of tests will exceed a preselected bound. Experimental results for benchmark circuits demonstrate the accuracy of the estimate.

Logic built-in self-test (LBIST) eliminates the need for external test data, and thus facilitates in-field testing. Instead of pseudo-random tests that are typically produced by on-chip test generation logic, storage-based LBIST uses deterministic test data entries, which are stored on-chip, for applying tests that are closer to deterministic tests. This article describes a storage-based LBIST approach that uses a unique type of scan-based tests referred to as cyclic tests. Cyclic tests have cyclic scan enable and scan-in sequences, with a higher proportion of functional capture cycles compared with conventional scan-based tests. This results in more clock cycles where fault effects can be captured in the flip-flops. The improved fault detection capabilities this provides help balance the number of applied tests and the storage requirements. Experimental results for benchmark circuits demonstrate the effectiveness of cyclic tests.

In the early stages of yield improvement, a faulty unit may produce a large volume of fail data because of the presence of multiple defects in the functional logic. Earlier solutions that address the fail data collection process on the tester make a decision to store fail data for every test separately. This article suggests a more fine-grained approach where fail data is collected for a subset of the tests and outputs. This is represented by storing a partially specified fault-free output response on the tester, and storing a fail data entry for a faulty unit only when it conflicts with a fully specified fault-free output value. Although the fault-free output response is larger, the fail data volume collected for faulty units is reduced. This is important since fail data is collected over many faulty units. This article considers the selection of the partially specified fault-free output response a priori and presents experimental results to demonstrate that the fail data volume is reduced significantly, and accurate logic diagnosis is possible with the reduced fail data.

Path selection procedures identify path delay faults whose tests detect small delay defects. Path selection criteria are positive in the sense that they point to paths that should be selected, e.g., the longest paths. However, the longest paths are in many cases untestable, and the number of paths can be large when the longest testable paths are considered. For this scenario, it is advantageous to have a negative path selection procedure that excludes paths from consideration as targets for test generation. This provides the flexibility to identify detectable path delay faults among a reduced number of path delay faults. Such a procedure is developed in this article and referred to as a path unselection procedure. The procedure performs linear-time traversals of the circuit to unselect fan-out branches, and thus exclude from consideration paths that are shorter than the ones it keeps. It also uses available information about detectable and undetectable path delay faults to unselect fan-out branches or avoid unselecting them. To demonstrate its use, the procedure is applied to benchmark circuits as part of an iterative test generation procedure whose goal is to target manageable numbers of the longest path delay faults.

Test points are inserted into a circuit to improve its testability or diagnosability. The diagnosability goal may be to reduce the number of indistinguished fault pairs, increase the accuracy of logic diagnosis, or reduce the number of diagnostic tests. This article describes a test point insertion procedure, combined with a test compaction procedure, whose goal is to reduce the number of tests in a diagnostic test set, and bring it closer to the number of tests in a fault detection test set. A test point allows a fan-out branch to assume values that are different from those of the fan-out stem. Effectively, the fan-out branch becomes an independent input. The test compaction procedure reduces the number of tests in two ways: 1) by utilizing the extra inputs created when test points are inserted and 2) a diagnostic test set typically consists of a fault detection test set followed by diagnostic tests. The test compaction procedure modifies the diagnostic test set to use all the tests as both fault detection and diagnostic tests. Experimental results for single stuck-at faults in benchmark circuits demonstrate the effectiveness of this approach in producing diagnostic test sets whose numbers of tests are closer to those of compact fault detection test sets while preserving the accuracy of logic diagnosis.

In a design that consists of several logic blocks, each logic block may be tested separately using its own compressed test set and on-chip decompression logic. The decompression logic is typically based on a linear circuit, such as a linear-feedback shift register (LFSR), and tests are compressed into initial states (seeds). This article observes that even if different LFSRs of different lengths are used for different logic blocks, there is flexibility to select compressed tests that can be shared among the logic blocks. This article describes a test compaction procedure that accepts compact compressed test sets computed for the logic blocks individually. The procedure combines the test sets into a single test set and optimizes it considering all the logic blocks together. This is important for applications where storage of tests is a bottleneck. Experimental results are presented to demonstrate the effectiveness of the test compaction procedure when groups of benchmark circuits are considered as logic blocks in the same design. A procedure for constructing groups with significant sharing of compressed tests is also discussed.

Test data compression allows compressed tests to be stored on a tester and decompressed on-chip. Test data compression has not been applied before to transparent-scan sequences in spite of their ability to provide test compaction beyond conventional scan-based tests. A transparent-scan sequence$T$can be obtained from a conventional compact scan-based test set$C$. In this case, the length of$T$is equal to the number of clock cycles required for applying$C$. Test compaction applied to$T$can reduce its length well below the number of clock cycles required for$C$. To allow test data compression and test compaction to be applied together to a transparent-scan sequence, this brief defines a format for a conventional compressed scan-based test set$C$that supports features of a compact transparent-scan sequence, and allows a compact transparent-scan sequence$T$to be obtained from$C$. Using this format, compaction of$T$is achieved by modifying certain parameters of$C$. The decompression logic remains similar to the conventional logic used for$C$. Experimental results for the set of single stuck-at faults in benchmark circuits demonstrate significant reductions in the length of$T$starting from a compressed and compacted scan-based test set$C$.

Logic built-in self-test (LBIST) is important for in-field testing. In a storage-based LBIST approach, deterministic test data are stored on-chip and used for applying tests that are closer to deterministic tests than pseudorandom tests. Using the same stored test data for applying several different tests allows the volume of test data stored on-chip to be reduced, and the fault coverage to be increased. This observation was applied earlier in two ways: 1) by complementing bits of stored test data or applied tests to form additional tests and 2) by forming different tests from different combinations of stored test data entries that are obtained by partitioning deterministic tests. Partitioning was applied earlier to uncompressed deterministic tests. In this article, partitioning is applied for the first time to compressed deterministic tests. Under the resulting LBIST approach, tests are formed on-chip using pseudorandom combinations of partitioned compressed tests. A software procedure is described for deriving a reduced set of test data entries for on-chip storage. With compressed tests, the storage requirements are already reduced, and they are reduced further by the software procedure. Experimental results demonstrate the effectiveness of this LBIST approach considering both single stuck-at and single-cycle gate-exhaustive faults in benchmark circuits.

Fail data collection is carried out for faulty units to allow defect diagnosis to be performed. After passing scan chain tests, fail data collection targets faults in the functional logic. Several approaches addressing the fail data collection process on the tester were developed to ensure that the volume of fail data collected for faulty units with defects in the functional logic is manageable. In addition, the collection of compacted output responses reduces the fail data volume, and the fail data volume can be reduced further by compressing it. This article complements these approaches by considering the storage scheme for fail data, observing that the same fail data may be shared by different faulty units. By storing shared fail data only once, the fail data volume can be reduced. Sharing of fail data occurs when the fail data for a faulty unit$u_{j}$is contained in the fail data for a faulty unit$u_{i}$. It also occurs when the intersection of the fail data for$u_{i}$and$u_{j}$is nonempty. If there is no faulty unit whose fail data is contained in the intersection, and the sharing is significant, the article defines a dummy faulty unit$u_{k}$with fail data equal to the intersection. This article develops these observations into a storage scheme for fail data. The experimental results for simulated faulty units based on benchmark circuits demonstrate significant reductions in fail data volume.

A logic diagnosis procedure produces a set of can-didate faults that are expected to identify the defects present in a faulty chip. To reduce the number of candidates produced, diagnostic tests are often needed. The use of diagnostic tests increases the storage requirements of a test set. Earlier works reduced the input storage requirements of a fault detection test set by using each stored test to apply several different tests. When applied to diagnostic tests, the tests were selected by performing diagnostic fault simulation of a basic fault model. In this paper, we apply this approach to target large sets of candidate faults produced by a logic diagnosis tool. A procedure for the selection of a subset of the available tests to be used as diagnostic tests is described. Experimental results for simulated defects in benchmark circuits and the logic blocks of an OpenSPARC T1 microprocessor show that the diagnostic test set selected using our approach produces better diagnosis results, with a minimal increase in input storage, compared to a diagnostic test set produced by a commercial tool.

Test sets that target several fault models are important for addressing the need to achieve comprehensive defect coverage. A commonly used test generation process tops off the test set to address the fault models one by one. However, if the test set becomes excessively large, the order by which the fault models are targeted creates a bias in their fault coverages. This article considers the scenario where (1) a bound on the number of tests is introduced in advance, and (2) after targeting a fault model$F_{0}$, the detection of faults from fault models$F_{1}$and$F_{2}$is equally important for improving the quality of the test set. The article introduces a test generation objective that balances the detection of faults from$F_{1}$and$F_{2}$to reduce the bias toward one of them. It then describes a test generation procedure that uses the objective to produce a balanced test set in the case where a compressed test set for$F_{0}$(consisting of single stuck-at faults) is used for producing all the tests for$F_{1}$and$F_{2}$(consisting of single-cycle gate-exhaustive faults and bridging faults, respectively). Experimental results for benchmark circuits are presented to support the discussion.

Tests for path delay faults are important for covering small delay defects whose cumulative effect causes a circuit to fail. The number of path delay faults, and the number of tests for them, may be large even when a path selection criterion requires the detection of a path delay fault through every line in the circuit. This article suggests a refinement of this criterion that targets a uniform coverage of the circuit using path delay faults. To address this target, the test generation procedure finds contiguous subcircuits whose lines are uncovered by path delay faults, and targets path delay faults through the largest such subcircuits. When a path delay fault is detected, the subcircuit it goes through is partitioned into smaller subcircuits. The sizes of the resulting subcircuits are evaluated in advance to select the path delay faults with the largest impact on coverage. Experimental results for benchmark circuits use a transition fault test set as a baseline, and demonstrate that a limited number of additional tests can improve the coverage of the circuit significantly based on this criterion.

The approximate computing paradigm supports yield improvement by allowing imperfect components to be used for computations that can tolerate imprecision. Applying the same arguments to the scan logic, a circuit with faults in the scan logic does not need to be discarded if it is possible to ascertain that the circuit will work correctly during functional operation. This article takes several steps toward a solution that allows circuits with faults in the scan logic to be used. It provides conditions under which a circuit with faults in the scan logic is usable. It also suggests how to extend a test set for fault detection targeting the functional logic to provide the fault detection capabilities needed to ascertain that a circuit with faults in the scan logic is usable. The transparent-scan approach is used for this purpose. Experimental results for benchmark circuits demonstrate some of the effects of this approach.

Improving the quality of a test set without storing additional tests is important when a higher fault coverage is required but test data storage is limited. Such an improvement can be achieved by using every test in a base test set to apply several different tests. In this paper, we consider the case where a base test set for basic faults is used for detecting more complex faults. Depending on the operators used for producing different applied tests, the number of options available for applied tests can be large. In such cases it is necessary to select a subset of applied tests from all the available ones. We develop algorithms for solving this problem in two scenarios. In the first scenario additional coverage is required for a small subset of faults associated with specific gates. In the second scenario additional coverage is required for the entire circuit. Experimental results are presented for benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor to demonstrate the effectiveness of these algorithms.

Bounded transparent-scan supports test compaction beyond that achievable with conventional scan-based tests. This article considers the compression of bounded transparent-scan tests. All the components of a test (scan-in state, primary input vector, scan-in and scan-enable sequences) are produced by the on-chip decompression logic from a compressed test. The article describes a test compaction procedure that starts from a conventional compressed and compacted multicycle scan-based test set. Such a test set benefits from test data compression and test compaction applicable to conventional scan-based tests. The procedure modifies as many tests as possible into compressed bounded transparent-scan tests to reduce the number of tests, the storage requirements, and the number of clock cycles required for test application. Experimental results for benchmark circuits demonstrate the ability to compress bounded transparent-scan tests and achieve test compaction.

A typical VLSI design flow is iterative, implying that performance, power, area and testability are improved iteratively. With the shift left paradigm, most of the changes made to a design, including to a large extent changes to address testability, occur at the RTL. Test generation is an exception with a gate level netlist being required by ATPG tools. Within an iterative flow, repeated ATPG to reevaluate the testability of a design after its RTL has been changed becomes a bottleneck. To address this bottleneck, the test generation process needs to transform a test set generated for an earlier version of the design into a test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design. The main contribution of the paper is to compute such a mapping after RTL changes and resynthesis produce a new gate level netlist, where signal names may have changed, new signals may have been introduced, and signals that existed earlier may have been removed. Experimental results for industrial circuits with changes made at the RTL show an average of 5-fold reduction in test generation time.

The variety and complexity of defects that occur in manufactured circuits require test sets that detect a variety of fault models. Two approaches to the generation of such test sets exist: targeting several different fault models for test generation directly, or generating an$n$-detection test set where every modeled fault is detected by$n$different tests. This article observes that it is possible to combine the advantages of both approaches by using an$n$-detection test set as a baseline where a known number of tests provides an initial coverage for a variety of fault models. The test set can be made more specific to fault models of interest by replacing tests that only contribute to the number of detections with tests that detect modeled faults. As part of the test generation procedure based on this concept, the article introduces a procedure that condenses the detected faults into a subset of tests, leaving other tests available for replacement or to retain$n$-detection tests. Experimental results are presented for benchmark circuits using four different fault models to demonstrate the effectiveness of this approach.

This paper describes a fast test generation process for digital circuits that exhibit extensive structural similarity. The property of structural similarity can be seen in circuits that are subjected to engineering change order (ECO), circuits that are modified during place and route, circuits subjected to retiming, and circuits with multiple similar cores. The goal of the paper is to determine the testability of a circuit (circuit2) given a test set for a structurally similar circuit (circuit1). This is achieved by transforming a test set generated for circuit1 into a test set for circuit2 as efficiently as possible, without repeating the entire test generation process. The process described in the paper starts with a structural analysis of circuit1 and circuit2 to obtain a mapping between their inputs and outputs. The mapping is used for transforming test patterns from circuit1 into test patterns for circuit2. The experiments conducted on industrial designs show an average of more than 10-fold reduction in runtime, compared with running the entire test generation process for circuit2.

As a superset of cell-aware faults, gate-exhaustive faults provide a target for the generation of a comprehensive test set. Considering two-cycle gate-exhaustive faults, the number of faults can be excessive, and many of the faults are undetectable. This article considers the efficient identification of undetectable two-cycle gate-exhaustive faults. To take advantage of the large numbers of necessary assignments the faults have, the procedure described in this article is based on the computation of input necessary assignments. This article also notes that gates with large percentages of undetectable two-cycle gate-exhaustive faults are more important to target for test generation. Experimental results are presented for such gates in benchmark circuits.

Transparent-scan enhances test compaction by allowing scan shift and functional capture cycles to be interleaved in arbitrary ways, and using both types of clock cycles for detecting faults. An initial transparent-scan sequence$T$can be obtained by translating every clock cycle of a compact scan-based test set$C$into a test vector of$T$. This sequence can then be compacted to achieve a lower number of clock cycles than that required for$C$. A bottleneck in the compaction of$T$is the need to perform repeated sequential fault simulation. This article makes the new observation that a transparent-scan sequence contains independent subsequences, where fault detection is not influenced by and does not influence the rest of the sequence. The article focuses on independent subsequences at the end of$T$, referred to as independent suffixes. The test compaction procedure described in this article identifies the shortest independent suffix, compacts it without considering the rest of the sequence, and moves it to the beginning of the sequence. This is repeated as long as new independent suffixes are obtained. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

Volume logic diagnosis is typically applied in two phases. In the first phase, a fault detection test set is used for collecting fail data and performing logic diagnosis. If the fail data based on a fault detection test set is not sufficient for accurate logic diagnosis, a faulty unit is considered again in the second phase with a larger diagnostic test set. When diagnostic tests are generated, the defects present in the faulty units they target are unknown, and the tests are generated for target faults. This article suggests that the use of multicycle tests with the same input test data (scan-in states and primary input vectors) as the tests in a fault detection test set can address this issue. Under the approach suggested in this article, a multicycle test is considered useful for diagnosis when it causes the faulty unit to produce more fail data than tests with fewer cycles and the same input test data. The volume of fail data is obtained directly from the faulty unit and does not require the use of target faults. This article discusses the tester support needed for this approach, and its effect on the logic diagnosis procedure. It presents experimental results for benchmark circuits to demonstrate the extent to which it is effective.

Path delay faults model small delay defects that affect the operation of the circuit when they accumulate along a path. For lines on a path, the propagation conditions can be related to those of transition faults. Two-cycle defect-aware, cell-aware and gate-exhaustive faults model delay defects with more complex activation conditions than transition faults. This article observes that detecting gate-exhaustive faults along a path results in the detection of small delay defects with more complex activation conditions than transition faults. Such path delay faults are referred to as gate-exhaustive path delay faults. This article defines gate-exhaustive path delay faults and describes a path selection procedure to support test generation. The experimental results for benchmark circuits demonstrate the possibility of detecting gate-exhaustive path delay faults.

Storing deterministic test data on-chip allows logic built-in self-test (LBIST) to produce a special type of random test that consists of random combinations of deterministic test data. Such tests can achieve a higher fault coverage than random tests whose bits are determined randomly. A bottleneck of this approach is the volume of test data that needs to be stored. This article observes that the use of multicycle tests can address this bottleneck by reducing the number of tests needed for detecting target faults and, thus, the volume of test data needed for producing them. A software procedure is described to support this solution. Experimental results for benchmark circuits demonstrate the effectiveness of multicycle tests in this context.

Logic diagnosis to support yield improvement requires the collection of fail data. The full fail data for a faulty unit consist of the tests and observable outputs where the faulty unit produces faulty values. The volume of fail data that needs to be collected can be excessive. A recent solution is to use only pass/fail data for as many tests as possible. With pass/fail data for a test, the full fail data is replaced with a single bit that indicates whether the faulty unit passed or failed the test. However, with conventional scan-based tests, some tests require the full fail data to preserve the diagnostic quality of the test set. This article observes that the use of scan-based tests under bounded transparent-scan increases the diagnostic quality achievable using only pass/fail data. The article describes a test generation procedure for bounded transparent scan that uses only pass/fail data, and targets the same diagnostic quality as a conventional scan-based test set with full fail data. The experimental results demonstrate that, for many of the benchmark circuits considered, a bounded transparent-scan test set with pass/fail data matches the diagnostic quality of a conventional scan-based test set with full fail data.

Undetectable faults result from logic redundancies and constraints on applicable tests. The presence of an undetected (undetectable or aborted) fault implies that a test, which would have covered its site, is missing from the test set. When undetected transition faults form a path, the missing tests imply that (small) delay defects along the path may not be detected even if they are detectable. The goal of this article is to provide additional coverage for paths of undetected transition faults by using two-cycle gate-exhaustive faults for subcircuits (gates) that wrap the paths. The use of gate-exhaustive faults alleviates the need to model delay defects along the paths, or use path delay faults that may also be undetectable. The article defines the target paths, and gates that wrap them, for which two-cycle gate-exhaustive faults can be defined. Experimental results for benchmark circuits demonstrate the discussion.

Defect-aware, cell-aware, and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an \( n \) -input subcircuit can have up to \( 2^n \) faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by \( T_1 \) obtained after truncating a larger test set denoted by \( T_0 \) . Suppose that the truncation reduces the set of detected faults from the set denoted by \( D_0 \) to the set denoted by \( D_1 \) . The procedure described in this article modifies the tests in \( T_1 \) to gain the detection of faults from \( D_0 \) \( \setminus \) \( D_1 \) , even at the cost of losing the detection of faults from \( D_1 \) . The goal is to reduce the fault coverage loss by computing a test set denoted by \( T_2 \) that detects a set of faults denoted by \( D_2 \) such that \( |T_2| = |T_1| \) and \( |D_2| \gt |D_1| \) . Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.

A test compaction procedure under transparent scan can compact a scan-based test set that contains a minimum number of tests. The additional test compaction can be important in applications that require highly compacted test sets. Transparent scan views a scan-based test set as a sequence of scan shift and functional capture cycles and allows the two types of clock cycles to appear in arbitrary sequences. The contribution of this brief is to suggest that one of the reasons for the effectiveness of transparent scan for test compaction is its ability to prepone fault detections by replacing scan shift with functional capture cycles when faults are activated during scan shift cycles. When fault detections are preponed, clock cycles around the original detection clock cycles become unnecessary and can be omitted. This view results in a new test compaction procedure that focuses on steps that contribute to test compaction, thus reducing the computational effort of test compaction compared with general-purpose test compaction procedures.

Functional test sequences are used as manufacturing tests to complement scan-based tests. Functional test sequences target defects in the functional logic of the circuit. However, they may fail because of defects in the scan logic that prevent the circuit from operating correctly in functional mode. It is advantageous to detect such defects by dedicated test sequences before attempting to apply functional test sequences. The computation of dedicated test sequences for faults in the scan logic is the topic of this brief. The procedure described in this brief accepts a pool of functional test sequences. It identifies subsequences from the pool that are effective for detecting faults in the scan logic while balancing their lengths. It then compacts the sequences to reduce their total length further. Experimental results for benchmark circuits demonstrate large variations among different circuits in the total length of the sequences and significant reductions in the total length for all the circuits considered.

Scan-based tests were shown to create nonfunctional operation conditions that can cause a fault-free circuit to exhibit the appearance of a delay fault. Scan-based tests that are extracted from functional test sequences avoid nonfunctional operation conditions during their functional capture cycles and are referred to as functional scan-based tests. This brief observes that the stuck-at fault coverage of functional single-cycle tests is significantly higher than the transition fault coverage of functional launch-on-capture (LOC) tests that are extracted from the same sequences. To bridge the fault coverage gap, this brief describes a procedure that extracts both functional LOC and close-to-functional launch-on-shift (LOS) tests together from functional test sequences. The LOS tests have the unique property that their functional capture cycles consist of functional single-cycle tests. Experimental results for benchmark circuits show significant reductions in the fault coverage gap between stuck-at and transition faults.

When test data compression uses a linear-feedback shift-register (LFSR) for on-chip decompression, stored tests consist of seeds for the LFSR. Extra clocking of an LFSR seed, bringing the LFSR to one of its next-states, was shown to allow several different tests to be applied based on every stored test, thus reducing the number of seeds that need to be stored, or increasing the fault coverage. Extra clocking that brings the LFSR to its next-states is referred to as positive extra clocking. Only this type of clocking was used earlier. This article suggests to replace a seed by a previous state of the LFSR as a way to increase the effectiveness of this approach without changing the test application process. The computation of previous states is referred to as negative extra clocking. The procedure described in this article uses negative extra clocking to replace seeds with previous states while adjusting the positive extra clocking of the seeds. Experimental results are presented for benchmark circuits to demonstrate the importance of negative extra clocking in reducing the number of seeds that need to be stored.

Storing compressed tests reduces the storage requirements of a test set. For additional reductions in the input storage requirements, earlier works use every stored test to apply several different tests. This allows the number of stored tests to be reduced without reducing the number of applied tests, achieving the same fault coverage with lower input storage requirements. This paper studies such an approach for a diagnostic test set, which is important for yield learning. The set of compressed tests is partitioned into ones that are important for fault detection, and ones that are added for defect diagnosis. The compressed fault detection tests are first used to produce additional diagnostic tests, thus reducing the need to store compressed diagnostic tests directly. If necessary, compressed diagnostic tests are added to the set of stored tests, and used for applying additional diagnostic tests. Experimental results for benchmark circuits demonstrate the effectiveness of this approach in reducing the input storage requirements of a diagnostic test set.

Dynamic test compaction procedures use independent fault sets to guide the generation of compact test sets. In addition, a maximal independent fault set provides a lower bound on the number of tests, and can thus be used for evaluating the level of test compaction. This article notes that defect-aware, cell-aware, and gate-exhaustive faults have certain properties that can be used in the computation of independent fault sets. This article focuses on gate-exhaustive faults and the computation of a maximal independent fault set. The experimental results for benchmark circuits support the discussion.

A comprehensive test set targets faults of different types to ensure that defects of different types are detected. When test compaction is carried out for such a test set, it is advantageous if the compacted test set contains a compact test set for each fault type separately. In this case, if one (or more) of the fault types is found to be more important to detect, a compact test set for it can be extracted without further processing. This article describes the first test compaction procedure for transition and stuck-at faults, where by construction, the compact test set contains compact test sets for each fault type separately. The experimental results for benchmark circuits demonstrate the ability to compact a comprehensive test set under this condition.

In a commonly used test data compression method, the on-chip decompression logic is based on a linear-feedback shift-register ( LFSR), and compressed tests consist of seeds for the LFSR. A seed can be modified and used for applying several different tests. This reduces the input test data volume further than the basic test data compression method. In this context, this article introduces a new approach for applying several different tests based on every seed. The new approach pads a seed in different ways to obtain new seeds for LFSRs with more bits, all of which can be implemented by a single programmable LFSR. The advantage of using LFSRs with more bits is that they are effective in detecting more target faults, thus supporting test compaction together with a reduction in the input test data volume. The experimental results for benchmark circuits demonstrate these points.

Built-in self-test (BIST) approaches are suitable for in-field testing since they do not require a tester for storage and application of test data. They also reduce the security vulnerabilities associated with loading and unloading of external test data into scan chains. As technologies evolve, in-field testing needs to address more complex defect and aging mechanisms that require specific deterministic tests. This can be addressed by BIST approaches that store test data on-chip and use the data for on-chip generation of both random and deterministic tests. In this case, there is a tradeoff between the amount of stored test data and the comprehensiveness of the test set that can be applied. This article explores this tradeoff in a specific context that has the following main features: 1) the initial stored test data is based on a stuck-at test set; 2) the target faults are single-cycle gate-exhaustive faults; and 3) the stored test data is enhanced gradually by test data based on a gate-exhaustive test set to increase the coverage of gate-exhaustive faults.

Fail data is collected by a tester from faulty units to allow defect diagnosis to be carried out. The fail data describes the full output response of the unit. The volume of fail data that faulty units produce during volume diagnosis can exceed the tester memory capacity. Existing solutions stop the fail data collection for a faulty unit after sufficient fail data has been collected or modify the test set to produce less fail data. This article considers the format for storing fail data on the tester. This article suggests a hybrid approach, where full output responses are stored for some tests, and only pass/fail information is stored for the remaining tests. This article describes procedures based on diagnostic fault simulation to determine a subset of tests for which full output responses are needed and for adding new tests such that fewer tests in the extended test set would require full output responses. The experimental results for benchmark circuits demonstrate the reductions in fail data volume that can be achieved by a hybrid approach.

Functional broadside tests were developed to avoid overtesting of delay faults. The tests achieve this goal by creating functional operation conditions during their functional capture cycles. To increase the achievable fault coverage, close-to-functional scan-based tests are allowed to deviate from functional operation conditions. This article suggests that a more comprehensive functional broadside test set can be obtained by replacing target faults that cannot be detected with faults that have similar (but not identical) detection conditions. A more comprehensive functional broadside test set has the advantage that it still maintains functional operation conditions. It covers the test holes created when target faults cannot be detected by detecting similar faults. The article considers the case where the target faults are transition faults. When a standard transition fault, with an extra delay of a single clock cycle, cannot be detected, an unspecified transition fault is used instead. An unspecified transition fault captures the behaviors of transition faults with different extra delays. When this fault cannot be detected, a stuck-at fault is used instead. A stuck-at fault has some of the detection conditions of a transition fault. Multicycle functional broadside tests are used to allow unspecified transition faults to be detected. As a by-product, test compaction also occurs. The structure of the test generation procedure accommodates the complexity of producing functional broadside tests by considering the target as well as replacement faults together. Experimental results for benchmark circuits demonstrate the fault coverage improvements achieved, and the effect on the number of tests.

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a launch-on-shift (LOS) test that is guaranteed to detect the same stuck-at faults without any logic or fault simulation. The LOS test also detects transition faults. This was used for obtaining a compact LOS test set that detects both types of faults. In the scenario where LOS tests are used for both stuck-at and transition faults, this article observes that, under certain conditions, the detection of a stuck-at fault guarantees the detection of a corresponding transition fault. This implies that the two faults are equivalent under LOS tests. Equivalence can be used for reducing the set of target faults for test generation and test compaction. The article develops this notion of equivalence under LOS tests with equal primary input vectors and provides an efficient procedure for identifying it. It presents experimental results to demonstrate that such equivalences exist in benchmark circuits, and shows an unexpected effect on a test compaction procedure.

Yield improvement requires information about the defects present in faulty units. This information is derived by applying a logic diagnosis procedure to the fail data collected by a tester from faulty units. It is typical in the early stages of yield learning to find faulty units that produce excessive volumes of fail data. The current practice is to terminate the fail data collection and possibly discard the fail data already collected for the unit. An earlier study shows that a faulty unit may produce excessive volumes of fail data for some tests but not for others. Based on this observation, a possible solution is to collect full fail data only for tests where this is feasible and pass/fail information for other tests. For this approach to be practical, it is necessary to be able to perform logic diagnosis with hybrid fail data that consists of full fail data for some tests and only pass/fail information for other tests. The main challenge in designing such a procedure is to balance the use of the two types of data to produce accurate logic diagnosis results. This article describes a logic diagnosis procedure, from the class of procedures used by commercial tools, that addresses this challenge. Experimental results for benchmark circuits demonstrate the importance of pass/fail information in this scenario.

Multicycle tests have several advantages including the ability to support test compaction. By extracting multicycle functional broadside tests from functional test sequences, it is possible to ensure functional operation conditions during the functional capture cycles between the scan operations of a test. The challenge that this article addresses is that the computational effort of extracting l-cycle functional broadside tests from a functional test sequence increases linearly with l. Therefore, the computational effort of a test generation procedure that increases l gradually to match l to the circuit is quadratic in l. This makes it infeasible to consider large values of l that are important for test compaction. To address this challenge the paper develops a partitioning procedure under which test extraction requires the same computational effort for every l. This article also describes a test generation procedure that is linear in l. Experimental results for transition faults in benchmark circuits demonstrate the importance of large values of l for test compaction.

Multicycle tests are useful for test compaction even when full scan allows single- or two-cycle tests to be used. To avoid sequential test generation, multicycle tests can use the test data (scan-in states and primary input vectors) from a single- or two-cycle test set, possibly modified to make it more suitable for multicycle tests. However, the modification process requires repeated fault simulation to prevent a loss of fault coverage. This brief observes that the need to modify test data results from the fact that tests are only extended forward to increase their numbers of clock cycles starting from their (modified) scan-in states. The brief observes further that extending tests backward is a more computationally efficient way of obtaining multicycle tests with modified test data. The brief defines a new type of multicycle test to increase the effectiveness of backward extension and describes a test compaction procedure based on backward and forward extension. It presents experimental results for gate-exhaustive faults, requiring large numbers of tests, in benchmark circuits.

Two-cycle gate-exhaustive faults provide a comprehensive model for delay defects that are localized to gates (cells or subcircuits). However, the number of two-cycle gate-exhaustive faults can be excessive. Cell-aware faults are obtained by performing layout analysis of cells to select faults that are important to detect. This article suggests a complementary view of faults that are important to detect. Under this view, a two-cycle gate-exhaustive fault is important to detect if it can affect the circuit during functional operation. Such faults can be identified by generating functional broadside tests. To obtain unconstrained two-cycle tests, which are more compact and detect more faults than functional broadside tests, the article uses a test generation procedure that extracts test cubes from functional broadside tests, merges the test cubes into tests, and derives both broadside and skewed-load tests from the resulting test data. The procedure is iterative to allow a gradual increase in the number of tests and the number of detected two-cycle gate-exhaustive faults. Experimental results for benchmark circuits demonstrate the tradeoff explored by the procedure.

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used.

Built-in self-test (BIST) eliminates the need for an expensive tester, and reduces the security vulnerabilities of scan design. This paper describes a BIST approach that combines the following features. (1) It is based on storage of test data on-chip to achieve complete fault coverage. (2) Every entry of the stored test data is used for applying several different tests to reduce the amount of stored test data. (3) The test data is derived from functional broadside tests, and the applied tests maintain close-to-functional operation conditions to avoid overtesting of delay faults. Experimental results are presented for benchmark circuits to demonstrate the effectiveness of this approach.

The hardware design process adds, at each level, scaffolding logic to aid test, debug and engineering changes. Fault injection attacks can place a design in a non-functional state where the scaffolding is utilized for obtaining information that is not intended for the user. To counter such security threats, this paper suggests to include in the design logic that will identify invalid state patterns, and reset or hold a sufficient part of the state to prevent useful computations from occurring. To support such a solution, the paper also suggests that the fault coverage of a scan-based test set in the presence of single stuck-at faults can be used for designing the reset and hold logic. Such a test set relies on the use of non-functional states for fault detection. Without using the reset and hold logic, the test set achieves a high fault coverage (over 80% in the experiments reported in this paper). When the reset and hold logic is used, the fault coverage of the same test set is reduced below a preselected target (30% in the experiments reported in this paper). The reduction in the fault coverage occurs because much of the non-functional state space is no longer available. This also eliminates the security risk associated with these states.

A large number of paths necessitates the selection of path delay faults for test generation. The selected path delay faults should be detectable, and associated with the longest paths of the circuit. This paper introduces a new consideration that is important for the selection of path delay faults, namely, the extent to which a path delay fault can be activated during functional operation. This is important since certain paths that cannot be activated during functional operation may not be optimized for speed. To address this issue, the paper describes a path selection procedure that uses functional broadside tests to identify functional path delay faults. The procedure selects target path delay faults that are associated with the longest paths, and are as similar as possible to functional path delay faults. Experimental results for benchmark circuits demonstrate the levels of similarity.

Test data compression methods reduce the input storage requirements of a test set by storing compressed tests. To enhance the ability to reduce the input test data volume, earlier approaches use the same input test data to apply several different tests. This paper considers two methods that have not been used before for this purpose. The methods are considered in the context where a linear-feedback shift-register (LFSR) is used as part of the decompression logic, and tests are compressed into seeds for the LFSR. The first method complements a bit of a seed to obtain a different test than the one produced by the uncomplemented seed. The second method uses the same seed for different LFSRs to produce different tests. The two methods are used together to demonstrate the advantages of a hybrid approach where the methods complement each other. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of a hybrid approach.

A test set for transition faults detects smaller delay defects if transition faults are detected through longer paths. Conversely, this paper observes that it is advantageous for a test set for path delay faults, which targets small delay defects, to detect larger delay defects along the paths. The paper defines a notion of masking that prevents larger delay defects from being detected. It defines a non-masking non-robust test for a path delay fault that guarantees the detection of larger delay defects along the path. It also defines masking metrics that allow the level of masking of larger delay defects for a test, and a test set, to be evaluated. Using these metrics, the paper describes a procedure that computes a test set for path delay faults with reduced levels of masking for larger delay defects. Experimental results are presented to demonstrate the extent to which masking of larger delay defects occurs under tests for path delay faults in benchmark circuits.

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits.

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional.

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations.

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a skewed-load test that detects the same stuck-at faults without performing logic or fault simulation. By using this transformation, it is possible to generate a compact skewed-load test set for stuck-at and transition faults. The advantage for test compaction is related to the fact that the test set contains a single test type. For cases where broadside tests are preferred over skewed-load tests, this article studies the possibility of transforming a single-cycle test into a broadside test, and generating a compact broadside test set for stuck-at and transition faults. This article addresses several challenges in order to achieve this goal without resorting to sequential test generation or state justification that have a high computational complexity. The experimental results for benchmark circuits demonstrate the levels of test compaction that can be achieved using small numbers of observation points.

Maintaining functional operation conditions during the application of scan-based tests is important for avoiding overtesting of delay faults. This issue has been considered for the functional capture cycles of scan-based tests, where the faults are typically detected. When scan shift cycles are used for fault detection, functional operation conditions are important during scan shift cycles as well. A transparent-scan sequence allows both types of clock cycles to be considered uniformly, allowing faults to be detected during functional capture as well as scan shift cycles. This article defines the concept of a globally functional transparent-scan sequence that maintains close-to-functional operation conditions during all its clock cycles. The procedure described in this article for computing globally functional transparent-scan sequences starts from a transparent-scan sequence that avoids scan shift cycles in order to maintain functional operation conditions. The procedure introduces scan shift cycles into the sequence in order to detect target faults. This process is guided by a transparent-scan sequence that is translated from a conventional scan-based test set and achieves the same fault coverage. Experimental results for benchmark circuits demonstrate the tradeoff between the proximity to functional operation conditions and the fault coverage achievable by the globally functional transparent-scan sequence.

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets.

Under broadcast scan, scan chains are partitioned into groups that receive the same scan-in values. This article considers, for the first time, the application of functional broadside tests under broadcast scan. This article provides a definition of a close-to-functional broadside test that is applicable under a broadcast scan configuration. The test is referred to as a group-functional broadside test. This article describes how a subset of group-functional broadside tests is obtained from a functional broadside test and discusses the proximity to functional operation conditions that a group-functional broadside test maintains. It also describes the generation of a group-functional broadside test set. The experimental results for transition faults in benchmark circuits explore the tradeoff between the level of test data compression, the proximity to functional operation conditions, and the transition fault coverage, by considering scan configurations with different numbers of scan chains.

Using both broadside and skewed-load tests for delay faults provides a higher fault coverage and more compacted test sets. An earlier work showed that it is possible to share input test data between broadside and skewed-load tests, and thus reduce the input test data volume. This article develops an algorithm for computing stored tests that can be used for applying both broadside and skewed-load tests in the context of a specific test data compression method. Under this method, a programmable linear-feedback shift register is used for on-chip decompression. In the stored test data, a stored test consists of a seed and two primary input vectors. The seed determines the scan-in state of the applied broadside or skewed-load test as well as the additional scan-in vector required for a skewed-load test. In the algorithm developed in this article, stored tests are computed directly without first computing broadside or skewed-load tests. This avoids situations where the tests cannot be compressed or do not have common input test data.

Fail data is collected on a tester to allow defect diagnosis to be carried out. The high volume of fail data that some faulty units produce, and the test application time, motivated the development of procedures for terminating the fail data collection process before it stores the entire fail data for a faulty unit. A procedure for modifying a test set to reduce the fail data volume it produces was developed to complement these approaches, but without considering the constraints of a test data compression method. This article describes a procedure for modifying a stored test set to reduce the fail data volume under a test data compression method where a linear-feedback shift-register is used for on-chip decompression. The constraints of the test data compression method affect the procedure in several important ways. The experimental results for benchmark circuits demonstrate the ability of the procedure to reduce the fail data volume by modifying a stored test set.

The use of multicycle tests, with several functional capture cycles between scan operations, contributes significantly to the ability to compact a test set. Multicycle tests have the added benefit that they can contribute to the detection of defects with complex behaviors that are not detected by single-cycle or two-cycle tests. To ensure that this benefit is materialized when test compaction is applied to transition faults, this article suggests to incorporate into the test compaction procedure an additional fault model whose fault coverage increases when multicycle tests are used. To ensure that the computational complexity of test compaction is not increased by a fault model with a large number of faults, or faults with complex behaviors, the added fault model is required to have the same characteristics as the transition fault model. A type of transition fault called unspecified transition fault satisfies these requirements. The article describes a test compaction procedure for transition faults that incorporates unspecified transition faults, and presents experimental results for benchmark circuits to demonstrate the levels of test compaction and fault coverage that can be achieved.

Test compaction benefits from the use of multicycle tests that have several clock cycles between their scan-in and scan-out operations. For maximum benefit, primary output vectors should be observed during all the clock cycles between the scan operations of a multicycle test. This allows the test to detect all the faults whose fault effects reach the primary outputs, in addition to the ones whose fault effects are latched onto the flip-flops before the scan-out operation. However, for consistency with single-cycle tests for single stuck-at faults, or two-cycle tests for transition faults, only one primary output vector should be observed per test. This can be the last primary output vector of the test, as in the case of single-cycle and two-cycle tests, but other options are more useful, as demonstrated in this article. In particular, this article suggests that the primary output vector to be observed should be selected individually for every test. It also describes a static procedure for selecting a single primary output vector to observe individually for every test based on a given compact multicycle test set and a dynamic test compaction procedure that produces multicycle test sets with this property.

Test data compression is based on storage of compressed tests and use of on-chip decompression logic for test application. Further reductions in the input test data volume are achieved by methods that apply several different tests based on every compressed test. This article makes the new observation that by keeping the same number of compressed tests and applying several different tests based on every compressed test, it is possible to improve the quality of the test set applied to the circuit. This article studies such an approach for path delay faults (PDFs) using a linear-feedback shift register (LFSR) as the decompression logic. Because of the nature of PDFs, targeting an extended subset of PDFs increases the confidence that important PDFs are detected. However, the benefit of detecting additional faults may not justify an increase in the number of stored tests. The approach suggested in this article is used for detecting an extended subset of target PDFs using the same set of LFSR seeds. Extra clocking of the LFSR is used for obtaining scan-in states for several new two-cycle tests based on the same seed. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

Reverse order fault simulation and its variations provide a test compaction option with a low computational effort that is applicable even when test constraints or complex fault models preclude the application of other conventional test compaction procedures. This is the scenario considered in this brief. Reverse order fault simulation procedures remove unnecessary tests from a test set without otherwise modifying it. Reverse order fault simulation is typically applied once after the complete test set has been generated. This brief observes that when other test compaction procedures are not applied, forward-looking reverse order fault simulation sometimes yields a smaller test set if it is applied more often during the test generation process. However, applying it more often also increases the computational effort. This brief explains this phenomenon and describes a procedure that uses the new insights to improve the ability of forward-looking reverse order fault simulation to achieve test compaction at a reduced computational effort. The experimental results for benchmark circuits are presented to support the discussion.

Test sequences that do not use scan chains have several advantages as manufacturing tests. Test sequences can be produced by sequential test generation procedures, and static test compaction can be applied to reduce the length of the sequence without losing fault coverage. A typical sequential test generation procedure that produces a single test sequence concatenates test subsequences to form the test sequence. Existing static test compaction procedures ignore the construction of the sequence from subsequences and consider every test vector individually for omission. This brief introduces a broad-brush static test compaction procedure that considers entire subsequences for omission to achieve test compaction. As additional subsequences are concatenated, subsequences concatenated earlier may become unnecessary. The procedure described in this brief identifies this situation. The advantage of a broad-brush approach is a low computational effort, which is demonstrated by experimental results for benchmark circuits.

Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.

As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant.

Gate-exhaustive faults address the fact that not all the defect mechanisms and behaviors are known in advance, and not all of them can be translated into fault models. Therefore, it is advantageous to ensure that a test set covers unexpected defects by exhaustive testing of gates or subcircuits. This paper observes that these properties make gate-exhaustive faults suitable for providing extra coverage for sites where coverage is missing because of undetectable target faults from other fault models. Undetectable faults result from logic redundancy, and leave circuit sites uncovered. To allow subcircuits to be considered as gates while avoiding the need to consider large numbers of faults, the gate-exhaustive approach is applied selectively. Instead of using all the input patterns of every gate, the iterative procedure described in this paper uses increasing numbers of input patterns of gates that include undetectable target faults in order to achieve a coverage goal for these faults. Experimental results demonstrate the extent to which it is possible to cover the sites of undetectable single stuck-at faults using tests for gate-exhaustive faults.

Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where they detect delay faults. One of the challenges in the generation of functional broadside tests is test compaction. Existing dynamic compaction approaches for scan tests are not applicable to functional broadside tests, and static compaction approaches are limited in the level of test compaction they can provide. The solution suggested in this paper has two new properties. (1) Instead of attempting to compact functional broadside tests, test compaction is applied to a functional test sequence from which functional broadside tests are extracted. The compact sequence yields a compact functional broadside test set. (2) Compaction of the functional test sequence is performed without sequential fault simulation. This is possible since test compaction does not have to preserve the fault coverage of the functional test sequence. The solution is developed in the scenario where the primary input vectors of a circuit are not constrained during functional operation. Experimental results for benchmark circuits demonstrate its ability to compact a functional broadside test set for transition faults.

This paper studies the concept of bounded transparent-scan to take advantage of the test compaction capabilities of transparent-scan at the significantly lower computational cost of conventional multicycle tests. Transparent-scan considers the scan enable input of a standard-scan circuit as a regular primary input. This allows arbitrary sequences of scan shift and functional capture cycles to be used as part of a transparent-scan sequence, contributing to test compaction. However, it also has the computational cost of sequential fault simulation over all the clock cycles of the test application process. With bounded transparent-scan, tests start and end with scan-in and scan-out operations that do not need to be simulated. Between the scan operations, arbitrary sequences of scan shift and functional capture cycles are allowed to support test compaction. The paper develops a test compaction procedure under bounded transparent-scan, and presents experimental results for benchmark circuits to demonstrate its effectiveness.

Multiple defects are prevalent in early stages of yield improvement for a new technology. When a logic diagnosis procedure is applied to a faulty unit that contains a multiple defect, it sometimes produces a large set of candidate faults. Such a set includes extra candidates that do not match the defect present in the faulty unit. An earlier study indicates that a logic diagnosis procedure may prefer certain faults as candidate faults, causing them to appear as extra candidates in many sets of candidate faults. This points to the possibility of using a small number of observation points to eliminate extra candidates that appear often. This paper takes advantage of this observation to improve the quality of diagnosis by placing observation points. Experimental results for benchmark circuits demonstrate the effectiveness of observation points in reducing large sets of candidate faults.

A diagnostic test generation procedure targets fault pairs in a set of target faults with the goal of distinguishing all the fault pairs. When a fault pair cannot be distinguished, it prevents the diagnostic test set from providing information about the faults, and consequently, about defects whose diagnosis would have benefited from a diagnostic test for the indistinguishable fault pair. This is referred to in this paper as a diagnostic hole. This paper observes that it is possible to address diagnostic holes by targeting different but related fault pairs, possibly from a different fault model. As an example, this paper considers the case where diagnostic test generation is carried out for single stuck-at faults, and related bridging faults are used for addressing diagnostic holes. Considering fault detection, an undetectable single stuck-at fault implies that certain related bridging faults are undetectable. This paper observes that, even if a pair of single stuck-at faults is indistinguishable, a related pair of bridging faults may be distinguishable. Based on this observation, diagnostic tests for pairs of bridging faults are added to a diagnostic test set when the related single stuck-at faults are indistinguishable. Experimental results of defect diagnosis for defects that do not involve bridging faults demonstrate the importance of eliminating diagnostic holes.

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits.

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure.

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan.

Close-to-functional broadside tests are used for avoiding overtesting of delay faults that can result from non-functional operation conditions, while avoiding test escapes because of faults that cannot be detected under functional operation conditions. When a close-to-functional broadside test deviates from functional operation conditions, the deviation can affect the entire circuit. This article defines the concept of a boundary-functional broadside test where non-functional operation conditions are prevented from crossing a preselected boundary. Using the procedure described in this article, the boundary maintains the same values under a boundary-functional broadside test as under a functional broadside test from which it is derived. Indirectly, this ensures that the deviations from functional operation conditions throughout the entire circuit are limited. The concept of a boundary-functional broadside test is extended to skewed-load tests, and to partial-boundary-functional tests. Experimental results are presented for benchmark circuits to demonstrate the fault coverage improvements that can be achieved using boundary-functional broadside and skewed-load tests as well as partial-boundary-functional tests of both types.

The presence of undetectable faults in a set of target faults implies that tests, which may be important for detecting defects, are missing from the test set. This article suggests an approach for addressing missing tests that fits with the rationale for computing an n -detection test set. The artcile defines the concept of an incomplete test that is relevant when a target fault is undetectable. An incomplete test activates the fault but fails to detect it because of one or more assignments that are missing from the test. The procedure described in this article improves the quality of a test set by attempting to ensure that every undetectable fault has n incomplete tests with the smallest possible numbers of missing assignments, for a constant n ≥ 1. The incomplete tests are expected to contribute to the detection of detectable defects around the site of the undetectable fault. The computation of missing assignments for a test is performed in linear time by avoiding fault simulation and considering all the undetectable faults simultaneously. Experimental results demonstrate the extent to which a given test set can be improved without increasing the number of tests.

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

This brief describes a new approach to test compaction under transparent scan. Transparent scan achieves higher levels of test compaction than possible with the conventional scan-based tests by interleaving scan shift cycles and functional clock cycles in arbitrary ways. Earlier approaches relied on the computation of a single transparent-scan sequence, and the omission of test vectors from it. However, a single transparent-scan sequence can be prohibitively long. In the approach described in this brief, a transparent-scan test set consists of several sequences whose lengths are limited. Test compaction is achieved by combining sequences into longer sequences that detect more faults, and removing from the test set entire sequences that become unnecessary. Experimental results for benchmark circuits demonstrate the ability of the procedure to achieve test compaction without creating prohibitively long transparent-scan sequences.

Functional broadside tests avoid overtesting of delay faults that may occur with scan tests. Functional broadside tests can be extracted from a functional test sequence. This paper describes a procedure for extracting a close-to-minimum set of multicycle functional broadside tests from a functional test sequence. The procedure uses a modified sequential fault simulation process to collect information about detectable faults. This process indicates which faults must be detected by scan-out operations of multicycle tests, and which ones can be detected on primary outputs. The procedure uses a set-covering procedure to select a close-to-minimum set of clock cycles for scan-out operations. Every scan-out operation is complemented into a multicycle test. In addition, the procedure selects at most one test for faults that can be detected on the primary outputs. Experimental results are presented for benchmark circuits to demonstrate various features and extensions of the procedure.

In the initial stages of the yield improvement process for a new technology, a faulty unit may contain several defects (a multiple defect). The presence of a multiple defect may cause a state-of-the-art logic diagnosis procedure that is based on simulation and ranking of single modeled faults to produce a large set of candidate faults. Test removal or selection procedures are based on the observation that a large set of candidate faults is obtained when defects interact under certain tests. If the tests are ignored, the accuracy of logic diagnosis is improved. However, when a test is ignored, useful diagnostic information may also be lost. Instead, this brief suggests that it is possible to assign a score to every test based on its contribution to the accuracy of logic diagnosis. The test scores are used for scaling the contributions of the tests to the identification of candidate faults. This results in a reduced set of candidate faults where the faults are identified by tests with higher scores. The procedure requires a single additional logic diagnosis step, with a negligible computational effort. Experimental results are presented for multiple defects in benchmark circuits to demonstrate the effectiveness of the procedure.

Transparent-scan is an approach to test compaction where scan shift cycles and functional capture cycles are interleaved in arbitrary ways as needed for detecting target faults. This is achieved by viewing the scan enable input as a regular primary input that can be assigned arbitrary sequences of zero and one values. This paper notes that transparent-scan leaves an unused combination of the scan enable and scan chain input values. This paper suggests that the unused combination can control design-for-testability logic to achieve better test compaction. At the cost of one additional EXCLUSIVE-OR gate for every state variable, and routing of the scan chain input to all the flip-flops, the extended transparent-scan approach described in this paper allows the values of the next-state variables to be complemented before they are latched in the flip-flops during a functional capture cycle. Extended transparent-scan is developed under bounded transparent-scan, where scan-in and scan-out operations of a conventional scan-based test set are maintained in order to limit the computational cost. Experimental results for transition faults in the functional logic of benchmark circuits demonstrate the additional test compaction that can be achieved with extended transparent-scan. Transition faults in the scan logic are considered as well.

Multicycle tests achieve test compaction by increasing the number of clock cycles between scan operations and reducing the number of tests. Tests in a compact multicycle test set typically have different numbers of clock cycles between their scan operations. This creates an opportunity to improve the test set by increasing the numbers of clock cycles between the scan operations of the tests, without increasing the number of tests and without exceeding a bound L on the number of clock cycles. Motivated by this observation, this paper studies the padding of multicycle broadside and skewed-load tests for transition faults. After padding, all the tests have L clock cycles between their scan operations. This paper makes several observations and defines new types of multicycle tests that are supported by commercial tools to allow padding to be performed without losing fault coverage. The new types of tests can be used for achieving a higher fault coverage, further test compaction, or an improved test set quality within the bound L. This paper develops padding procedures and presents experimental results for benchmark circuits to demonstrate these effects.

Transition faults require scan tests with two functional clock cycles between a scan-in and a scan-out operation to activate the faults and propagate their effects to observable outputs. Multicycle tests, with two or more functional clock cycles between scan operations, provide the following advantages. (1) They potentially increase the defect coverage by exercising the circuit at-speed for several functional clock cycles. (2) They allow test compaction to be achieved. (3) Multicycle tests can address features such as multiple clock domains and partial scan. (4) They create closer-to-functional operation conditions that are important for avoiding overtesting of delay faults.

Gate-exhaustive and cell-aware tests are generated based on input patterns of cells in a design. While the tests provide thorough testing of the cells, the interconnects between them are tested only as input and output lines of cells. This paper defines cell-based faults that allow the interconnects to be tested more thoroughly within a uniform framework that only targets input patterns of cells. In contrast to a real cell that is part of the design, a dummy cell is used for defining interconnect-aware faults. Using a gate-level description of the circuit, a dummy cell contains an interconnect, an output gate of the real cell that drives it, and an input gate of the real cell that it drives. Experimental results for benchmark circuits show that many of the interconnect-aware faults are not detected accidentally by gate-exhaustive tests, and that the quality of the test set is improved by targeting interconnect-aware faults. Here, quality is measured by the numbers of detections of single stuck-at faults in a gate-level representation of the circuit.

Close-to-functional broadside tests create close-to-functional operation conditions during the clock cycles where delay faults are detected in order to avoid overtesting. The requirement for functional operation conditions is relaxed in order to achieve the fault coverage of arbitrary (non-functional) broadside tests, and thus avoid test escapes. Existing procedures for computing close-to-functional broadside tests are based on limited information about the deviations that the tests create from functional operation conditions. Noting that functional broadside tests can be extracted from functional test sequences, this paper defines a new concept of a close-to-functional test sequence from which close-to-functional broadside tests can be extracted. For the resulting tests, the deviations from functional operation conditions are known, and can be bounded, over multiple clock cycles. The paper also describes a procedure for computing close-to-functional test sequences that are effective for the detection of transition faults. Experimental results demonstrate the deviations that need to be allowed in order to achieve the transition fault coverage of an arbitrary (non-functional) broadside test set.

Observation points in the combinational logic of a circuit can aid in the diagnosis of logic defects by reducing the number of indistinguished fault pairs. This paper considers the use of observation points in the combinational logic for the diagnosis of scan chain defects under an approach to test application called transparent-scan. Tests that are used for the diagnosis of scan chain defects include functional capture cycles that propagate the effects of scan chain faults through the combinational logic. Scan chain faults can thus be distinguished based on the values that are propagated in their presence to an observation point in the combinational logic. The procedure for observation point insertion considers the following parameters with respect to scan chain faults: 1) the number of indistinguished fault pairs and 2) the distances, measured in numbers of scan cells, between the faults that cannot be distinguished. With lower distances, a set of candidates for a faulty scan chain is likely to contain faults in the same vicinity of the scan chain. This facilitates failure analysis. Experimental results demonstrate the effectiveness of observation points in the combinational logic for scan chain diagnosis under transparent-scan.

Identical instances of a logic block are included in a design to improve its performance or reliability. This allows instances at close proximity to be tested by comparing their output responses, alleviating the need to know which tests will be applied, or what the fault-free response is. This paper considers an approach to online testing where the primary output sequences of identical finite-state machines that receive the same primary input sequences are compared to detect faults. To address the hardware and delay overheads of bringing one of the machines to the same state as the other before starting the output comparison process, this paper describes an initialization process where only part of the state of one machine is loaded into the other, and subsequences of their common primary input sequences are used for completing the initialization process. A unique feature of this process is that it addresses the situation where the input sequences that are applied during online testing, and the initial state for output comparison, are unknown. With this initialization process it is possible to start the output comparison process at an arbitrary point during functional operation. Experimental results for benchmark circuits demonstrate the percentages of state variables who values need to be loaded from one machine to the other, the fault coverage that can be achieved by output comparison following initialization, and the occurrence of failures in the initialization process.

This paper defines a new type of multicycle tests called autonomous multicycle tests. Similar to multicycle scan-based tests, autonomous multicycle tests include several consecutive functional capture cycles to enhance defect detection and achieve test compaction. Unlike multicycle scan-based tests, an autonomous multicycle test set uses the same initial state for all the tests. During the functional capture cycles of a test, the primary inputs are driven by primary outputs, and the circuit operates autonomously. A test uses a scan-in operation only for the initial primary input vector, and to determine the connection between the primary inputs and outputs. It uses a scan-out operation only for the final primary output vector. This results in reduced overheads related to storage requirements and test application time compared with scan-based tests, and several unique properties that are discussed in this paper. This paper describes a test generation procedure for autonomous multicycle tests that avoids sequential test generation, and presents experimental results to demonstrate the ability of the tests to detect target faults.

Close-to-functional scan-based tests are expected to create close-to-functional operation conditions in order to avoid overtesting of delay faults. Existing metrics for the proximity to functional operation conditions are based on the scan-in state. For example, they consider the distance between the scan-in state and a reachable state (a state that the circuit can visit during functional operation). However, the deviation from functional operation conditions can increase during a test beyond the deviation that is measured by the scan-in state. To ensure that the deviation does not increase, this article introduces the concept of a partially invariant pattern. The article describes a procedure for extracting partially invariant patterns from functional broadside tests whose scan-in states are reachable states. Being partially specified, partially invariant patterns are suitable for test data compression. The article studies the use of partially invariant patterns for linear-feedback shift-register ( LFSR ) based test data compression. Noting that a seed may not exist for a given partially invariant pattern with a given LFSR , the procedure described in this article uses an iterative process that not only matches a seed to a partially invariant pattern, but also adjusts the partially invariant pattern based on the test that the seed produces. The article also addresses the selection of LFSR s for the generation of close-to-functional broadside tests based on partially invariant patterns. Experimental results are presented to demonstrate the feasibility of the procedure.

Earlier works observed that certain primary inputs have preferred values, which help increase the gate-level fault coverage when they appear in a functional test sequence. This article observes that multiplexers present additional opportunities for increasing the fault coverage of a functional test sequence, which are not captured by preferred primary input values. Because multiplexers are prevalent, their effect on the fault coverage can be significant. A static analysis that is independent of any functional test sequence is performed in this article to identify preferred values for the outputs of multiplexers. This is followed by a dynamic analysis that adjusts the select inputs of the multiplexers for a given functional test sequence to ensure that the preferred values appear on the outputs of the multiplexers more often. The analysis yields design-for-testability logic for the select inputs of the multiplexers that have preferred values. The logic is independent of the functional test sequence, and it allows the fault coverage to be increased when the select inputs are not primary inputs, or when the same select inputs are used for different multiplexers. Experimental results are presented to demonstrate that this approach has a significant effect on the fault coverage of functional test sequences.

An earlier work observed that the effectiveness of using several fault models for test generation is increased if the existence of an undetectable fault in one model does not imply that a fault in the same site but from a different model is also undetectable. Based on this observation, a bridging fault model that requires two-cycle tests was defined to provide additional coverage for lines with undetected transition faults, and a set of bridging faults corresponding to undetected transition faults was selected prior to test generation. This paper observes that the effectiveness of this approach is increased if the target faults are updated dynamically during test generation. This creates fewer cases where faults are targeted unnecessarily, or faults that should be targeted are not. The result is 100% coverage of bridging faults corresponding to undetected transition faults, which is not achieved with the earlier approach.

Scan chain faults produce large volumes of fail data that prevent the entire fail data from being collected for the purpose of defect diagnosis. Even with a single scan chain fault, the fail data volume is magnified by scan shift cycles that propagate faulty values into larger numbers of flip-flops, thus increasing the fail data volume. An approach referred to as transparent-scan allows smaller numbers of scan shift cycles to be used compared to a conventional scan-based test set, thus allowing the fail data volume to be reduced. Motivated by these observations, this paper describes a procedure that reduces the volume of fail data that scan chain faults produce under a transparent-scan sequence by omitting scan shift cycles from the sequence, or replacing them with functional capture cycles. The procedure is applied as a postprocessing step to test generation, similar to a static test compaction procedure. This is the first procedure that reduces the fail data volume for scan chain faults by modifying tests, and it is unique in that it achieves this goal by reducing the number of scan shift cycles, which is possible under transparent-scan. Experimental results for benchmark circuits demonstrate that the reduction in the fail data volume is in many cases larger than the reduction in the length of the sequence.

A variety of fault models have been defined to capture the behaviors of commonly occurring defects and ensure a high quality of testing. When several fault models are used for test generation, it is advantageous if the existence of an undetectable fault in one model does not imply that a fault in the same component but from a different model is also undetectable. This allows a test set to cover the circuit more thoroughly when additional fault models are used. This paper studies the possibility of defining such fault models by considering transition faults as the first fault model, and bridging faults as the second fault model. The bridging faults are defined to cover lines for which transition faults are not detected. A test compaction procedure is used for demonstrating the bridging fault coverage that can be achieved, and the effect on the number of tests.

The prevalence of bridging defects makes bridging fault models important to consider during fault simulation and test generation. The large number of bridging faults that can be defined for a circuit led to the development of procedures for selecting subsets of bridging faults that are likely to occur based on the circuit layout, and hard-to-detect bridging faults whose coverage provides a more effective representation for the quality of a test set. This paper develops a procedure for the selection of subsets of bridging faults that addresses the need to provide a uniform coverage of the circuit in order to prevent areas with low coverage from resulting in test escapes. In an iterative process, the procedure described in this paper uses a set of randomly selected bridging faults to compute coverage metrics for circuit lines. The lines with low coverages are used for defining a new set of bridging faults that are targeted for test generation. The iterative process updates this information to ensure that the lines with the lowest coverages continue to be targeted. A single iteration without performing test generation can be used for evaluating a test set or comparing different test sets with respect to their ability to cover the circuit.

Static test compaction procedures that modify tests perform the modification so as to increase the number of faults that some of the tests detect, thus making other tests unnecessary. Tests that become unnecessary are removed from the test set without reducing the fault coverage. This paper describes a static test compaction procedure of this type for transition faults that has the following additional feature. When the procedure modifies tests, it preserves the lengths of the paths through which transition faults are detected. This is important for preserving the ability of the test set to detect small delay defects. The procedure is structured to increase the lengths of the paths as it modifies tests even when it cannot reduce the number of tests. Experimental results for benchmark circuits demonstrate the extent to which it is possible to reduce the number of tests in an already-compact test set while preserving or increasing the path lengths.

A test reordering algorithm is presented to improve the results of scan chain diagnosis when a limited amount of fail data is collected by the tester. Tests are reordered based on information derived by applying an enhanced defect diagnosis procedure to the faulty units with scan defects. Tests that are found important for diagnosis of more faulty units are placed earlier in the test set based on the expectation that these tests will be useful for diagnosis of other faulty units as well. Experimental results collected for benchmark circuits in the presence of single and multiple scan chain defects indicate that reordering tests based on diagnostic information improves the quality of scan chain diagnosis when a limited amount of fail data is collected by the tester.

Scan chain faults that affect the scan logic of a design are important to diagnose. However, scan chain faults create large volumes of fail data that make it necessary to terminate the fail data collection process early. An approach to test generation called transparent-scan was shown to have several advantages for diagnosis of scan chain faults over conventional scan-based tests. One of these advantages is that it allows compact test sequences to be generated. This reduces the volume of fail data that scan chain faults produce. The goal of this paper is to reduce the volume of fail data further, beyond test compaction. The paper observes that different clock cycles of the transparent-scan sequence produce similar diagnostic information. Consequently, it is sufficient to store fail data for a subset of the clock cycles of the sequence. A procedure for selecting these clock cycles is described in this paper. Experimental results are presented for a basic and a more comprehensive set of scan chain faults.

Approximations of functional broadside tests maintain close-to-functional operation conditions in order to avoid overtesting of delay faults. Approximations were used earlier for increasing the fault coverage of functional broadside tests. This paper describes the first procedure that uses an approximation, referred to as piecewise-functional broadside tests, to achieve test compaction. Piecewise-functional broadside tests are characterized by a parameter p. A lower value of p indicates a closer proximity to functional operation conditions. The test compaction procedure combines a pair of tests, tiand tj, to form a test, ti,j, that can replace tiand tjwithout reducing the fault coverage, and thus reduce the number of tests. With tiand tjhaving parameter values piand pj, respectively, the combined test ti,jhas parameter value pi,j≤ pi+ pj. The procedure increases the bound p on pi,jgradually as it compacts the test set. Experimental results for benchmark circuits show that significant levels of test compaction can be achieved with p = 2. In addition, the procedure converges for a small value of p.

The compaction of test programs for processor-based systems is of utmost practical importance: Software-Based Self-Test (SBST) is nowadays increasingly adopted, especially for in-field test of safety-critical applications, and both the size and the execution time of the test are critical parameters. However, while compacting the size of binary test sequences has been thoroughly studied over the years, the reduction of the execution time of test programs is still a rather unexplored area of research. This paper describes a family of algorithms able to automatically enhance an existing test program, reducing the time required to run it and, as a side effect, its size. The proposed solutions are based on instruction removal and restoration, which is shown to be computationally more efficient than instruction removal alone. Experimental results demonstrate the compaction capabilities, and allow analyzing computational costs and effectiveness of the different algorithms.

It was shown earlier that certain primary input values have a negative effect on the fault coverage of a functional test sequence when they appear repeatedly in the sequence. A gate-level sequential test generation procedure based on this observation computed a primary input cube c with preferred values, and generated random functional test sequences that conformed to c with a high probability 0.5 ≤ p <; 1. This procedure selected values for p out of a set of possible values, and assigned the same value of p to all the primary inputs. Motivated by the low computational complexity of this procedure, this paper addresses the selection of p and the possibility of using different values of p for different primary inputs. The goal is to increase the fault coverage and reduce the number of functional test sequences. The procedure described in this paper adjusts a functional test sequence to a circuit by complementing values that conflict with c. The procedure requires fewer functional test sequences to reach or exceed the fault coverage of the earlier procedure for benchmark circuits. The procedure can be applied to any functional test sequence or set of functional test sequences.

This paper describes a procedure for computing a multicycle test set whose scan-in states are compressed into seeds for a linear-feedback shift register, and whose primary input vectors are held constant during the application of a multicycle test. The goal of computing multicycle tests is to provide test compaction that reduces both the test application time and the test data volume. To avoid sequential test generation, the procedure uses a single-cycle test set to guide the computation of multicycle tests. The procedure optimizes every multicycle test, and increases the number of faults it detects, by adjusting its seed, primary input vector, and number of functional clock cycles. Optimizing the seed instead of the scan-in state avoids the computation of scan-in states for which seeds do not exist. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

A defect diagnosis procedure is an important part of the yield improvement process. As defects become more complex, the output responses they produce differ to larger extents from the output responses of modeled faults, and they become more difficult to diagnose. Biases in the defect diagnosis procedure can also cause defects to be more difficult to diagnose. It is important to study and remove such biases in order to ensure that they do not affect the accuracy of the procedure. This paper undertakes a study of the biases of a defect diagnosis procedure and suggests a way to improve it. The study illustrates an approach by which biases in defect diagnosis procedures can be analyzed in general.

A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks to the logic blocks in the subset when a primary input vector has a negative effect on their fault coverage. The procedure is different from earlier test generation and test compaction procedures in that it increases the fault coverage without modifying the functional test sequence. It thus preserves some of the functional characteristics and the test application process for the sequence. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

This paper develops a merging procedure for functional test sequences that achieves test compaction for a pool of functional test sequences by reducing the number of sequences in the pool. The procedure has the following new features: 1) in contrast to existing selection procedures, the merging procedure described in this paper increases the fault coverage of test sequences in the pool, thus enhancing the ability to reduce the number of sequences and 2) in contrast to existing procedures that concatenate or merge test sequences, the procedure described in this paper does not increase the lengths of the sequences it merges. The procedure is based on the concept of restoration of test vectors. In the context of test sequence merging, restoration consists of copying test vectors from a test sequence Tjinto a test sequence Tiin order to allow Tito detect faults that Tjdetects. The merging procedure focuses on the removal of one test sequence Tjat a time by restoring test vectors from Tjinto other sequences, allowing them to detect the faults that Tjdetects. Experimental results for benchmark circuits demonstrate that the procedure reduces the number of sequences in a pool significantly.

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric.

This article describes a new procedure that generates seeds for LFSR -based test generation when the goal is to produce an n -detection test set. The procedure does not use test cubes in order to avoid the situation where a seed does not exist for a given test cube with a given LFSR . Instead, the procedure starts from a set of seeds that produces a one-detection test set. It modifies seeds to obtain new seeds such that the tests they produce increase the numbers of detections of target faults. The modification procedure also increases the number of faults that each additional seed detects. Experimental results are presented to demonstrate the effectiveness of the procedure.

Diagnosis of scan chain faults is important for yield learning and improvement. Procedures that generate tests for diagnosis of scan chain faults produce scan-based tests with one or more functional capture cycles between a scan-in and a scan-out operation. The approach to test generation referred to as transparent-scan has several advantages in this context. (1) It allows functional capture cycles and scan shift cycles to be interleaved arbitrarily. This increases the flexibility to assign to the scan cells values that are needed for diagnosis. (2) Test generation under transparent-scan considers a circuit model where the scan logic is included explicitly. Consequently, the test generation procedure takes into consideration the full effect of a scan chain fault. It thus produces accurate tests. (3) For the same reason, it can also target faults inside the scan logic. (4) Transparent-scan results in compact test sequences. Compaction is important because of the large volumes of fail data that scan chain faults create. The cost of transparent-scan is that it requires simulation procedures for sequential circuits, and that arbitrary sequences would be applicable to the scan select input. Motivated by the advantages of transparent-scan, and the importance of diagnosing scan chain faults, this article describes a procedure for generating transparent-scan sequences for diagnosis of scan chain faults. The procedure is also applied to produce transparent-scan sequences for diagnosis of faults inside the scan logic.

As part of a yield improvement process, fail data is collected from faulty units. Several approaches exist for reducing the tester time and the volume of fail data that needs to be collected based on the observation that a subset of the fail data is sufficient for accurate defect diagnosis. This article addresses the volume of fail data by considering the test set that is used for collecting fail data. It observes that certain faults from a set of target faults produce significantly larger numbers of faulty output values (and therefore significantly larger volumes of fail data) than other faults under a given test set. Based on this observation, it describes a procedure for modifying the test set to reduce the maximum number of faulty output values that a target fault produces. When defects are considered in a simulation experiment, and a defect diagnosis procedure is applied to the fail data that they produce, two effects are observed: the maximum and average numbers of faulty output values per defect are reduced significantly with the modified test set, and the quality of diagnosis is similar or even improved with the modified test set.

During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the volume of fail data will be reduced. Test reordering can enhance the ability to terminate the process early without affecting the quality of diagnosis. In this paper, test reordering targets logic defects based on information that is derived during defect diagnosis. The defect diagnosis procedure is enhanced to identify tests that are useful for defect diagnosis across a sample of faulty instances of a circuit. Tests that are determined to be useful for more faulty instances of a circuit are placed earlier in the test set based on the expectation that the same tests will be useful for other faulty instances of the circuit. The experimental results for logic defects in benchmark circuits support the effectiveness of this approach and indicate that test reordering helps to terminate fail data collection early without impacting the diagnosis quality.

Path selection procedures select the path delay faults that are the most important to detect as targets for test generation. When the criteria for path selection can be evaluated locally at the gate level, it is possible to consider the detectability of path delay faults during the path selection process. This flexibility does not exist if path selection is performed based on more complex conditions, or by a tool that cannot be modified to take into consideration the detectability conditions for path delay faults. For this scenario, this brief describes a procedure that accepts a set P of path delay faults, and replaces every undetectable path delay fault p ∈ P with a detectable path delay fault r that is as similar to p as possible. This brief defines similarity as the length of the longest contiguous subpath that is common to p and r. Experimental results demonstrate the extent to which similarity can be maintained when path delay faults that are associated with the longest paths are considered for benchmark circuits.

A complete industrial defect diagnosis flow for yield learning includes the use of diagnostic tests. Diagnostic tests improve the ability of a defect diagnosis procedure to provide accurate diagnosis results. Because of the costs involved, diagnostic test generation is carried out only for units where the results of defect diagnosis based on a fault detection test set are not accurate enough. This paper formulates the diagnostic test generation problem under this scenario with the goal of simplifying the test application process for diagnostic tests, taking into consideration that different units require different diagnostic tests. The parameters that the problem formulation targets are the numbers of diagnostic tests for the individual units, and the total number of diagnostic tests for all the units. A lower total number of diagnostic tests increases the similarity between the diagnostic test sets for the individual units. With similar diagnostic test sets, the units are partitioned into groups such that all the units in a group are tested using the same diagnostic test set. The paper describes a diagnostic test generation procedure that uses dynamic test compaction to optimize these parameters.

An excessive switching activity during the functional capture cycles of scan-based tests can lead to overtesting of delay faults. Low-power test generation procedures that address this issue consider the switching activity of the fault-free circuit. This paper observes that an excessive switching activity in a faulty circuit can also affect the test application process. In particular, we show that a fault effect may disappear if a signal-transition is delayed because of an excessive switching activity in the faulty circuit. Thus, excessive switching activity in the faulty circuit can result in test escapes. Using functional broadside tests for benchmark circuits, we study the extent to which the switching activity of a faulty circuit may exceed the switching activity that is possible during functional operation. We also consider the effects of eliminating tests with excessive switching activity in faulty circuits.

This paper presents an algorithm for reducing the test data volume collected by a tester for defect diagnosis of an IC and the tester time. The tester executes the tests and transfers the failing test responses one by one from the tester capture memory to the tester data-logs. While the tester is transferring the fail data, the proposed algorithm analyzes the failing outputs for every test and determines if the test is a potential contributor to the identification of defects. If not, then the test is eliminated from the tester data-logs. Otherwise, the test may replace an existing test or be added as a new test. The addition and replacement of tests continue until the algorithm determines that the fail data transferred to the tester data-logs is sufficient for accurate defect diagnosis. The early termination of the fail data transfer reduces the overall tester time. The effectiveness of the method was verified using real defects in industry fabricated dies. The algorithm was also implemented in a test program library and integrated into a production fail flow for sort data-log optimization. The overhead of the algorithm was minimal, and yielded a 5x reduction in the test data trasfer time.

Partially-functional broadside tests attempt to maintain close-to-functional operation conditions by using scan-in states that are referred to as partially-reachable. An earlier procedure starts from the fully-unspecified state, and uses fully-specified primary input vectors to compute partially-specified states that are partially-reachable. The procedure is divergent in that the number of states it considers increases with every iteration. This paper describes a new, convergent procedure that starts from a subset of reachable states, and uses the fully-unspecified primary input vector to compute partially-reachable states. The procedure typically converges without any additional constraints. By starting from reachable states, the convergent procedure captures functional constraints that cannot be obtained by the divergent procedure starting from the fully-unspecified state. Experimental results for benchmark circuits demonstrate the implications on the generation of partially-functional broadside tests.

Given a chip that produced a faulty output response to a test set, a defect diagnosis procedure produces a set of candidate faults that is expected to identify the defects that are present in the chip. The accuracy of the set of candidate faults is higher when the set is smaller or when its overlap with the defects that are present in the chip is larger. To increase the accuracy of a set of candidate faults, this paper describes an approach where several sets of candidate faults are computed based on different subsets of the test set. The subsets are obtained by removing small numbers of tests from the complete test set. The result is sets of candidate faults that are similar but not identical. The number of sets where a fault appears yields a confidence level that the fault actually belongs in a set of candidate faults. New sets of candidate faults are defined based on the confidence levels obtained. The smallest set of candidate faults can be used as the final result of defect diagnosis, or the sets can be used for ranking the candidates. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

This paper describes a procedure that computes seeds for$LFSR$-based generation of partially-functional broadside tests. Existing$LFSR$-based test data compression methods compute seeds based on incompletely-specified test cubes. Functional broadside tests are fully-specified, and they have fully-specified scan-in states. This is the main challenge that the test generation procedure described in this paper needs to address. It addresses it by using a process that modifies an initial seed$s_i$in order to reduce the Hamming distance between the scan-in state$p_i$that$s_i$creates and a reachable state$r_j$. When the Hamming distance is reduced to zero, the seed can be used for generating functional broadside tests. When the distance is larger than zero, the tests are partially-functional. Experimental results are presented for transition faults in benchmark circuits to demonstrate the resulting distances and fault coverage.

Test set quality benefits from tests that detect large numbers of faults. However, test compaction procedures target decreasing numbers of faults as they generate more tests and drop faults from consideration. This paper describes a procedure that balances the numbers of faults that tests in a given test set detect in order to improve its quality. In the first step of an iteration, the procedure moves tests from the beginning to the end of the test set. This allows fault simulation with fault dropping to create target faults for tests that were generated with small numbers of target faults. In the second step, the procedure constructs a new test set where tests with small numbers of detected faults are modified to detect additional faults. Experimental results are presented to demonstrate the ability of the procedure to improve the quality of a test set for single stuck-at faults as measured by its bridging fault coverage, and the numbers of detections of single stuck-at faults.

Test vector omission allows the length of a functional test sequence to be reduced without reducing its fault coverage. When a circuit is embedded in a design, the omission of test vectors from a functional test sequence for the circuit may result in a sequence that does not satisfy the functional constraints imposed by the design. This paper addresses this issue by developing a procedure that restores omitted test vectors in order to satisfy functional constraints. For the discussion in this paper, functional constraints are captured by the switching activity of the sequence before any test vectors are omitted from it. This is referred to as its functional switching activity profile. Experimental results demonstrate that the length of a sequence can be reduced even after restoration of omitted test vectors based on its functional switching activity profile.

Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where delay faults are detected. When a circuit is embedded in a larger design, a functional broadside test needs to take into consideration the functional constraints that the design creates for its primary input vectors. At the same time, application of primary input vectors as part of a scan-based test requires hardware support. An earlier work considered the case where a primary input vector is held constant during a test. The approach described in this article matches the hardware for applying primary input vectors to the functional constraints that the design creates. This increases the transition fault coverage that can be achieved by functional broadside tests. This article also considers the effect on the transition fault coverage achievable using close-to-functional broadside tests.

In a circuit with multiple independent scan chains, it is possible to operate groups of scan chains independently in functional or shift mode. This design-for-testability approach can be used to increase the quality of a test set. This article describes an N -detection test generation procedure for increasing the quality of a transition fault test set in such a circuit. The procedure uses the possibility of applying the same test, with the scan chains operating in different modes, to increase the numbers of detections without increasing the number of tests that need to be generated or stored on a tester. This results in reduced input storage requirements compared with a conventional N -detection test set and an increased number of applied tests. The increased quality of the test set is verified by its bridging fault coverage.

This article describes a procedure for test data compression targeting functional and partially functional broadside tests. The scan-in state of such a test is either a reachable state or has a known Hamming distance from a reachable state. Reachable states are fully specified, while the popular LFSR -based test data compression methods require the use of incompletely specified test cubes. The test data compression approach considered in this article is based on the use of periodic scan-in states. Such states require the storage of a period that can be significantly shorter than a scan-in state, thus providing test data compression. The procedure computes a set of periods that is sufficient for detecting all the detectable target faults. Considering the scan-in states that the periods produce, the procedure ranks the periods based on the distances of the scan-in states from reachable states, and the lengths of the periods. Functional and partially functional broadside tests are generated preferring shorter periods with smaller Hamming distances. The results are compared with those of an LFSR -based approach.

With the increasing transistor count and design complexity of modern integrated circuits, a large volume of fail data is collected by the tester for a failing die. This fail data is analyzed by a diagnosis procedure to obtain information about the defects in the die that caused it to fail. However, large portions of the fail data are not necessary for diagnosis. As a result, the diagnosis procedure spends time analyzing unnecessary data, thus decreasing its speed and throughput. We present a methodology to minimize the amount of fail data that is provided to the diagnosis procedure without compromising the diagnosis accuracy (DA). Our methodology evaluates the outputs at which the tests failed to eliminate noncontributing failing tests. The efficacy of our algorithm is demonstrated using fail data from industry fabricated chips. The experimental results show that, on average, our algorithm achieves fail data minimization of 40% while maintaining an average DA of 95%. The speed of the diagnosis procedure is increased by 39%.

In test data compression methods that are based on the use of a linear-feedback shift register (LFSR), a seed that produces a test for a target fault is computed based on a test cube for the fault. With a given LFSR, a seed may not exist for a given test cube, even though a seed may exist for a different test cube that detects the same fault. This issue is addressed in this brief by computing seeds for LFSR-based test generation without using test cubes. Instead, the procedure described in this brief is based on the use of nontest cubes. A nontest cube for a fault must be avoided in any test or test cube for the fault in order to allow the fault to be detected. Therefore, nontest cubes do not limit the ability of the procedure to compute seeds with a given LFSR. Experimental results demonstrate the advantages that the use of nontest cubes provides, and the associated computational cost.

Procedures that were described earlier increase the accuracy of defect diagnosis by ignoring small subsets of tests in order to produce smaller candidate fault sets. The premise behind these procedures is that most of the tests in a given test set are useful for defect diagnosis, and only small numbers of tests need to be ignored. This paper makes the new observation that it is possible to use small subsets of tests to obtain more accurate diagnosis results. This paper describes a procedure that starts from an empty test set, and adds tests one at a time. The test selected at every iteration is the one that results in the smallest candidate fault set. The addition of tests increases the number of candidate faults gradually. Experimental results for benchmark circuits demonstrate that the addition of tests provides more candidate fault sets with higher degrees of accuracy than the removal of tests. One of these candidate fault sets can be used for failure analysis.

This paper describes a procedure for generating close-to-functional broadside tests for transition faults. Such tests avoid overtesting of transition faults and keep the power dissipation within its functional bounds. The procedure has the following features that are not addressed together by existing procedures. (1) The procedure takes into consideration functional constraints on primary input sequences of a circuit that is embedded in a larger design. (2) It generates close-to-functional broadside tests with a measurable proximity to functional operation conditions. (3) It generates tests with equal primary input vectors that are suitable for embedded circuits as well as low-cost testers. Several experimental observations help in addressing the challenge of generating close-to-functional broadside tests with equal primary input vectors under functional constraints on primary input sequences.

While compaction of binary test sequences for generic sequential circuits has been widely explored, the compaction of test programs for processor-based systems is still an open area of research. Test program compaction is practically important because there are several scenarios in which Software-based Self-Test (SBST) is adopted, and the size of the test program is often a critical parameter. This paper is among the first to propose algorithms able to automatically compact an existing test program. The proposed solution is based on instruction removal and restoration, which is shown to significantly reduce the computational cost compared with instruction removal alone. Experimental results are reported, showing the compaction capabilities and computational costs of the proposed algorithms.

Soft error susceptibility is a growing concern with continued CMOS scaling. Previous work explores full- and partial-redundancy schemes in hardware and software for soft-fault tolerance. However, full-redundancy schemes incur high performance and energy overheads whereas partial-redundancy schemes achieve low coverage. An initial study, called Perturbation Based Fault Screening (PBFS), explores exploiting value locality to provide hints of soft faults whenever a value falls outside its neighborhood. PBFS employs bit-mask filters to capture value neighborhoods. However, PBFS achieves low coverage; straightforwardly improving the coverage results in high false-positive rates, and performance and energy overheads. We propose FaultHound, a value-locality-based soft-fault tolerance scheme, which employs five mechanisms to address PBFS's limitations: (1) a scheme to cluster the filters via an inverted organization of the filter tables to reinforce learning and reduce the false-positive rates; (2) a learning scheme for ignoring the delinquent bit positions that raise repeated false alarms, to reduce further the false-positive rate; (3) a light-weight predecessor replay scheme instead of a full rollback to reduce the performance and energy penalty of the remaining false positives; (4) a simple scheme to distinguish rename faults, which require rollback instead of replay for recovery, from false positives to avoid unnecessary rollback penalty; and (5) a detection scheme, which avoids rollback, for the load-store queue which is not covered by our replay. Using simulations, we show that while PBFS achieves either low coverage (30%), or high false-positive rates (8%) with high performance overheads (97%), FaultHound achieves higher coverage (75%) and lower false-positive rates (3%) with lower performance and energy overheads (10% and 25%).

It was noted earlier that the accuracy of defect diagnosis may be improved if certain tests are removed from consideration by the defect diagnosis procedure. This paper observes that the effects, which support the removal of tests, also support the removal of observable outputs from consideration during defect diagnosis. Specifically, a test may create an output response that a defect diagnosis procedure will not be able to interpret correctly. This may affect some observable outputs more strongly than others. Therefore, the removal of observable outputs from consideration can improve the accuracy of diagnosis. This paper describes a generalized augmented defect diagnosis procedure that removes tests and observable outputs from consideration. It presents experimental results to demonstrate the effects of removing observable outputs on the accuracy of diagnosis.

Test vector omission is a static test compaction procedure for functional test sequences that removes unnecessary test vectors from a sequence. The test vector omission procedure requires fault simulation for every test vector (or subsequence) that it considers for omission. It was noted earlier that it is possible to reduce the set of simulated faults based on the clock cycles where the faults are detected. However, this reduction is effective only for the later test vectors of a sequence. This paper defines a minimal set of faults that need to be simulated for the omission of a test vector by considering, in addition to detection clock cycles, also clock cycles where test subsequences start. The former are computed by a conventional sequential fault simulation process. For the latter, the paper introduces a sequential reverse order fault simulation process, and an approximation with a reduced computational complexity. Experimental results show significant reductions in the run time for test vector omission without affecting the level of compaction.

Test compaction that accommodates the constraints of test data compression can be achieved by generating test cubes for target faults, and then merging the test cubes. This paper describes an improved test cube merging procedure for four-way bridging faults. The procedure is motivated by the prevalence of bridging defects and the fact that test sets for bridging faults are larger than test sets for single stuck-at faults. A four-way bridging fault gi/ai/himodels the case where a value aiof a line hidominates the value of a line gi. A basic test cube merging procedure considers a set of test cubes Cdetthat detects target faults. The paper extends the set of test cubes to include, in addition to Cdet, a set of test cubes Cdomthat assign values to dominating lines. Test cubes from Cdomhave significantly fewer specified values than test cubes from Cdet. When test cubes from Cdomare merged with test cubes from Cdet, each resulting test cube detects more faults, and fewer test cubes are needed for detecting the same set of target faults.

Test quality metrics that use the numbers of detections of target faults are based on the premise that increasing the number of tests for a fault increases the likelihood of detecting defects around the site of the fault. This paper describes a new definition of the number of detections for faults that have only one test in a given test set. Such faults are prevalent in compact test sets. For a fault with a single test, metrics based on the number of detections yield the same value, one, for any test. The new definition associates different numbers of detections with different tests for the fault by considering the number of distinct test cubes that a test contains. It thus provides a target for the generation of a single test with a higher quality for the fault. The effectiveness of the definition is demonstrated by modifying a compact test set to increase the numbers of detections of single stuck-at faults with single tests, and comparing a bridging fault coverage of the test set before and after the modification.

This paper describes a new characterization of broadside tests that measures the proximity to functional operation conditions during their functional clock cycles, where delay faults are detected. Proximity to functional operation conditions is important for avoiding overtesting of delay faults. The new characterization considers a test as piecewise-functional based on its scan-in state. For functional operation conditions, the scan-in state must be a reachable state (a state that the circuit can enter during functional operation). However, using only reachable states as scan-in states limits the fault coverage that can be achieved. In a piecewise-functional broadside test, the scan-in state can be partitioned into substates that are also substates of reachable states. The paper presents a definition that allows every broadside test to be characterized as piecewise-functional. It also describes procedures for characterization, and for modification of broadside test sets so as to ensure that they create closer-to-functional operation conditions.

A restoration based static test compaction procedure removes unnecessary test vectors from a functional test sequence in order to reduce its length. To allow the procedure to reduce the storage requirements of the sequence further, this paper introduces a new approach where a single stored sequence is used for applying several different functional test sequences. Under this approach, the stored sequence is considered as two-dimensional arrays with different dimensions. Each array yields a different test sequence, which is a permutation of the stored sequence. When the permutations are effective in detecting target faults, an existing static test compaction procedure, with certain modifications, can reduce the length of the stored sequence, and rely on the application of the permutations to detect all the target faults. Simulation results show significant reductions in the input test data volume. The cost of increased numbers of clock cycles for test application can be utilized for increasing the fault coverage of non-target faults.

Test vector omission was introduced as a static test compaction procedure for functional test sequences. Experimental results indicated that it can also increase the fault coverage accidentally when it is applied to a sequence that does not detect all the detectable target faults. However, this capability was not explored directly. It is important since test vector omission provides a smaller search space for functional test sequences than any existing approach to sequential test generation. This paper describes a branch-and-bound procedure for test vector omission whose goal is to find functional test sequences for faults that are not detected by a given sequence. Experimental results for benchmark circuits demonstrate that the procedure provides a cost-effective addition to a simulation-based sequential test generation procedure.

Test compaction can be achieved by using multicycle tests. To avoid the computationally intensive process of sequential test generation, multicycle tests can be generated by extending two-cycle tests. However, the scan-in state of a two-cycle test is not always effective for a multicycle test when the primary input vectors are held constant during the functional clock cycles of a test. This paper studies the extent of this issue by considering exhaustive two-cycle and multicycle test sets with constant primary input vectors for finite-state machine benchmarks. Based on the results of this study, it describes an efficient test compaction procedure that modifies selected two-cycle tests in a given test set in order to make them more effective as a source for multicycle tests with constant primary input vectors. Experimental results are presented to demonstrate the importance of this step to test compaction.

This paper describes a procedure that computes seeds for linear-feedback shift register-based diagnostic test generation. A conventional process first computes test cubes, and then computes seeds that produce them by solving sets of linear equations. With this process, a seed may not exists for a given test cube. To address this issue, the procedure described in this paper produces seeds directly. Staring from a seed for fault detection, it modifies the seed such that the test it produces will distinguish a pair of faults. The procedure is applied in two modes. The first mode does not require diagnostic test cubes. In this mode, the procedure attempts to modify a seed for fault detection so as to lose the detection of one of the faults on one of the outputs where the faults are detected. The procedure thus uses the concept of test elimination that was used earlier for diagnostic test generation. The second mode is guided by a diagnostic test cube for a fault pair that needs to be distinguished. The procedure modifies a seed so as to reduce the distance between the test that the seed produces and the test cube. Without the requirement to match all the specified values of the test cube, the procedure can produce a seed for distinguishing the pair of faults even when a seed for the given test cube does not exist. Experimental results are presented to demonstrate the effectiveness of the procedure.

A class of static test compaction procedures for functional test sequences is based on the omission of unnecessary test vectors. According to the definition used by these procedures, a test vector is unnecessary if all the target faults continue to be detected after it is omitted. This article introduces a more general definition of unnecessary test vectors that allows additional ones to be omitted. According to this definition, a test vector is unnecessary if every target fault can be detected by a sequence that is obtained after omitting the vector, and possibly other vectors. The article develops a procedure for omitting test vectors based on this definition and discusses its effects on the storage requirements and test application time.

This article introduces a new approach to extreme static test compaction for functional test sequences that modifies the sequence in order to enhance the ability to omit test vectors from it and thus compact it. In the new approach, modification of the sequence and omission of test vectors from it are tightly coupled by focusing both subprocedures on subsequences of limited lengths. In a new process that is referred to as folding, a subsequence is partitioned into two halves, and the goal of the modification is to ensure that the two halves are as similar as possible. With similar halves, the expectation is that it will be possible to omit test vectors from the subsequence. Experimental results demonstrate that the procedure produces extremely short functional test sequences for benchmark circuits.

Multicycle tests support test compaction by allowing each test to detect more target faults. The ability of multicycle broadside tests to provide test compaction depends on the ability of primary input sequences to take the circuit between pairs of states that are useful for detecting target faults. This ability can be enhanced by adding design-for-testability (DFT) logic that allows states to be complemented. This article describes a test compaction procedure that uses such DFT logic to form a compact multicycle broadside test set for transition faults where the tests use constant primary input vectors. The use of complemented states also allows the procedure to increase the transition fault coverage beyond the transition fault coverage of a broadside test set. The procedure has the option of increasing the switching activity of the tests gradually in order to explore the tradeoff between the number of tests, the fault coverage, and the switching activity.

A low-power test generation procedure that was developed earlier merges broadside test cubes that are derived from functional broadside tests in order to generate a low-power broadside test set. This has several advantages, most importantly, that test cubes, which are derived from functional broadside tests, create functional operation conditions in subcircuits around the sites of detected faults. These conditions are preserved when a test cube is merged with other test cubes. This brief applies a similar approach to the generation of a low-power skewed-load test set. The main challenge that this paper addresses is the derivation of skewed-load test cubes from functional broadside tests. The paper also considers the percentages of values that should be unspecified in the skewed-load test cubes in order to balance the need to create functional operation conditions with the need for test compaction.

This brief describes a static test compaction procedure for low-power test sets, which is based on the observation that a higher switching activity leads to a smaller number of tests. To use this observation in the context of low-power test sets, this brief makes the following new observations. First, considering the number of tests in a given test set where a line g makes a 0 → 1 or a 1 → 0 transition, there are large variations in this number between different lines. Increasing the switching activity only for a subset G of lines that make the smallest numbers of signal transitions is sufficient for achieving test compaction. Second, the switching activity for the subset G can be increased in a way that the specific values that the lines assume can occur during functional operation, and the maximum switching activity for the test set does not increase. These observations allow the compacted test set to remain a low-power test set. Experimental results demonstrate significant reductions in the numbers of tests in low-power test sets for transition faults in benchmark circuits.

This paper describes a new model for a set of test sequences where a set S is described by a single functional test sequence T. Using this model, a procedure that compacts T compacts all the sequences in S simultaneously. This enhances the ability of the procedure to compact the set compared with procedures that consider the sequences in the set individually. It also allows the test sequences in S to be redefined. If different sequences in S have substantially different lengths, repartitioning T allows new sequences with more uniform lengths to be obtained. After repartitioning, additional test compaction can be achieved. This paper describes a test compaction procedure that includes these operations based on the modeling of a set as a single sequence.

This paper describes a test compaction procedure that considers a set of functional test sequences for a set of logic blocks in a design. The logic blocks may have different numbers of primary inputs, and functional test sequences of different lengths. The procedure expands the test sequences such that every sequence is applicable to every logic block. It then concatenates and compacts the sequences into a single sequence. In this process, it considers the logic blocks one at a time to avoid the need to store and simulate all the logic blocks simultaneously. The resulting test sequence can be applied to all the logic blocks in parallel. The experimental results demonstrate the levels of test compaction that can be achieved by this approach. The results also demonstrate that the resulting sequence has an improved coverage of faults that were not targeted during the generation of the functional test sequences or the test compaction procedure.

Test generation by merging of test cubes supports test compaction and test data compression. This paper describes a new approach to the use of test cube merging for the generation of compact diagnostic test sets. For this the paper uses the new concept of non-test cubes. While a test cube for a fault fi0detects the fault, a non-test cube for a fault fi1prevents the fault from being detected. Merging a test cube for a fault fi0and a non-test cube for a fault fi1produces a diagnostic test cube that distinguishes the two faults. The paper describes a procedure for diagnostic test generation based on merging of test and non-test cubes. Experimental results demonstrate that compact diagnostic test sets are obtained.

Comparing a single transition fault with a single path delay fault, targeting (i.e., simulating or generating a test for) a path delay fault is not more complex than targeting a transition fault. However, targeting a set of path delay faults is significantly more complex than targeting a set of transition faults when the goal is to consider the testable path delay faults that are associated with the longest paths. The reason is the large fraction of untestable path delay faults among these faults. This complication is removed if the requirement on the lengths of the paths is removed. In this case, it is possible to use path delay faults instead of transition faults as a basic delay fault model for better coverage of small delay defects. This paper studies the effects of using path delay faults as a basic delay fault model instead of transition faults.

Test compaction can be achieved by generating incompletely-specified tests (test cubes) and merging test cubes that are compatible. A test cube that is generated for one target fault specifies values that are needed for detecting only this fault. Compatible test cubes do not conflict in any of their specified values. When compatible test cubes ci0and ci1are merged, they yield a single test cube, ci0+ci1which detects all the faults that are detected by ci0and ci1individually. In addition, ci0+ci1may detect other faults. Thus, merging of test cubes yields test cubes that detect more faults, contributing to test compaction. After test cube merging, unnecessary test cubes may exist in the test set. Such test cubes can be identified by fault simulation followed by reverse order fault simulation.

This paper describes a method for built-in generation of functional broadside tests for a circuit that is embedded in a larger design, taking functional constraints on its primary input sequences into account. The constraints are captured by functional input sequences of the design. Specifically, the peak switching activity in the circuit under the functional input sequences is used to bound the switching activity during on-chip test generation.

This talk will cover different aspects of low-cost and high-quality SOC test to meet varying end application requirements (catalog, automotive, wireless, etc.). While some of the test techniques are well-known, they will be stitched together through illustrations to indicate how test cost can be minimised in the presence of various design and tester constraints, without compromising on the quality. Different digital and analog IP components will be considered as part of the SOC test integration process

Static test compaction procedures reduce the number of tests in a given test set without reducing the fault coverage. Static test compaction procedures can use the set or the number of faults detected by each test as guidance. Fault simulation without or with limited fault dropping is needed for producing this information. However, it can be time consuming. To compute the information needed for guiding static test compaction efficiently, this paper describes a fault simulation procedure with fault dropping that attempts to balance the sizes of the sets of detected faults. This is achieved by switching the test being simulated as soon as it detects a fault. Differences in the numbers of detected faults, in spite of the attempt to balance them, is attributed to the relative effectiveness of the tests in detecting target faults. The paper shows that reordering a test set based on the results of fault simulation with test switching is effective when applied prior to forward-looking reverse order fault simulation. In general, the procedure can be used in applications where it is advantageous to balance the sets of detected faults.

Multi-cycle scan-based tests are useful for test compaction since, in general, a test with more clock cycles between its scan operations can detect more faults. For delay faults, test compaction is achieved by applying several consecutive clock cycles under a fast clock. This complicates the fault simulation and test generation processes. This paper describes a new approach that stores multi-cycle tests, but applies to the circuit tests that are effectively two-cycle broadside tests. The storage of multi-cycle tests allows the number of stored tests, and the input test data volume, to be reduced. Alternatively, for the same number of stored tests, it allows additional two-cycle tests to be applied. The application of two-cycle broadside tests allows fault simulation and test generation procedures for broadside tests to be used.

When built-in test generation is used for a design that can be partitioned into logic blocks, it is advantageous to identify groups of blocks whose tests have similar characteristics, and use the same built-in test generation logic for the blocks in each group. This paper studies this issue for a built-in test generation method that produces functional broadside tests. Functional broadside tests are important for addressing overtesting of delay faults as well as avoiding excessive power dissipation during test application. The paper discusses the design of the test generation logic for a group of logic blocks, and the selection of the groups.

When using output response compaction it is necessary to address the fact that circuits may produce unknown output values. Methods to address this issue ensure that the output response compactor would produce a unique fault-free signature that can be used for fault detection. This paper considers the unknown output values that are produced by faulty circuits. If a faulty circuit produces an unknown value when the output value of the fault-free circuit is known, the unknown faulty output value may affect the computation of a signature. The faulty signature may not be unique, and it may not always be different from a fault-free signature. The ability to verify that the fault will be detected based on its signature is thus lost. Without limiting the discussion to a particular output response compactor, the paper studies the prevalence of such faults in benchmark circuits, the prevalence of unknown faulty output values for which the corresponding fault-free values are known, and the effects of addressing this issue.

Test data compression methods reduce the input test data volume by allowing compressed tests to be stored on a tester. Additional reductions in the input test data volume can be achieved if each stored test is used for producing several different tests. Skewed-load tests create a unique opportunity to expand a stored test into several different skewed-load tests by continuing to shift the scan-in state for one or more additional clock cycles. This opportunity for test data volume reduction beyond test data compression is introduced in this paper. The paper describes a procedure that starts from a given skewed-load test set. The procedure removes tests from the test set and recovers the fault coverage by applying several tests based on every stored test.

Functional test sequences may be generated for simulation-based design verification, and used as manufacturing tests or for speed binning. A class of earlier procedures selects functional test sequences for target faults from a set of available sequences in order to reduce the storage requirements and test application time. This paper describes a procedure that reduces the storage requirements further by using the selected sequences for producing additional sequences, which are referred to as overlaps. In an overlap, the first vectors of one selected sequence and the last vectors of another are combined. Overlaps thus combine initialization, fault activation and fault propagation conditions from two sequences to detect additional faults, making it unnecessary to select other sequences. Overlaps can also be used for increasing the fault coverage with respect to a fault model that was not targeted during the selection of the sequences.

Functional broadside tests are useful for guiding a low-power test generation procedure by providing a target for the switching activity of low-power tests. Low-power test generation procedures based on functional broadside tests first generate a set of functional broadside tests. They then use the tests for guiding the generation of low-power non-functional broadside tests that are required for increasing the fault coverage. In the low-power test generation procedure described in this paper, functional and non-functional broadside tests are generated simultaneously by the same process. In addition to the simplicity that this provides, it also requires fewer functional broadside tests that detect target faults to be generated. Moreover, it allows stricter constraints on the switching activity of non-functional broadside tests to be satisfied. These constraints prevent a non-functional broadside test from compensating for an excessively high switching activity in one sub-circuit with a low switching activity in another.

In a two-step defect diagnosis process, a fault detection test set is used for initial diagnosis to compute an initial set of candidate faults. When the initial set is large, diagnostic tests are generated based on the candidate faults in the set, and the set is refined based on the extended test set. This paper investigates the ability of functional broadside tests to serve as diagnostic tests for refining initial sets of candidate faults. The paper discusses the advantages of using functional broadside tests for this purpose. These advantages are related to the fact that the tests create functional operation conditions, and thus avoid nonfunctional effects that may make diagnosis less accurate. It also describes a multistep defect diagnosis process that uses functional broadside tests. Experimental results are presented to show the extent to which functional broadside tests can reduce initial sets of candidate faults.

This paper describes a new approach to static test compaction for scan circuits that modifies tests in order to reduce the number of tests in a test set. The main contribution of this paper is a procedure referred to as restoration. In a basic step, the restoration procedure considers two tests, tremand tmod, with sets of detected faults Dremand Dmod, respectively. Starting from tnew= tmod, and considering tnewas a variation of trem, the procedure restores bits of treminto tnewas necessary to ensure that faults from Dremare detected by tnew. The procedure then restores bits of tmodinto tnewas necessary to ensure that all the faults from Dmodare detected by tnew. The test tnewis used for replacing tmod, and the faults it detects out of Dremare moved to Dmod. After several such steps, if Drem becomes empty, tremcan be removed from the test set. The procedure is applied to test sets that are already compacted. The results show that the procedure can achieve significant additional compaction even without considering all the tests for removal or modification.

Experimental results indicate that the addition of diagnostic tests to a fault detection test set may sometimes result in a larger set of candidate faults. Experimental results also indicate that a defect diagnosis procedure does not require the complete observed response of a faulty chip in order to produce accurate diagnosis results. Motivated by these observations, this paper augments a defect diagnosis procedure with a process that removes from consideration tests whose effects on the results of diagnosis may be negative. The augmented procedure runs the underlying defect diagnosis procedure several times in order to decide which tests should be removed from consideration. Experimental results indicate that this results in smaller sets of candidate faults and improved accuracy of diagnosis.

This article studies the generation of low-power skewed-load tests such that the signal transitions (and line values) they create during their fast functional clock cycles match those of functional broadside tests. Functional broadside tests create functional operation conditions during their fast functional clock cycles. As a result, the signal transitions that occur during these clock cycles can also occur during functional operation. The procedure described in this article matches these signal-transitions on a line-by-line basis when generating low-power skewed-load tests. The procedure accepts a functional broadside test set for transition faults. In one of its basic steps, the procedure modifies a functional broadside test into a skewed-load test. This allows it to retain many of the signal transitions (and line values) of the functional broadside test in the skewed-load test. Experimental results for benchmark circuits demonstrate the extent to which it is possible to match the signal-transitions of skewed-load tests with those of functional broadside tests while achieving the high transition fault coverage that is typical of skewed-load tests.

This article describes a design-for-testability approach for increasing the transition fault coverage of multi-cycle broadside tests. Earlier methods addressed two-cycle tests. The importance of multi-cycle tests results from the ability to produce more compact test sets than possible with two-cycle tests, from the fact that when multi-cycle tests are applied at-speed, they can detect defects that are not detected by two-cycle tests and from their ability to avoid overtesting of delay faults. The approach described in this article is based on holding the values of selected state variables constant during the functional clock cycles of a multi-cycle broadside test. This allows new tests to be produced, which are different from broadside tests, without relying on nonfunctional toggling of state variables as in earlier methods for two-cycle tests. Experimental results show significant improvements in transition fault coverage using a fixed set of hold configurations for two types of multi-cycle broadside test sets: (1) test sets that are stored and applied from an external tester, and (2) functional broadside test sets that are generated using on-chip hardware.

The goal of static test compaction is to reduce the number or tests, or the lengths of test sequences, without reducing the fault coverage. Static test compaction that reduces the number of tests was formulated as a set covering problem in order to benefit from the heuristics that exist for solving this problem. This paper applies set covering concepts and heuristics to static test compaction that reduces the length of a functional test sequence. Although set covering is not applicable directly to a single test sequence, it provides a theoretical framework and justification for a particular set of heuristics. The procedure uses a parameter denoted by n to determine the computational effort for computing the sets that are used for making compaction decisions. With n=1, the procedure is equivalent to a static test compaction procedure that does not use set covering. Experimental results demonstrate that shorter test sequences are obtained for n>1 than for n=1. A variation of the static test compaction procedure that produces a monotonic decrease in test sequence length with n is also described.

An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. A transparent-scan sequence for one block is likely to detect faults in other blocks since transparent scan does not distinguish between functional and scan clock cycles, and allows faults to be detected at all the clock cycles of the sequence. Such sharing of tests is not meaningful with conventional scan-based tests, especially when the blocks have different numbers of state variables. Transparent scan thus enhances the ability to produce a compact test set for a group of logic blocks. The static test compaction procedure described in this paper uses transparent-scan sequences that follow the application of conventional scan-based tests precisely. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it selects a subset that detects all the target faults, which are detected by the complete set.

This paper describes a low-power test generation procedure, which targets the switching activity during the fast functional clock cycles of broadside tests. The procedure is based on merging of test cubes that it extracts from functional broadside tests. The use of test cube merging supports test compaction and it can be used for accommodating the constraints of test data compression. The use of functional broadside tests provides a target for the switching activity of low-power tests, which does not exceed the switching activity that is possible during functional operation, or that the circuit is designed for. The use of test cubes that are extracted from functional broadside tests is a unique feature of this procedure. It ensures that the low-power tests would create functional operation conditions in subcircuits that are defined by the test cubes. Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and nonfunctional) broadside tests in benchmark circuits.

Functional broadside tests address overtesting due to high-power dissipation by creating functional operation conditions during the clock cycles where delay faults are detected. Guided by their switching activity, it is possible to generate a low-power test set whose switching activity does not exceed the switching activity possible during functional operation. This brief applies the same approach to the generation of a low-power diagnostic test set. Excessively high switching activity can cause unexpected fault effects to appear, which will reduce the accuracy of fault diagnosis. This is avoided with a low-power diagnostic test set. Functional broadside tests are also used for avoiding diagnostic tests with unnecessarily low switching activity. The procedure described in this brief is the first to generate low-power diagnostic tests under functional constraints on switching activity as given by functional broadside tests.

The goal of fault diagnosis is to identify a set of candidate faults, or fault locations, that explain an observed faulty output response of a chip. In fault diagnosis procedures that are based on specific fault models, a scoring algorithm can be used for defining sets of candidate faults that include the faults with the highest scores. This paper shows that it is possible to capture the underlying concepts that make fault scoring effective through a graph, which is referred to as the dominance graph. With a test set T used for fault diagnosis, the graph represents the dominance relations between the equivalence classes obtained with respect to T. The observed response Robsof a chip-under-diagnosis is associated with an equivalence class Cobs, and Cobsis added to the dominance graph. A candidate fault set is defined based on the dominance relations that are added to the graph due to the addition of Cobs. Certain properties of these dominance relations point to the type of the defect present in the chip, and the most appropriate algorithm for defining a set of candidate faults based on it.

The possibility of achieving test compaction by using multi-cycle tests led to the development of procedures that produce compact multi-cycle test sets for the detection of single stuck-at faults, for the detection of transition faults, and for n-detections of single stuck-at faults [1]-[4]. The advantages of compact diagnostic test sets motivated the development of the test compaction procedures from [5]-[7]. These procedures were applied to produce compact single-cycle diagnostic test sets. The procedure described in this paper achieves test compaction for diagnostic test sets by using multi-cycle tests to replace single-cycle tests in a compact single-cycle diagnostic test set.

We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.

The local switching activity of scan-based tests is important due to the possibility that scan-based tests will result in excessive power dissipation in certain subcircuits even when the total power dissipation is acceptable. This paper focuses on the local switching activity during the fast functional capture cycles of functional broadside tests. This switching activity is guaranteed not to exceed the switching activity possible during functional operation. Therefore, with functional broadside tests it is possible to maximize the switching activity without causing excessive power dissipation. This is important for test quality since, in general, higher switching activity allows more delay defects to be detected. In addition, it allows smaller test sets to be obtained for delay faults. The paper defines a switching activity metric called the adjacent switching activity that captures the switching activity around the sites of detected transition faults, where additional switching activity is most likely to contribute to test quality. It compares the cases where the adjacent and the total switching activity of functional broadside tests for transition faults are maximized. The results demonstrate that the two objectives result in significantly different test sets. Moreover, better quality test sets are obtained by maximizing the adjacent switching activity.

Existing low-power test generation procedures use a single number to represent the power dissipation in a circuit or subcircuit. As a result, the specific signal transitions they create may deviate substantially from those possible during functional operation (and those the circuit is designed for). Functional broadside tests create functional operation conditions during their two functional capture cycles. Therefore, the specific signal transitions that occur during their second, fast functional capture cycles can occur during functional operation. This paper defines and studies the patterns of signal transitions under the second, fast functional capture cycles of functional broadside tests. These patterns can be used for evaluating the deviations from functional power dissipation created by low-power test sets that consist of arbitrary (functional and nonfunctional) broadside tests. They can also be used for guiding the generation of low-power test sets. The paper presents experimental results for both applications.

This paper describes a test generation procedure that produces functional broadside tests for logic blocks whose primary input sequences are constrained. The constraints are created during functional operation by logic blocks that drive the logic block under consideration. Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where delay faults are detected. Test generation procedures for functional broadside tests typically assume that the primary input sequences are unconstrained during functional operation. This paper shows that the constraints, which are imposed by a logic block driving the primary inputs of another block, can be time dependent and difficult to represent compactly. The test generation procedure described in this paper addresses this issue by separating the problem of test generation into the generation of constrained primary input sequences for the block under consideration, and the extraction of functional broadside tests from these sequences.

Functional broadside tests address overtesting of delay faults by using reachable states as scan-in states. Since reachable states are, in general, fully specified, functional broadside tests are not amenable to the commonly used test data compression methods. This paper defines multicycle functional broadside tests whose scan-in states are incompletely specified. The first clock cycles of a test bring the circuit from the scan-in state into a reachable state without activating delay faults. The last two clock cycles detect delay faults by applying a two-cycle functional broadside test. This paper also describes a test generation procedure for tests of this type. The procedure uses a condition, which is based on the initial state of the circuit for functional operation, to simplify the generation of the tests.

A test set includes a significant amount of information about input assignments that prevent the faults that it does not detect from being detected. The procedure described in this paper extracts this information and uses it to guide an efficient test generation process that is fundamentally different from existing processes. Even with limited computational complexity, this new process is able to generate tests for hard-to-detect transition faults that are not detected by a test set that consists of both broadside and skewed-load tests. The basic idea is the following. Let t be a test that does not detect a fault f. The procedure extracts from t a minimal subset of values that prevent f from being detected. These values are included in a partially-specified test, which is referred to as a nontest cube. In a basic step, the procedure finds a nontest cube for f based on t. It then modifies t by complementing one specified value of the nontest cube to ensure that it does not prevent f from being detected. This is repeated until a test is found or a termination condition is reached. The nontest cubes are also used for finding necessary assignments and identifying undetectable faults.

Functional broadside tests allow overtesting to be avoided as part of a scheme that considers both test generation and the analysis of output responses, by ensuring that delay faults are detected under functional operation conditions. Compared with two-cycle tests, multicycle tests allow more faults to be detected with each test, thus reducing the number of tests that need to be applied. They also provide an opportunity for nonfunctional electrical effects, which are caused by switching between modes of operation, to subside before the clock cycles where delay faults are detected. Built-in test generation facilitates at-speed testing and reduces the test data volume. Motivated by these observations, this article describes the modification of a built-in test generation method for two-cycle functional broadside tests so as to generate multicycle functional broadside tests. The size of the hardware is not increased by the modification. The article investigates the following issues related to this method: (1) the effect of using multicycle tests on the number of tests that need to be applied; (2) fault simulation for tailoring the test generation hardware to a circuit that takes into account, to different extents, the need to allow nonfunctional electrical effects to subside; (3) the insertion of observation points in order to increase the transition fault coverage.

Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. In addition, the power dissipation during the fast functional clock cycles of functional broadside tests does not exceed that possible during functional operation. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states offline.

Considering full-scan circuits, incompletely-specified tests, or test cubes, are used for test data compression. When considering path delay faults, certain specified input values in a test cube are needed only for determining the lengths of the paths associated with detected faults. Path delay faults, and therefore, small delay defects, would still be detected if such values are unspecified. The goal of this paper is to explore the possibility of increasing the number of unspecified input values in a test set for path delay faults by unspecifying such values in order to make the test set more amenable to test data compression. Experimental results indicate that significant numbers of such values exist. The proposed procedure unspecifies them gradually to obtain a series of test sets with increasing numbers of unspecified values and decreasing path lengths. Experimental results also indicate that filling the unspecified values randomly (as with some test data compression methods) recovers some or all of the path lengths associated with detected path delay faults. The procedure uses a matching of the sets of detected faults for the comparison of path lengths.

Tester limitations may impose certain constraints on the primary input vectors applicable as part of a two-pattern test for delay faults. Under these constraints, the primary input vectors may be held constant, or the second primary input vector of a test may be obtained by a single shift of a scan chain relative to the first. The goal of this brief is to study the differences in achievable transition fault coverage between various primary input constraints that are similar to the commonly used ones of holding or shifting primary input vectors. This brief also studies the possibility of combining the constraints in order to increase the transition fault coverage. The combination requires a fixed and circuit-independent hardware structure similar to the case where shifting of primary input vectors is used. This study is done using test sets that consist of both broadside and skewed-load tests in order to maximize the transition fault coverage.

This brief considers circuits with multiple scan chains where each scan chain can operate in shift, functional, or hold mode independently of the other scan chains. For circuits where the hardware overhead of controlling the scan chains independently is acceptable, this brief describes a procedure whose goal is to generate a test set that achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests, but where the shift mode is used as few times as possible during the first patterns of the tests. This allows the circuit to operate closer to its functional operation conditions, and reduces the power dissipation during the second patterns of the tests, which are applied at-speed.

The scan-in states of functional broadside tests are reachable states, which are states that the circuit can enter during functional operation. This is used for ensuring functional operation conditions during the functional clock cycles of the tests. For a partially-functional broadside test, the scan-in state has a known Hamming distance to a reachable state. This ensures measurable deviations from functional operation conditions during the functional clock cycles of the test. It is important for addressing overtesting as well as excessive power dissipation. This brief develops a fault-simulation procedure for transition faults under arbitrary (functional and nonfunctional) broadside tests that considers the tests as partially-functional broadside tests. The procedure can be used for evaluating the proximity to functional operation conditions of arbitrary broadside test sets. For illustration, the procedure is used for comparing a low-power test set with an arbitrary broadside test set.

For a test set that consists of test cubes (incompletely specified tests), test compaction can be achieved by merging pairs of compatible tests (tests that do not conflict in any of their specified values). This paper describes a test compaction procedure that enhances the ability of test-merging to reduce the number of tests in an incompletely specified test set that consists of both broadside and skewed-load tests for transition faults. In a basic step, the procedure attempts to remove a test t by combining it with several other tests, even if the tests are not compatible or have different types. This increases the possibility that all the faults detected by t will be detected by other tests, and t will be removed. Simulation results demonstrate reductions in numbers of tests beyond those achieved by test-merging with the same or lower numbers of specified values.

This brief describes a new approach to low-power test generation targeting the maximum switching activity during the fast functional clock cycles of broadside tests. This brief defines functional broadside templates as incompletely-specified broadside tests, which capture the signal-transitions that occur during the fast functional clock cycles of functional broadside tests. The same signal-transitions can occur during functional operation. Therefore, functional broadside templates can guide the generation of low-power test sets when the goal is to match the power dissipation that is possible during functional operation on a line-by-line basis. This brief describes a procedure for computing functional broadside templates from completely-specified functional broadside tests, and a low-power test generation procedure for transition faults based on templates.

Paths that cannot be sensitized during functional operation do not need to be optimized for speed, and their delays may be higher than the clock period. This paper uses functional broadside tests for path delay faults in order to avoid overtesting due to the detection of faults that are associated with such paths. To ensure that as many small delay defects as possible will be detected, the paper considers path delay faults that are associated with full paths as well as ones associated with subpaths. It uses a type of path delay faults called transition path delay faults to define the conditions under which a path delay fault associated with a subpath is detected. It uses detection conditions called the hazard-based detection conditions, which yield a type of weak non-robust tests, to detect as many transition path delay faults as possible. Experimental results demonstrate the importance of considering subpaths for different coverage objectives.

The conventional detection conditions for transition faults require a transition at the fault site for activating a fault. The hazard-based detection conditions allow a transition fault to be activated by a pulse. Earlier, the hazard-based detection conditions were used for obtaining more accurate estimates of transition fault coverage and for more accurate defect diagnosis. This paper considers their use for test compaction. The procedure described in this paper replaces the conventional detection conditions with the hazard-based detection conditions for some faults. The use of the hazard-based detection conditions allows each test to detect more faults, thus allowing the number of tests to be reduced.

Skewed-load and broadside tests complement each other and allow higher delay fault coverage to be achieved for a standard-scan circuit that supports both types of tests. The difference between the two types of tests is mainly in the test application process. The input test data required for both of them are similar. This similarity is used in this work to compute compact input test data that can be used as a basis for forming both types of tests. It results in improved fault coverage compared to the use of broadside (or skewed-load) tests alone, and in reduced test data volume compared to the case where broadside and skewed-load tests are stored separately. Experimental results are presented using a procedure that accepts a test set of any type, and computes input test data suitable for the application of both types of tests. The procedure modifies the test data so as to compact it as well as increase the fault coverage. The procedure is applied to a broadside test set and to mixed test sets that consist of both types of tests.

Functional test sequences have several advantages over structural tests when they are applied at-speed. A large pool of functional test sequences may be available for a circuit due to the application of a simulation-based design verification process. This paper describes a versatile procedure that uses a pool of functional test sequences as a basis for forming a single compact functional test sequence that achieves the same or higher gate-level fault coverage than the given pool. The procedure extracts test subsequences from the test sequences in the pool and concatenates them to form a single test sequence. It also employs an enhanced static test compaction process aimed at improving the fault coverage in addition to reducing the test sequence length.

This paper describes a fast procedure for identifying undetectable transition faults under functional broadside tests. By using reachable states as scan-in states, functional broadside tests avoid overtesting that may occur when scan-based tests are used for detecting delay faults. The proposed procedure is based only on logic simulation, and does not perform test generation of any type. In one of its variations, the procedure uses logic simulation of fully unspecified primary input vectors starting from a known initial state in order to identify a superset of broadside tests that covers all the functional broadside tests. It then uses this superset to identify undetectable transition faults. The procedure identifies large numbers of undetectable transition faults in certain benchmark circuits.

Multicycle (multipattern) scan-based tests contain multiple clock cycles between scan operations. Each such clock cycle defines a pattern of the test. Multipattern tests require fewer clock cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of clock cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.

When a multipattern scan-based test is applied at-speed to detect delay defects, it is necessary to change the primary input vectors at-speed. However, tester limitations can make this infeasible. The solution where the primary input vectors are held constant during the test reduces the fault coverage. An alternative solution is to store the primary input sequences of a multipattern test set on-chip and apply them at-speed from an on-chip memory. To support such a solution, this paper describes a procedure for computing a multipattern test set that requires a small number of different primary input sequences. Experimental results for single stuck-at faults and for transition faults show that a multipattern test set that detects all the detectable faults requires a number of primary input sequences that is significantly smaller than the number of tests.

Test generation procedures forn-detection test sets improve the quality of a test set by adding tests that increase the numbers of detections of target faults. A different approach ton-detection test generation increases the numbers of detections of target faults within the bounds of the number of tests of a single-detection test set. Multicycle tests provide the flexibility of improving the quality of a test set by increasing the number of clock cycles in each test, without increasing the number of tests. Improved test quality is thus achieved with limited increases in test application time and test data volume due to the larger numbers of clock cycles in each test. This paper describes a procedure that starts from a compact one-detection single-cycle test set for single stuck-at faults and produces a multicycle test set with the same number of tests, but increased numbers of clock cycles and improved test quality. The procedure uses only one-detection fault simulation of single stuck-at faults. A similar procedure is applied starting from a two-cycle test set and considering transition faults. The procedures produce tests with constant primary input vectors to accommodate tester limitations.

Path delay faults are used for modeling small delay defects. Due to the large numbers of paths and the large numbers of undetectable path delay faults, test generation procedures for path delay faults use path selection procedures and procedures for the identification of undetectable faults to facilitate test generation. To complement these procedures, this paper describes a metric for assessing the likelihood that a path delay fault is detectable. Path selection procedures should prefer such faults in order to yield sets of target faults that are detectable even if not all the undetectable faults are identified prior to test generation. The metric is defined such that it allows all the path delay faults with the same value of the metric (the same likelihood of being detectable) to be enumerated together. The metric is computed based on the numbers of detections of transition faults under a test set for such faults, and requiresN-detection fault simulation of transition faults for a sufficiently large value ofN. The results of test generation for path delay faults confirm that faults with higher values of the metric are more likely to be detectable.

The size of a diagnostic test set is significantly larger than the size of a fault detection test set. As a result, fault detection test sets may be used for initial defect diagnosis, and diagnostic tests may be added as needed to narrow down a set of candidate defect sites. Between a fault detection test set and a full diagnostic test set there is a large range of test sets that can be used for improved (initial) diagnosis. This paper describes a diagnostic test generation process that produces such a range of test sets. The process is based on a ranking of the indistinguished fault pairs according to the importance of distinguishing them. The ranking is based on the structural distance between faults. This allows failure analysis to explore fewer and more localized areas of the circuit as the size of the diagnostic test set is increased. This paper also discusses the insertion of observation points to distinguish fault pairs that remain indistinguished by a diagnostic test set. Observation point insertion uses the ranked list of indistinguished fault pairs to ensure that a limited number of observation points will address the fault pairs that are the most important to distinguish.

Ann-detection test set detects each target faultntimes. A higher value ofnincreases the likelihood that defects around the site of a target fault will be detected. However, ann-detection test set that consists of single-pattern tests (generated for single stuck-at faults) cannot guarantee that delay defects will be detected. For this it is necessary to use multi-pattern tests. The procedure described in this work generates a multi-patternn-detection test set for single stuck-at faults. The procedure is applied starting from a single-patternn-detection test set for single stuck-at faults. Experimental results demonstrate that the multi-patternn-detection test set achieves a high transition fault coverage. It achieves a similar bridging fault coverage to the single-pattern test set. An added advantage is that the multi-pattern test set typically requires significantly fewer clock cycles for test application than the single-pattern test set.

Test sets that contain both broadside and skewed-load tests are important for achieving the highest possible delay fault coverage for standard-scan circuits. Both types of tests can be represented as 〈s1, v1, s2, v2〉, where s1and s2are states, and v1and v2are primary input vectors. To facilitate the generation of a mixed test set that contains both broadside and skewed-load tests, this paper associates with s2a property that can be used for estimating whether a skewed-load or a broadside test is more likely to exist with s2in its second pattern. This paper uses this property for guiding a test generation procedure to consider only one of the two test types for most of the target faults.

The use of n-detection test sets increases the likelihood of defect detection. With a uniform value of for all the target faults, the expectation is that defects across the circuit will be covered uniformly. This paper demonstrates that this may not be the case by considering the four-way bridging faults detected by n-detection test sets for single stuck-at faults in benchmark circuits. Partitioning the bridging faults into subsets according to their dominated line, the results show that certain subsets have significantly lower bridging fault coverage than others. Thus, certain defect sites are significantly less covered than others. This paper also shows that it is possible to predict which subsets will have low bridging fault coverage based on the numbers of detections of single stuck-at faults under a conventional one-detection test set. This observation leads to a simplified n-detection test generation strategy. It also points to the possibility of using higher numbers of detections for certain single stuck-at faults, or targeting other fault models only at the sites that are expected to be less covered.

The conventional detection conditions for transition faults do not predict fault effects that may be created when transition faults are activated and/or propagated by pulses (or hazards). For this, detection conditions that take hazards into consideration need to be used. However, since the occurrence of pulses cannot be predicted accurately based on a gate-level circuit description, the transition fault model becomes more susceptible to pattern-dependent effects, where errors on observed outputs that are predicted by the fault model may not appear in a circuit-under-diagnosis. This paper considers the implications of these pattern-dependent effects on the resolution of fault diagnosis based on transition faults.

Recently a new method called ATE assisted compaction for achieving test response compaction has been proposed. The method relies on testers to achieve additional compaction, without compromising fault coverage, beyond what may already be achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be used with any design including legacy designs. In this work, we enhance this method so that the level of diagnostic resolution achieved without it can be maintained. Experimental results on larger ISCAS-89 show that additional test response compaction can be achieved while diagnostic resolution for single and double stuck-at faults is not adversely impacted by the procedure.

When multiple defects are present in a chip, the defects may be distributed randomly, or clustered in certain areas. When a large number of defects are clustered in an area, the possibility that their effects will interact is stronger than when they are fewer and further apart. This paper demonstrates that this reduces the accuracy of fault diagnosis based on single faults. Specifically, with the same diagnosis procedure based on single faults and the same number of faults injected into a circuit, random subsets of transition faults are easier to diagnose than clusters. The paper also develops a fault diagnosis procedure based on single faults that provides more accurate results for large clusters. The procedure considers limited numbers of double transition faults in order to obtain better matches for the cluster being diagnosed.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using simple hardware, and can achieve high transition fault coverage for testable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states off-line.

It was recently observed that the methods to generate scan based tests with low switching activity cause about 40% less activity than functional tests. Thus such tests may cause test escapes as they may not adequately stress the circuits under test. In this work we propose a method called Max-Fill to generate high quality partially-functional broadside delay tests. The generated tests are shown to cause switching activity close to the switching activity during functional operation. The method computes a set of reachable states in which states are likely to cause high switching activity. During test generation phase, these states are used as background states to fill the unspecified bits of test cubes. Additionally, the number of test patterns produced is less than that produced by low power test methods. Experimental results for ISCAS-89 circuits are given.

This paper studies issues related to transition fault diagnosis using multicycle broadside tests that are applied at-speed. Two transition fault models were proposed earlier for at-speed simulation, referred to as d-faults and x-faults. Both fault models account for the extra delay of a transition fault in order to allow at-speed simulation. However, they differ in the following ways. (1) The number of x-faults is equal to the number of conventional transition faults, while the number of d-faults grows with the number of cycles in a test. (2) Output responses of x-faults contain unspecified values that result in lower diagnostic resolution. The paper describes a fault diagnosis procedure that combines the use of x-faults for efficiency with the use of d-faults for diagnostic resolution.

For most purposes, it is sufficient for a low-power test set to ensure that the power dissipation during test application will not exceed that possible during functional operation. This is guaranteed for the fast functional capture cycles of functional broadside tests. This paper describes a procedure that generates broadside test sets with bounded switching activity during fast functional capture cycles based on the maximum switching activity of a functional broadside test set, targeting transition faults in full-scan circuits. The procedure first generates a compact functional broadside test set. It then extends the test set in steps in order to increase its fault coverage to that of an arbitrary broadside test set (a test set that includes non-functional broadside tests). During these steps, the maximum switching activity of the functional broadside test set is used for bounding the switching activity.

This paper describes a diagnostic test generation procedure for transition faults that produces mixed test sets consisting of broadside and skewed-load tests. A mix of broadside and skewed-load tests yields improved diagnostic resolution compared with a single test type. The procedure starts from a mixed test set generated for fault detection. It uses two procedures to obtain new tests that are useful for diagnosis starting from existing tests. Both procedures allow the type of a test to be modified (from broadside to skewed-load and from skewed-load to broadside). The first procedure is fault independent. The second procedure targets specific fault pairs. Experimental results show that diagnostic test generation changes the mix of broadside and skewed-load tests in the test set compared with a fault detection test set.

Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This paper describes a static test compaction procedure for such mixed test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Experimental results demonstrate that the procedure is able to reduce the sizes of available mixed test sets significantly. Moreover, it modifies the types of significant numbers of tests before including them in the compacted test set.

Transition faults are used for modeling delay defects. A comparison between transition faults and single stuck-at faults indicates that many more transition faults than single stuck-at faults in standard-scan circuits are undetectable. Furthermore, this paper shows that undetectable transition faults in benchmark circuits appear in larger clusters than single stuck-at faults, where a cluster consists of several undetectable faults that are included in the same connected subcircuit. This implies that test sets for transition faults do not cover delay defects uniformly across the circuit. The paper studies the clustering of undetectable transition faults in standard-scan benchmark circuits by considering exhaustive as well as deterministic test sets. It defines double transition faults that provide targets for improving the coverage of subcircuits with undetectable transition faults, and presents the results of test generation.

The use of multi-cycle (or multi-pattern) tests for delay faults can reduce the number of clock cycles required for test application, and enhance the ability of a test set to detect delay defects. This is achieved by exercising the circuit in functional mode for several clock cycles as part of each test. This advantage is especially important for multi-pattern functional broadside tests, which guarantee normal functional operation conditions during the functional clock cycles of the test. This paper describes a procedure for generating multi-pattern broadside tests. The procedure extends a two-pattern test set gradually to increase the number of patterns included in each test while reducing the number of tests. Experimental results demonstrate that significant reductions in the numbers of clock cycles are possible with the proposed procedure for both functional and arbitrary broadside test sets.

The power dissipation during the application of scan-based tests can be significantly higher than during functional operation. An exception is the second, fast functional capture cycles of functional broadside tests, where it is guaranteed that the power dissipation will not exceed that possible during functional operation. The power dissipation during the other clock cycles of functional broadside tests is studied here for the first time. The clock cycles under consideration are referred to as scan shift cycles. This paper describes a test generation procedure that limits the power dissipation during scan shift cycles of functional broadside tests. Experimental results for benchmark circuits demonstrate the extent to which the power dissipation during scan shift cycles can be limited without affecting the transition fault coverage.

The complexity of deterministic sequential test generation for a target fault in a circuit withnprimary inputs is determined by the need to explore a search space that consists of 2nprimary input vectors at every time unit. This paper studies the possibility of reducing the complexity of deterministic sequential test generation by using subsets of primary input vectors of limited sizes during test generation for target faults. It considers a test generation procedure that uses subsets of primary input vectors of sizeN, for increasing values ofNstarting withN=1 . The subsets consist of primary input vectors from the test sequence already generated, and of random primary input vectors. The results indicate that all or most of the detectable single stuck-at faults in benchmark circuits can be detected using small subsets of primary input vectors.

Transparent-scan is a test application scheme for scan circuits. It provides unique opportunities for test compaction that do not exist with the standard test application scheme. We show that it also provides unique opportunities for reducing the power dissipation of a scan-based test set. After translating a standard scan-based test set into a transparent-scan sequence, we apply two operations for reducing the power dissipation of the sequence. The first operation attempts to remove a test vector that causes high power dissipation. The second operation attempts to replace a scan clock cycle with a functional clock cycle, or a functional clock cycle with a scan clock cycle, in order to reduce the power dissipation. Both operations are implemented such that they reduce the power dissipation without reducing the fault coverage. We also consider a third operation that attempts to complement arbitrary values in the transparent-scan sequence in order to further reduce the power dissipation.

One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as complements to skewed-load and broadside tests, and also allows them to be computed efficiently. We discuss these properties in the context of transition faults. We describe procedures for selecting the constant vector for the state inputs during a scan operation, and for generating fixed-state tests. We present experimental results to demonstrate the transition fault coverage improvements possible with these tests.

We consider the use of necessary assignments for input lines, referred to as input necessary assignments, as part of a test generation process for path delay faults in standard-scan circuits. Input necessary assignments are computed in polynomial time and provide a unified framework for identifying undetectable faults and generating tests for detectable faults. Within this framework, large numbers of path delay faults can be considered efficiently and accurately. The proposed test generation procedure is able to resolve large numbers of path delay faults associated with the longest paths in benchmark circuits by detecting the faults using broadside tests or showing that they are undetectable by such tests. We also consider the use of input necessary assignments for test compaction.

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the second capture cycle. As a result, a functional broadside test may detect faults that cannot affect functional operation (redundant faults). Addressing this issue completely requires full sequential test generation. We discuss an alternate solution that fits naturally with an existing process for generating functional broadside tests.

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests were defined and studied in the context of full-scan circuits. In this work, we study the definition of broadside and functional broadside tests in partial-scan circuits. A unique property we show is that if the unscanned state variables are observable (through the application of input sequences or through observation points), the fault coverage achievable with functional broadside tests is independent of the level of scan and the subset of scanned state variables. This implies that when functional broadside tests are used to avoid overtesting, using lower percentages of scanned state variables may be possible without reducing the fault coverage significantly. Experimental results support this point.

Both test compaction and test data compression methods provide an opportunity for a tester to apply modified versions of each test, in addition to the original test. We take advantage of this opportunity to achieve additional test data volume reductions. One way to modify a test is to complement some or all of its bits. We represent the way in which modified tests will be obtained by a complementation vector. Experimental results demonstrate that, even when a test set has minimum or close-to-minimum size, the use of a complementation vector allows us to reduce the size of the stored test set further, and almost always below the known lower bound on the size of a test set. The use of a complementation vector is equivalent to a modulo-2 addition operation. We generalize it to modulo-Maddition, for a constantM≥ 2. With modulo-Maddition, each stored test yields up toMtests. It is thus possible to reduce the size of the stored test set even further.

We describe a storage scheme for functional test sequences where a test sequenceTis associated with a primary input vectorBcalled a background vector.Tis stored by storing only the differences between its test vectors andB. We describe a procedure for computing a background vectorBfor a given test sequenceT. We also describe a procedure that modifiesTso as to reduce its storage requirements with respect toB. We present experimental results demonstrating that the single background vectorB, computed based onT, allowsTto be modified such that a vast majority of its entries are equal to the corresponding entries ofB. Consequently, storage ofTreduces to storage of a small number of entries. We also extend the discussion to storage ofTbased on two background vectors. A second background vector provides more flexibility in storingTas a list of entries where it is different from its background vectors. This contributes to a further reduction in storage requirements for certain circuits.

We define the strength of a test for transition faults based on the number of fault effects that can disappear without causing the test to lose the detection of target faults. The removal of fault effects represents the uncertainty created by pattern-dependent effects that can slow-down or speed-up signal-transitions, thus causing fault effects predicted by logic-level simulation to disappear. A test set that consists of higher-strength tests is less susceptible to these effects. We demonstrate that a transition fault test set with higher-strength tests also detects more path delay faults, which represent delay defects that were not targeted during test generation.

Functional broadside tests were defined to address overtesting that may occur with unrestricted scan-based tests. However, the fault coverage achievable by functional broadside tests is lower than the fault coverage achievable by unrestricted scan-based tests. It was observed that skewed-load tests can improve the fault coverage achievable by unrestricted broadside tests. Motivated by these observations, we define functional (and partially-functional) skewed-load tests to improve the fault coverage of functional broadside tests while attempting to curb overtesting. We present experimental results to demonstrate the ability of functional skewed-load tests to improve the fault coverage without exceeding the maximum switching activity of functional broadside tests (which is one indication of potential overtesting).

A test for a delay fault can be considered as covering a transition on one or more lines. A bias in the transition coverage of a delay test set implies that more rising or more falling transitions are covered by the test set. Such a bias is not captured by fault coverage metrics that consider both types of transitions together. We study the bias in the transition coverage of test sets for path delay faults. The results demonstrate that the bias is circuit-dependent. It also depends on the type of two-pattern tests used. In general, broadside tests show more bias than skewed-load tests, while enhanced-scan tests show little bias. We also consider the use of partial-enhanced-scan for reducing the bias exhibited by broadside tests.

We describe a storage scheme for functional test sequences where a test sequence T is associated with a primary input vector B called a background vector. T is stored by storing only the differences between its test vectors and B. We describe a procedure for computing a background vector B for a given test sequence T. We also describe a procedure that modifies T so as to reduce its storage requirements with respect to B. We present experimental results demonstrating that the single background vector B, computed based on T, allows T to be modified such that a vast majority of its entries are equal to the corresponding entries of B. Consequently, storage of T reduces to storage of a small number of entries.

Functional broadside tests were defined to avoid overtesting that may occur under structural scan-based tests. Overtesting occurs due to non-functional operation conditions created by unreachable scan-in states. Functional broadside tests were computed assuming that functional operation starts after the circuit is synchronized. We discuss the definition of functional broadside tests for the case where hardware reset is used for bringing the circuit into a known state before functional operation starts. We show that the set of reachable states for a circuit with hardware reset contains the set of reachable states based on a synchronizing sequence. Consequently, the set of functional broadside tests and the set of detectable faults for a circuit with hardware reset contain those obtained based on a synchronizing sequence. In addition, there are differences between different reset states in the sets of reachable states and the sets of detectable faults.

The concept of test vector chains was introduced in the context of simulation-based test generation. Test vector chains provide a specific algorithm for performing single-bit changes in order to obtain new test vectors from existing ones. In this algorithm, two test vectors tη and ti2 are used. The test vector chain C(tn,ti2) is obtained by gradually modifying tη into ti2. Starting from tη, each additional test vector in C(tn,ti2) is one bit further from tη and one bit closer to ti2 until ti2 is obtained. It was demonstrated that a test set T has a significant number of test vector chains that are effective in (1) increasing the numbers of detections of faults that were targeted during the generation of Γ; (2) increasing the fault coverage of faults that were not targeted during the generation of Γ; and (3) increasing the fault coverage of target faults when T does not detect all the target faults.

A deterministic broadside test generation procedure is proposed for transition path delay faults. Under this fault model, a path delay fault is detected if and only if all the individual transition faults along the path are detected by the same test. This is important for detecting both small and large delay defects. To handle the complexity of test generation, the procedure consists of five sub-procedures: a test generation procedure for transition faults, a preprocessing procedure that identifies undetectable transition path delay faults without performing test generation, a fault simulation procedure that identifies transition path delay faults that are detected by the tests for transition faults, a heuristic procedure similar to dynamic test compaction for transition faults that generates tests without backtracking on decisions made for previously detected faults, and a complete branch-and-bound procedure. Experimental results show that for most of the transition path delay faults in benchmark circuits either a test is found or the fault is identified as undetectable.

The existence of multiple copies of the same functional units in a design allows on-line testing to be performed by comparing the output responses of identical circuits when identical input sequences are applied to them. We extend the output response comparison scheme for identical sequential circuits in order to increase the fault coverage and reduce the fault latency of an unknown input sequence. The extension is based on using state variables in addition to primary outputs as part of the output response comparison scheme. The proposed procedure orders the state variables of the circuits such that each additional state variable in the ordered list has the highest possible impact on the on-line testability of the circuits. Depending on other constraints, the first state variables in the list can be selected for inclusion in the output response comparison scheme.

The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work to show that such tests can also be used for testing additional transistor stuck-open faults. Experimental results for coverage improvement in several ISCAS-89 benchmark circuits will be discussed.

Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.

A multi-cycle (or multi-pattern) scan-based test consists of several primary input patterns, which are applied consecutively in functional mode, between scan operations. Multi-cycle tests can reduce the total number of cycles needed to achieve a target fault coverage. Additionally, such tests exercise the circuit in its functional mode of operation during several clock cycles where the primary input patterns are applied. This is important for detecting defects that are not detected with two-pattern scan-based tests. However, a complete test generation process for multi-pattern tests requires sequential test generation. To generate multi-pattern tests with arbitrary numbers of patterns without performing full sequential test generation, and targeting delay faults, we use a broadside test set as a basis for test generation. We introduce the operation of concatenating broadside tests, and describe a procedure that uses it to form multi-cycle tests. We present experimental results demonstrating that the test sets require significantly fewer test cycles than broadside test sets, for the same transition fault coverage.

Multiple faults are typically detected by test sets for single faults. For bridging faults, we show that fault activation conditions are more difficult to create for certain multiple faults than for the single faults that comprise them. As a result, a test set for single bridging faults may leave significant percentages of detectable multiple faults undetected. We discuss three such cases, corresponding to three types of bridging faults, and present experimental results for one of them. As part of this study we consider the ability of a 10-detection test set for single stuck-at faults to detect multiple bridging faults of this type.

Equivalence and dominance relations used earlier in fault diagnosis procedures are defined as relations between faults, similar to the relations used for fault collapsing. Since the basic entity of diagnostic fault simulation and test generation is a fault pair, and not a single fault, we introduce a framework where equivalence and dominance relations are defined for fault pairs. Using equivalence and dominance relations between fault pairs, we define a fault pair collapsing process, where fault pairs are removed from consideration under diagnostic fault simulation and test generation since they are guaranteed to be distinguished when other fault pairs are distinguished. Another concept, which was used earlier to enhance fault collapsing, is the level of similarity between faults. We extend this definition into a level of similarity between fault pairs and discuss its use for fault pair collapsing. The level of similarity encompasses equivalence and dominance relations between fault pairs, and extends them to allow additional fault pair collapsing.

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cubetis generated at an arbitrary iteration of the test generation process, the test vector improvement step modifiestso as to increase the number of yet-undetected target faults thattdetects. This is done in this paper using a simulation-based process. We show that even iftwas generated using dynamic test compaction heuristics, it is possible to improvetfurther. Whentis partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits oft. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).

We demonstrate that undetectable single stuck-at faults in full-scan benchmark circuits tend to cluster in certain areas. This implies that certain areas may remain uncovered by a test set for single stuck-at faults. We describe an extension to the set of target faults aimed at providing a better coverage of the circuit in the presence of undetectable single stuck-at faults. The extended set of target faults consists of double stuck-at faults that include an undetectable fault as one of their components. The other component is a detectable fault adjacent to the undetectable fault. We present experimental results of fault simulation and test generation for the extended set of target faults.

Transition path delay faults were defined to capture the behavior of both small and large delay defects in a single fault model. The number of detectable transition path delay faults as defined earlier is the same or close to the number of conventional path delay faults that are detectable under the strong non-robust propagation conditions. When the weak non-robust propagation conditions are used, the number of detectable conventional path delay faults is significantly higher. Using what are called the hazard-based detection conditions for transition faults, we define detection conditions for transition path delay faults, under which the number of detectable faults is the same or close to the number of conventional path delay faults that are detectable under the weak non-robust propagation conditions. The fault model still captures the behavior of both small and large delay defects, but the number of detectable faults is significantly higher.

The presence of an undetectable faultuimay modify the response of a detectable faultdjto a test set used for fault diagnosis. This may impact the accuracy of fault diagnosis based on the responses of single faults. Many state-of-the-art diagnosis processes are based on the responses of single stuck-at faults even though their goal is to diagnose defects (including multiple defects) that are different from stuck-at faults. Therefore, we study the effects of undetectable single stuck- at faults on the accuracy of fault diagnosis based on the responses of single stuck-at faults. For this purpose, we consider the cases where the response of a double stuck-at faultui&dj, which consists of an undetectable faultuiand a detectable faultdj, is different from the response of the single faultdj. We show that there are significant, yet manageable, numbers of such faults in benchmark circuits under test sets used for fault diagnosis. In all these cases, a fault diagnosis process based on single stuck-at faults may not identify the locations ofdjanduias candidate defect sites if a defect affects the sites ofdjandui. We conclude that it is important to considerui&djduring fault diagnosis in order not to preclude the sites ofdjanduias candidate defect sites.

We define a new type of detection conditions for delay faults, referred to as hazard-based detection conditions, to enhance the coverage of delay faults using the standard scan test application methods. Some delay faults, including irredundant faults, may be undetectable under the conventional detection conditions. These faults may be detectable under the hazard-based detection conditions. The use of hazard-based detection conditions thus improves the delay fault coverage achievable for a circuit. We consider transition faults under standard scan for the study in this paper.

We propose a path selection criterion to improve the coverage of small delay defects. Under this criterion, every line in the circuit is covered by one of the longest testablepaths or subpathsthat goes through it. Earlier criteria that considered only complete paths (from inputs to outputs) did not use longest testable subpaths, which may be longer than the longest complete testable paths. Earlier criteria that considered subpaths considered only subpaths of longest paths. We apply the proposed criterion to a delay fault model called the transition path delay fault model. This model was introduced to capture both small and large delay defects. We present experimental results to demonstrate that consideration of subpaths improves the circuit coverage relative to the case where only complete paths are allowed.

We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. This is important since it provides a direct link between test quality and the circuit synthesis. We discuss robust fault models for bridging faults and interconnect open faults, and their use as part of a test generation process for a non-robust fault model.

The switching activity of scan-based tests for delay faults is considered as a test compaction heuristic. Two test compaction processes based on the switching activity are described. The results of several experiments are presented where test sets consisting of tests with different switching activity are compared based on their size as well as coverage of untargeted faults. The results demonstrate that test sets where the tests have higher switching activity are smaller. Their untargeted fault coverage is comparable, and sometimes even higher, than that of larger test sets for the same target faults. To avoid overtesting due to high switching activity it is possible to consider functional broadside tests. For other types of tests it is possible to bound the switching activity such that it would not exceed that possible during functional operation.

In this paper, we describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selected. This step allows fault diagnosis to be performed based on a single fault model after identifying the most appropriate one. We describe a specific implementation of this preprocessing step based on what is referred to as the unique output response of a fault model. As an example, we apply it to the diagnosis of multiple stuck-at faults, selecting between single and double stuck-at faults as the fault model for diagnosis. Experimental results demonstrate improvements compared to diagnosis based on single stuck-at faults, and compared to diagnosis based on both single and double stuck-at faults. We also discuss the use of a subset of double stuck-at faults for diagnosis, and the application of the proposed preprocessing step with other fault models.

A recent approach to test generation avoids the assignment of certain input values in order not to prevent target faults from being detected. The test generation process based on this approach is efficient; however, it generates large test sets. We develop a dynamic test compaction procedure for this approach. Our goal is to reduce the test set size by increasing the number of faults detected by each test vector, while keeping the computational complexity as low as that of the original procedure. This is achieved by avoiding the assignment of certain input values in order not to prevent subsets of faults from being detected.

Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed new flush tests and appropriate ordering of flush tests to achieve higher fault coverage. In this paper, we investigate detection of a set of scan cell internal bridging faults extracted from layout. We show that the detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. Half-speed flush tests we proposed earlier to improve the coverage of stuck-at, stuck-on and stuck-open faults also detect additional bridging faults. We classify the undetectable faults based on the reasons for their undetectability. We observe that the driver strengths of the scan cell inputs can be optimized to improve the bridging fault coverage. Both zero-resistance and nonzero-resistance bridging fault models are considered in this work. A low power supply voltage based test method and IDDQ testing are examined for resistive bridging fault detection.

Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that for using n-detection test sets to improve the detection of unmodeled defects. We use a heuristic to target a subset of fault pairs for n-distinguishing in order to improve the efficacy of the patterns generated for aiding diagnosis. Experimental results on the larger ISCAS benchmark circuits are presented to demonstrate the improvements in defect diagnostic resolution due to the use of n-distinguishing test sets. We use randomly selected resistive bridges to represent unmodeled defects. The experimental results also show that the coverage of unmodeled defects by n-distinguishing test sets is similar to that by n-detection test sets even though the number of n-distinguishing tests is typically smaller. This suggests the possibility of using n-distinguishing test sets in place of n-detection test sets in manufacturing test.

Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number of stuck-at fault pairs it distinguishes. We use the static test compaction process as part of a process that constructs the transparent-scan sequence gradually, using test compaction to prevent the length of the sequence from becoming unnecessarily long.

We describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selected. This step allows fault diagnosis to be performed based on a single fault model after identifying the most appropriate one. We describe a specific implementation of this preprocessing step based on what is referred to as the unique output response of a fault model. As an example, we apply it to the diagnosis of multiple stuck-at faults, selecting between single and double stuck-at faults as the fault model for diagnosis. Experimental results demonstrate improvements compared to diagnosis based on single stuck-at faults, and compared to diagnosis based on both single and double stuck-at faults.

This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG.

We define the notion of a lingering synchronization effect. Such an effect occurs when a primary input cube (an incompletely-specified primary input vector) determines the state of a circuit for several time units after it is applied. Such a primary input cube may prevent certain faults from being detected when it appears in a test sequence. It should therefore be avoided when the goal is to achieve a high fault coverage. We demonstrate that benchmark circuits have primary input cubes with small numbers of specified values (typically one or two), which have lingering synchronization effects. In some cases, the synchronization effects linger for large numbers of time units. We also describe a random test generation process that avoids primary input cubes with lingering synchronization effects, and achieves high fault coverage for benchmark circuits.

We describe a method for improving the quality of n-detection test sets. Unlike earlier methods for achieving the same goal, the proposed method is based on the conventional definition of the number of detections and uses a conventional n-detection test generation process. Under the proposed method, the set of target faults is partitioned into two or more subsets. n-detection test generation is carried out for each subset separately. The resulting test sets are combined into a single test set. Partitioning causes more faults to be targeted directly, and fewer faults to be dropped due to accidental detection. The fault subsets can be selected based on detection conditions of common defects. In this work we partition the set of faults into a subset that consists of all the stuck-at 0 faults, and a subset that consists of all the stuck-at 1 faults. We demonstrate through experimental results that for the same test set size, partitioning the set of faults improves the coverage of untargeted faults (non-feedback four-way bridging faults) compared to n-detection test generation for the unpartitioned set of faults.

A necessary assignment for a fault f is a line value that must be assigned by a test vector that detects f. A higher number of necessary assignments translates into a lower test generation effort since the test generation process has a larger number of values that it must assign, and therefore, fewer options that it can explore. To increase the number of available necessary assignments, we define approximate necessary assignments as line values that are assigned by most of the test vectors for a fault. We describe a heuristic procedure for computing approximate necessary assignments for inputs and demonstrate their effectiveness in reducing the test generation effort of a random test generation process.

We study a property of circuit states referred to as persistence. The persistence pi(s) of a state s is the number of next-state variables whose values are specified (0 or 1) when a fully-unspecified primary input vector is applied to the circuit in state s. When a next-state variable Yi is specified under a fully-unspecified primary input vector, there are faults in the input cone of Yi that cannot be detected on Yi. We demonstrate through experimental results that when lower-persistence states are used as scan-in states, the resulting tests detect larger numbers of faults. Low-persistence states are thus preferable as scan-in states during test generation. We also discuss the computation of low-persistence states.

The functional operation of a synchronous sequential circuit is defined to start after the circuit is initialized to a known state, typically by a synchronizing sequence. The states that the circuit can visit after it is synchronized are called reachable states, and functional operation consists of state transitions between reachable states. We expand the definition of functional operation to include all the state transitions that may be traversed during the application of the synchronizing sequence. This adds certain state transitions that involve unreachable states to the definition of functional operation. Expanding the definition of functional operation is justified by the fact that the circuit needs to be designed for correct operation during the synchronization process. It is advantageous when functional broadside tests are used to avoid overtesting. We study the effect of the expanded definition on the coverage of transition faults.

In this paper, we describe a new transition fault model for synchronous sequential circuits. Similar to previous models, it addresses the fact that delayed signal-transitions span multiple clock cycles when a test sequence is applied at-speed. It addresses this issue in a different way than earlier models. The model requires the activation of single stuck-at faults with opposite stuck-at values on the same linegat consecutive time units. In addition, it requires the detection of both faults (as single faults) at the same or later time units. Due to the activation of the faults at consecutive time units, there is a 1 rarr 0 or 0 rarr 1 transition at the fault siteg. Since both faults are eventually detected, a deviation from the expected value at either the first or second time unit due to a delay fault ongor due to transitions that started earlier and did not settle will be (or is likely to be) detected. The model can be used together with other models to increase the confidence that delay defects will be detected. As an added advantage, the model helps detect other types of faults that require two-pattern tests, such as transistor stuck-open faults.

We extend the concept of forward-looking reverse order fault simulation ton-detection test sets. Forward-looking reverse order fault simulation is an efficient static test compaction process similar to reverse order fault simulation, but with the advantage that it results in test sets that do not contain any unnecessary tests. The application of test compaction procedures ton-detection test sets is important since the test sets are larger than conventional test sets. We demonstrate that forward-looking reverse order fault simulation produces smaller test sets than reverse order fault simulation and measure the quality of the resulting test sets by their bridging fault coverage.

We describe a method for online testing of delay faults based on the comparison of output responses of identical circuits. The method allows one of the circuits to participate in useful computations during the testing process, while the other circuit must be idle. We refer to this method as semiconcurrent online testing. While unknown input vectors are applied to the circuit that participates in useful computations, the proposed method applies modified vectors to the idle circuit. In this way, different conditions are created for the detection of delay faults, allowing identical delay faults that affect both circuits to be detected. In designing the modified vectors, we ensure that the expected fault-free responses of the two circuits are identical. We also ensure that the hardware for modifying the vectors applied to the idle circuit will be easy to implement on-chip.

In enhanced-scan circuits, a two-pattern test < t i , t j > for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test < t i , t j > based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We investigate a complementary view whereby the goal is to avoid the assignment of certain input values in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Other potential uses of the computed input cubes are in a deterministic test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults. We consider stuck-at faults in full-scan circuits. We also extend the discussion to four-way bridging faults.

A procedure proposed earlier for improving the fault coverage of a random primary input sequence modifies the input sequence so as to avoid repeated synchronization of state variables. We show that in addition to the values of state variables, it is also important to consider repeated setting of other lines to the same values. A procedure and experimental results are presented to demonstrate the improvements in fault coverage of random primary input sequences when the values of selected lines are considered.

We introduce the concept of test vector chains, which allows us to obtain new test vectors from existing ones through single-bit changes without any test generation effort. We demonstrate that a test setT0has a significant number of test vector chains that are effective in increasing the numbers of detections of target faults, i.e., faults targeted during the generation ofT0, as well as untargeted faults, i.e., faults that were not targeted during the generation ofT0.

A methodology using design-for-manufacturability (DFM) layout guidelines as a basis for modeling and detecting systematic defects was proposed earlier. In this paper, we show that this methodology can be extended to prioritize layout locations according to the importance of applying DFM guidelines to them. Prioritization is done based on test considerations including coverage and test set size. In particular, this methodology can identify layout locations where failure to follow a DFM guideline may result in test holes due to hard-to-detect defects. The prioritized list can be used by layout tools to create circuits that are easier to test.

We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.

We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthesis of the circuit. The stuck-at fault model is robust, but other fault models such as certain bridging fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. The ability to achieve 100% fault coverage, or understand why it is not achievable, is important since the requirement to achieve high test quality translates into a requirement to achieve complete fault coverage for target faults, regardless of the metrics used to measure test quality. We discuss a robust bridging fault model and its use as part of a test generation process for a non-robust bridging fault model (a non-robust bridging fault model may have to be used in order to capture the behavior of bridging defects). We also present experimental results related to the robust bridging fault model.

We describe a new type of fault dictionary called a same/different fault dictionary. The same/different fault dictionary is similar to a pass/fail fault dictionary in that it contains a single bit bijfor every modeled fault fiand test vector tj. However, in a pass/fail fault dictionary, bijis determined by comparing the output vector of the faulty circuit with the output vector of the fault free circuit; while in a same/different fault dictionary, bijis determined by comparing the output vector of the faulty circuit with a preselected output vector called a baseline output vector. By selecting appropriately the baseline output vectors for all the test vectors, it is possible to obtain increased diagnostic resolution with a same/different fault dictionary compared to a pass/fail fault dictionary. We describe a procedure for selecting baseline output vectors and present experimental results.

For fault models with large numbers of faults, such as bridging faults, fault collapsing based on dominance relations can be effective in reducing the test generation time by reducing the number of target faults. When dominance relations are used for fault collapsing, a fault fjis excluded from the set of target faults F if it dominates a fault fiin F. However, if firemains undetected after test generation, fjmay remain undetected as well. We define safe fault collapsing to address this issue. For safe fault collapsing with a parameter s, fjis excluded from the set of target faults F only if fjdominates at least s faults fi1,fi2, hellip ,fisin F. In this way, if any of the s faults dominated by fjis detected, fjwill be detected as well. A higher value of s increases the likelihood of detecting fjwithout targeting it. We describe a procedure for computing safe collapsed fault sets, and present experimental results of test generation for four-way bridging faults.

The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture to detect such defects is proposed. Unlike other sequences, like checking experiments, the enhancements are simple and independent of the circuit under test.

Nearly half of the transistors in the logic parts of large VLSI designs typically reside inside scan cells. Faults in scan cells may affect functional operation if left undetected. Such undetected faults may also affect the long term reliability of shipped products. Nevertheless, current test generation procedures do not directly target faults internal to the scan cells. Typically it is assumed that scan chain tests, called flush tests, test the scan cells sufficiently. We showed that flush tests applied at slower clock rates, called half-speed flush tests, and tests for scan cell inputs and outputs, detect stuck-at and stuck-on faults internal to scan cells to a similar extent as checking sequence based tests proposed earlier. In this work, we investigate the detection of opens in transistors internal to scan cells. A new flush test and a new method to apply flush tests are proposed to greatly enhance the coverage of opens. We also propose new scan based tests to further increase the coverage of opens. The proposed tests are shown to achieve the maximum possible coverage of opens in transistors internal to scan cells.

We describe a synthesis-for-testability approach targeting broadside testing of transition faults. We refer to this process as synthesis for broadside testability. Unlike design-for-testability (DFT) procedures that require additional control inputs to implement DFT modes of operation, synthesis for broadside testability uses only the standard scan design and relies on broadside tests to detect target faults. The proposed procedure improves the testability of a circuit by changing next-states of state- transitions from its unreachable states, i.e., states that the circuit cannot enter during functional operation. In this way, it replaces broadside tests of the original circuit with new broadside tests that are more effective in detecting target faults.

Functional operation of a synchronous sequential circuit is defined to start after the circuit is initialized to a known state, typically by a synchronizing sequence. The states that the circuit can visit after it is synchronized are called reachable states, and functional operation consists of state-transitions between reachable states. We expand the definition of functional operation to include all the state-transitions that may be traversed during the application of the synchronizing sequence. This adds certain state-transitions that involve unreachable states to the definition of functional operation. Expanding the definition of functional operation is justified by the fact that the circuit needs to be designed for correct operation during the synchronization process. It is advantageous when functional broadside tests are used to avoid over- testing. We study the effect of the expanded definition on the coverage of transition faults.

Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.

It was shown before that tests applied under nonfunctional operation conditions, which are made possible by scanning in an unreachable state, may lead to unnecessary yield loss. To address this issue, functional broadside tests were defined as broadside tests that use only reachable states of the circuit as scan-in states. Earlier procedures for generating functional broadside tests were not complete, i.e., they did not always detect all the detectable faults or prove that all the undetectable faults are undetectable. In this paper, we address the completeness of the functional broadside tests for transition faults. We describe the implementation of a test-generation procedure that can, for every transition fault, either find a functional broadside test or prove that the fault is undetectable under the functional broadside tests. We present experimental results where complete results are achieved for almost all the benchmark circuits considered.

A transition fault model is described, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal-operation conditions. However, fault simulation and test generation for standard transition faults become significantly more complex due to the need to handle faulty signal transitions that span multiple clock cycles. As a result, each transition fault needs to be considered multiple times, with multiple sizes of the extra delay on the faulty line. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur, thus allowing faults of all possible sizes to be encompassed in a single fault. Fault detection potentially occurs when an unspecified value reaches a primary output. "Pessimistic," "optimistic," and "random" versions of the fault model and corresponding fault coverages are defined. If a single fault coverage is to be computed, the pessimistic one provides the lowest fault coverage. By using the optimistic or random version, it is possible to obtain a range of possible fault coverages that is analogous to the range of sizes of transition faults. For certain applications, it is also possible to include more than one version of every fault in a single set of target faults and to compute a single fault coverage. Experimental results of fault simulation and test generation are presented to demonstrate the behavior of the model and to compare it with other fault models.

Random test sequences may be used for manufacturing testing as well as for simulation-based design verification. This paper studies one of the reasons for the fact that random primary input sequences achieve very low fault coverage for synchronous sequential circuits. It is shown that a synchronous sequential circuit may have input cubes, or incompletely specified input vectors, that synchronize a subset of its state variables, i.e., it forces them to certain specified values. When an input cube c that synchronizes the subset of state variables S(c) has a small number of specified inputs, the input vectors covered by it may appear often in a random primary input sequence. As a result, the sequence will force the same values on the state variables in S(c) repeatedly. This may limit the fault coverage that the sequence can obtain. To address this issue, a procedure is described for modifying a random primary input sequence to eliminate the appearance of input vectors that synchronize subsets of state variables. It is demonstrated that this procedure has a significant effect on the fault coverage that can be achieved by random primary input sequences.

The peak power dissipated in nonscan logic during fast capture cycles of scan-based two-pattern tests for path delay faults is considered. It is first demonstrated that the peak-power dissipation for an enhanced-scan test set, which has the smallest peak-power dissipation, is lower than that for a skewed-load test set and that the peak-power dissipation for a skewed-load test set, which has the smallest peak-power dissipation, is typically (but not always) lower than that for a broadside test set. Test sets that consist of more than one type of tests are then considered. Skewed-load and broadside tests may be used together to improve the fault coverage when this is permissible by a standard scan design. It is demonstrated that using both types of tests can sometimes reduce the peak-power dissipation. Results are also presented of an experiment where an arbitrary test set of one type is modified to reduce the peak power without reducing the fault coverage by introducing tests of another type.

An n-detection test set contains different tests for each target fault. The value of is typically determined based on test set size constraints, and certain values have become standard. Appropriate values for are investigated in this paper by considering the saturation of the n-detection test generation process. As is increased, eventually, the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with drops below a certain level. Three parameters of an n-detection test set are introduced to measure the saturation of the test generation process: 1) the fraction of faults detected times or less by the test set; 2) the fraction of faults detected fewer than times by the test set; and 3) the test set size relative to the size of a one-detection test set. It is demonstrated that the behavior of each one of these parameters follows a unique pattern as is increased, and certain features of this behavior can be used to identify saturation. All the parameters can be efficiently computed during the test generation process.

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.

Functional broadside tests were defined to address overtesting that may occur due to high peak current demands when tests for delay faults take the circuit through states that it cannot visit during functional operation (unreachable states). The fault coverage achievable by functional broadside tests is typically lower than the fault coverage achievable by (unrestricted) broadside tests. A solution to this loss in fault coverage in the form of observation point insertion is described. Observation points do not affect the state of the circuit. Thus, functional broadside tests retain their property of testing the circuit using only reachable states to avoid overtesting due to high peak current demands. However, the extra observability allows additional faults to be detected. A procedure for observation point insertion to improve the coverage of transition faults is described. Experimental results are presented to demonstrate that significant improvements in transition fault coverage by functional broadside tests is obtained.

Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift test method has the advantage that it provides higher fault coverage at reduced test generation time and test pattern counts. However a concern expressed often in the literature is the potential over testing or yield loss caused by the fact that launch off shift operates the circuit under test in non-functional manner. In this paper we present data, for the first time, which points to another potential problem with launch off shift tests. The data presented for ISCAS-89 benchmark circuits shows that a considerable numbers of functionally detectable transition delay faults are not detected by the normally used launch off shift tests that use a single fault activation cycle. Functionally detectable faults that escape tests could cause circuit malfunction in normal operation. Thus launch off shift tests when used in manufacturing test may result in test escapes. We also present data that shows that if launch off shift tests with multiple fault activation cycles are used essentially all functionally detectable faults can be detected.

Functional test sequences were shown to detect defects that are not detected by structural tests. They also help in avoiding overtesting. However, fault simulation to compute the stuck-at fault coverage of functional test sequences can be time consuming especially in applications where a large number of test sequences need to be evaluated and compared. To obtain fast yet accurate estimates of the stuck-at fault coverages of functional test sequences, we describe a fault coverage metric based only on logic simulation of the gate level circuit. The metric is based on the set of states that the circuit traverses under the test sequence. We define several versions of the metric suitable for different applications. We present experimental results demonstrating the effectiveness of the metric for ranking of test sequences based on their fault coverage.

We describe a diagnostic test generation procedure that targets the equivalence classes of the test set as it is being generated, instead of considering one fault pair at a time (an equivalence class contains faults that are indistinguished by the test set). When an equivalence class is targeted, all the fault pairs in the equivalence class are targeted simultaneously. This reduces the number of test generation targets, and as a result, it reduces the number of tests in the final test set as well as the test generation time. The implementation of the diagnostic test generation procedure is based on a test elimination process that can accommodate equivalence classes of any size.

The use of multiple scan chains was shown to improve the coverage of transition faults achieved by skewed-load tests. For broadside tests, the number of scan chains does not affect the transition fault coverage. We describe an enhanced broadside configuration under which increasing the number of scan chains helps increase the fault coverage. In the enhanced configuration, the first flip-flop of a scan chain operates in skewed-load mode while the other flip-flops operate in broadside mode. This provides flexibility in determining the value of the first flip-flop of every scan chain under the second pattern of a broadside test, thus increasing the transition fault coverage. We also describe a procedure that makes small modifications to a given scan chain configuration in order to improve the transition fault coverage.

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values that should not be assigned to inputs in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Potential uses of the computed input cubes are in a test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults

We describe a diagnostic test generation procedure that deals with the large numbers of target fault pairs by considering subsets of faults. Each subset of faults is targeted separately during diagnostic test generation, and fault pairs are defined only out of the faults included in a subset. With M subsets of size K, the number of fault pairs considered is at most MK(K-1)/2 instead of N(N-1)/2 for a circuit with N target faults. Fault subsets can be defined using information about faults that are likely to be difficult or important to distinguish. In this work, fault subsets are defined based on structural analysis of the circuit.

With shrinking feature sizes of manufacturing processes, the occurrence of systematic defects is expected to increase. In this paper, we present techniques for identifying potential systematic defect candidates from design-for-manufacturing (DFM) layout guidelines. DFM guidelines are tightened to find layout locations as potential sites for systematic defects, affected transistors are identified at the schematic level, and defect behaviors are translated to gate level logic faults. Experimental results are presented on an Intel Pentiumê4 design for the evaluation of existing tests in screening systematic failures and identifying potential test holes. Additional test content is generated for improving test quality.

An n-detection test set contains n different tests for each target fault. The value of n is typically determined based on test set size constraints, and certain values have become standard. In this work we investigate appropriate values for n by considering the saturation of the n-detection test generation process. As n is increased, eventually the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with n drops below a certain level. We introduce three parameters of an n-detection test set to measure saturation of the test generation process: (1) the fraction of faults detected n times or less by the test set, (2) the fraction of faults detected fewer than n times by the test set, and (3) the test set size relative to the size of a one-detection test set. We demonstrate that the behavior of each one of these parameters follows a unique pattern as n is increased, and certain features of this behavior can be used to identify saturation. All the parameters are easy to compute during the test generation process.

Autoscan is a design-for-testability approach proposed earlier that uses scan chains without external scan inputs or outputs in order to reduce the test application time and test data volume of scan. We describe three improvements to the basic autoscan design-for-testability approach based on the following observation. Under autoscan, due to the elimination of external scan inputs, the first flip-flop of a scan chain can only receive its value from the corresponding next-state line. Thus, its state cannot be controlled directly by a scan operation. In the improved autoscan approach, we allow the inverted next-state line to drive the first flip-flop of a scan chain during scan operations. We refer to the improved autoscan approach as autoscan-invert. We describe a scan synthesis procedure appropriate for autoscan-invert and present experimental results.

The concept of invariant states of synchronous sequential circuits is defined. An invariant state is incompletely specified (i.e., it is a cube), and its specified state variables remain constant under any input vector. Invariant states provide a method to identify redundant logic, which may not be identified based on redundant stuck-at faults. A procedure for finding invariant states with maximal numbers of specified state variables is described. The process of finding redundant logic based on an invariant state is explained. Experimental results show that several large benchmark circuits have invariant states with large numbers of specified state variables, explaining why these circuits are untestable. Properties of invariant states in synchronizable circuits are also discussed

Generation of$n$-detection test sets is typically done for a single fault model. This paper investigates the generation of$n$-detection test sets by pairing each fault of a target fault model with$n$faults of a different fault model. Tests are generated such that they detect both faults of a pair. To facilitate test generation, the faults included in a single pair are selected such that they have overlapping requirements for their detection. The advantage of this approach is that it ensures the detection of additional faults that would not be targeted during the$n$-detection test generation process for a single fault model. Experimental results with transition faults as the first fault model and four-way bridging faults as the second fault model are presented.

Diagnostic fault simulation is used to determine the pairs of faults distinguished by a given test set or test sequence. Diagnostic test generation is used to generate tests that distinguish pairs of faults. Typically, the test sets or test sequences contain tests that detect all the detectable target faults. In this paper, a framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets. These characteristics are used to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set. Such fault pairs do not need to be considered during diagnostic fault simulation or test generation that starts from a fault detection test set. Experimental results for single stuck-at faults in full-scan benchmark circuits demonstrate that only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. The concept of -sets is extended to define z-detections. This concept uses the results of conventional fault simulation to determine additional fault pairs that are guaranteed to be distinguished by a fault detection test set. The concept of z-sets is also extended to define difference-sets (or d-sets) that provide even fewer targets for diagnostic test generation.

We describe a procedure for forming n -detection test sets for n >1 without applying a test generation procedure to target faults. The proposed procedure accepts a one-detection test set. It extracts test cubes for target faults from the one-detection test set, and merges the test cubes to obtain new test vectors. By extracting and merging different test cubes in different iterations of this process, an n -detection test set is obtained. Merging of test cubes does not require test generation or fault simulation. Fault simulation is required for extracting test cubes for target faults. We demonstrate that the resulting test set is as effective in detecting untargeted faults as an n -detection test set generated by a deterministic test generation procedure. We also discuss the application of the proposed procedure starting from a random test set (instead of a one-detection test set).

Summary form only given. Overtesting occurs when a defect that would not be detected under functional operation conditions of a chip is detected due to non-functional conditions created during test application. More generally, overtesting refers to a failure of a chip that occurs during test application when the chip would operate correctly in functional mode. Thus, overtesting results in yield loss that is arguably unnecessary. Overtesting was reported under two-pattern scan-based tests applied for detecting transition faults. However, a wider range of test and defect types may be involved in overtesting. This talk reviews the existing methodologies for addressing overtesting. These methodologies can be broadly classified as based on redundant faults, or based on operation conditions. Methodologies based on redundant faults attempt to prevent faults, which do not affect the functional operation of the circuit, from being detected. Methodologies based on operation conditions attempt to ensure that non-functional operation, which is made possible by scan (or other design-for-testability logic), is avoided. Functional operation conditions in these methodologies are defined to occur when the circuit is in its reachable state space. For a synchronizable circuit, this includes every state that the circuit can visit after synchronization. This talk discusses the fundamental differences between these methodologies, their advantages and limitations. The differences between the methodologies can be seen from the following: 1) A detectable fault may have a test that detects it using a non-reachable state. 2) A redundant fault may become detectable under scan using a reachable state. The talk also raises questions related to overtesting, including the following: 1) Should overtesting (always) be avoided? 2) Should avoidance of overtesting focus only on transition (delay) faults and scan based tests? 3) Even if testing under functional operation conditions can achieve complete fault coverage, is the test set comprehensive enough? 4) Is there a preferred class of methodologies for avoiding overtesting?

We define a functional fault model that does not include explicit fault effect propagation requirements. Test generation for this functional fault model is done considering only a fault free circuit. This simplifies the functional test generation process. We demonstrate through experimental results that functional test sequences generated based on this model are effective in providing very high gate-level stuck-at fault coverage

We show that the functionality of scan chain inputs sometimes exists in a circuit as part of its functional operation, and can be exhibited by applying specific primary input vectors. By relying on such functionality it is possible to hide scan chains as part of a solution that addresses security. It is also possible to reduce the number of external scan chain inputs that need to be added to the circuit as part of the scan implementation, or remove the need to multiplex primary inputs as scan chain inputs. We define inherent scan in functions to capture the functionality of scan chain inputs that exists in a circuit, and show that they can be computed effectively by simulation. We address the case where multiple scan chains are to be used for the circuit

In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method.

Generation of n-detection test sets is typically done for a single fault model. In this work we investigate the generation of n-detection test sets by pairing each fault of a target fault model with n faults of a different fault model. Tests are generated such that they detect both faults of a pair. To facilitate test generation, we ensure that the faults included in a single pair have overlapping requirements for their detection. The advantage of this approach is that it ensures the detection of additional faults that would not be targeted during n-detection test generation for a single fault model. Experimental results with transition faults as the first fault model and four-way bridging faults as the second fault model are presented

Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application time for stuck-at faults. We show that similar advantages exist when considering transition faults. We first show that a test sequence under the transparent-scan approach can imitate the application of broadside tests for transition faults. Test compaction can proceed similar to stuck-at faults by omitting test vectors from the test sequence. A new approach for enhancing test compaction is also described, whereby additional broadside tests are embedded in the transparent-scan sequence without increasing its length or reducing its fault coverage

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach

We present a fault collapsing procedure for transition faults based on fault dominance relations. The effectiveness of the procedure is enhanced by introducing what we call extended transition faults. A standard transition fault involves a single line and a transition. A transition fault from the value to the value a' on a line g is represented as g = a rarr g = a'. An extended transition fault involves two different lines with arbitrary values, and it is represented as g1= a1rarr g2= a'2. We demonstrate the importance of extended transition faults in fault collapsing, and describe two fault collapsing procedures. We consider the effects of fault collapsing on test generation

Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%.

We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal operation conditions. However, fault simulation and test generation for the existing fault models become significantly more complex due to the need to handle faulty signal-transitions that span multiple clock cycles. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur. Fault detection potentially occurs when an unspecified value reaches a primary output. Due to the uncertainty that an unspecified value propagated to a primary output will be different from the fault free value, an inherent requirement in this model is that a fault would be potentially detected multiple times in order to increase the likelihood of detection. Experimental results demonstrate that the model behaves as expected in terms of fault coverage and numbers of detections of target faults. A variation of an n-detection test generation procedure for stuck-at faults is used for generating test sequences under this model.

The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously proposed random partitioning scheme is used to generate additional partitions. Experimental results are reported on the five largest ISCAS'89 benchmark circuits and compared with that for the random partitioning scheme and another earlier work using interval-based partitioning scheme.

When functional tests are used for manufacturing testing, their quality for detecting manufacturing defects needs to be evaluated. Evaluating functional tests using a traditional gate-level fault simulation environment has several disadvantages. To alleviate them, we describe a functional level coverage metric for estimating gate-level fault coverage that has a high degree of correlation to gate-level coverage. We borrow concepts from simulation-based design verification by defining fault detection conditions as coverage objects and monitoring their occurrence, also called their hit counts, during RTL simulation. To reduce the simulation overhead, we abstract gate-level fault detection conditions to the architectural level. The resulting hit counts are converted to an estimated fault coverage using a formula. Experimental results are presented on three datapath modules in a high-performance microprocessor considering two applications: identification of functional tests with high gate-level coverage relative to other tests, and identification of modules or module functions that require additional functional tests

When multiple copies of the same functional unit are available in a design, fault detection can be achieved by comparing the output responses of two copies (or two identical circuits). This obviates the need for storing test responses or for computing signatures of test responses. The paper proposes the testing of identical circuits using a deterministic test sequence by running the circuits at different speeds. This allows the detection of delay faults even if the two copies are affected by similar faults. The proposed method is particularly suitable in applications where functional sequences are used to bin products or to detect delay faults. The case where one of the copies is run at the full circuit speed while the other copy is run at half the full frequency was considered. To allow output response comparison under these conditions, a procedure for designing an input sequence that produces identical output vectors from the two copies every second time unit was described, assuming that both copies are fault free. It was shown that the existence of such input sequences depends on the initial state. Moreover, it is advantageous to start the two copies from different initial states. Experimental results show that very high fault coverage can be achieved by using such sequences

When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage drops leading to larger gate delays which may cause good chips to fail tests. This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests. Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

We present a test generation procedure for transition faults that minimizes the detection of functionally redundant transition faults in scan circuits. The procedure uses broadside testing. We also propose rules for identifying dominance relations between functionally redundant transition faults and functionally detectable transition faults. Dominance relations can provide two types of lower bounds. (1) A lower bound on the number of functionally detectable transition faults that cannot be detected without detecting any functionally redundant transition faults. (2) A lower bound on the number of functionally redundant faults that have to be detected if all the functionally detectable faults are detected. In our experiments with ISCAS-89 and ITC-99 benchmark circuits we achieve both of the lower bounds for almost all the circuits considered.

A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9 % to 44% average reduction in the fault simulation time for these circuits

In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them.

Design-for-testability (DFT) techniques used for synchronous sequential circuits allow redundant faults, which do not affect the functional operation of the circuit, to be detected after DFT insertion. Detecting such faults can cause a chip that operates correctly to be discarded as faulty. A solution proposed earlier was to mask output values where redundant faults are detected in the circuit with DFT, without masking other faults, which should continue to be detected. We investigate a complementary issue of generating test sets that require as little masking as possible. Our goal is to generate a test set that does not detect any redundant faults (or detects as few redundant faults as possible), such that no output values (or as few output values as possible) would have to be masked. We discuss the relationship of this problem to fault dominance. We then describe a specific procedure based on test selection for deriving test sets that detect as few redundant faults as possible while detecting all the other detectable faults.

It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result, it is shown that built-in test-pattern generation for scan circuits can be based on transition probabilities, instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. It is demonstrated that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits. The case where the circuit has a single scan chain, and the case where the circuit has multiple scan chains are considered.

This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode

Scan design allows a circuit to be tested using states that the circuit cannot enter during functional operation. It was observed that nonfunctional operation during testing may cause excessive currents that can cause a good chip to fail the test because of voltage droops caused by the excessive current demand. A good chip may also fail due to the propagation of signal transitions along nonfunctional long paths, especially during at-speed testing. This problem is studied in this paper in the context of tests for transition faults. A method for determining transition faults that are untestable under functional operation-conditions is described. Two procedures for generating transition-fault tests that use only functional operation conditions are also described. The first procedure accepts as input a broadside test set for transition faults. The second procedure accepts as input a test sequence for the nonscan circuit. Although such a test sequence is more complex to generate and simulate, it results in higher numbers of faults detected under functional operation conditions

To address the large numbers of bridging faults in a circuit, several approaches have been proposed for the selection of subsets of bridging faults as targets for test generation. A different approach that can be viewed as a fault collapsing method based on dominance relations between faults is investigated. It is enhanced by the introduction of dummy bridging faults, which are not real faults but whose tests detect large numbers of real faults. This approach is applied to nonfeedback four-way bridging faults. When no approximations are made, the proposed approach selects a subset of faults such that if they are detected all the nonfeedback four-way bridging faults are guaranteed to be detected. When this subset is too large, the proposed approach can also be applied to a subset of bridging faults preselected using other methods, e.g., realistic bridging faults or hard-to-detect bridging faults. In this case, it allows more bridging faults to be preselected. A new selection criterion and issues related to test generation for the selected faults are also investigated

The quality of test sequences for scan circuits under a test-application scheme called transparent scan as n-detection test sequences is studied. A transparent-scan sequence T is obtained from a compact single-detection combinational test set C. It is shown that for the same number of clock cycles required to apply C, the transparent-scan sequence T detects faults more times than C. It is also noted that a transparent-scan sequence based on a combinational test set contains unspecified values. The effects of specifying the unspecified values of the transparent-scan sequence on the quality of the sequence are studied by considering a random specification of these values. A procedure for modifying the scan-select subsequence of a (fully specified) transparent-scan sequence so as to improve its quality as an n-detection test sequence is also described. Finally, the extension of a transparent-scan test sequence into an n-detection test sequence that detects every target fault at least n times is considered. The results show a slower increase in test-application time with n than when combinational test sets are considered

We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented

This paper describes a circuit independent weighted pseudo random BIST pattern generator based on bit-flipping. The circuit dependent data is stored in memories so that different circuits can use the same BIST structure by only changing the data in the memories. New approaches are proposed for compressing and storing the bit-flipping data. Experimental results show that the proposed method reduces the size of the memory considerably while using similar test lengths as a recent method based on bit-fixing.

We study the quality of test sequences under a test application scheme called transparent-scan as n -detection test sequences. We obtain transparent-scan sequences from combinational test sets. We show that for the same number of clock cycles required to apply a compact single-detection combinational test set, a transparent-scan sequence detects faults more times than the combinational test set. We note that a transparent-scan sequence based on a combinational test set contains unspecified values. We consider several procedures for specifying the unspecified values of the transparent-scan sequence, and study their effects. We also study the extension of a transparent-scan test sequence into an n -detection test sequence that detects every target fault at least n times.

Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform both a worst-case analysis and an average-case analysis to check the effect of restricting n on the unmodeled fault coverage of an (arbitrary) n-detection test set. Our analysis is independent of any particular test set or test generation approach. It is based on a specific set of target faults and a specific set of untargeted faults. It shows that, depending on the circuit, very large values of n may be needed to guarantee the detection of all the untargeted faults. We discuss the implications of these results.

We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI(f) with every circuit fault f. The heuristic estimates the number of faults that will be detected by a test generated for f. Fault ordering is done such that a fault with a higher accidental detection index appears earlier in the ordered fault set and targeted earlier during test generation. This order is effective for generating compact test sets, and for obtaining a test set with a steep fault coverage curve. Such a test set has several applications. We present experimental results to demonstrate the effectiveness of the heuristic.

A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns increase the ability to detect unmodeled defects. The proposed method can be used with any test generation procedure to improve the effectiveness of the tests in detecting unmodeled defects. Experimental results on several industrial designs show the effectiveness of defect aware tests. We also propose a measure to estimate the effectiveness of given test sets in detecting unmodeled defects.

A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation and test generation are discussed and experimental results on benchmark circuits and industrial designs are presented. The experimental results presented show that the tests generated using simpler versions of the proposed fault model achieve higher defect coverage than the tests using two currently popular methods to derive high defect coverage tests.

The large numbers of bridging faults in a circuit resulted in several approaches to the selection of a subset of faults as targets for test generation. These approaches do not guarantee that all the bridging faults (or even that all the bridging faults that are likely to occur) will be detected. We investigate a different approach to the selection of target bridging faults. The approach is based on the introduction of dummy bridging faults, which are not physical faults but whose tests detect large numbers of physical faults. We apply this approach to four-way bridging faults. When no approximations are made, the proposed approach selects a subset of faults such that if they are detected, all the four-way bridging faults are guaranteed to be detected. We also investigate approximations and a test generation approach for the selected faults.

We describe a test generation procedure for path-oriented transition faults that takes into account the fact that operating conditions may change during circuit operation. A path-oriented transition fault is detected through the longest sensitizable path that goes through the fault site. The operating conditions we consider are junction temperature and power supply voltage. Since path delays change with operating conditions, the longest path through a fault site may be different under different conditions. We show that test generation using nominal delays is not sufficient for covering the complete range of operating conditions, even if N-detection test generation is used. Therefore, operating conditions need to be addressed explicitly during test generation. However, since temperature and voltage are continuous variables and represent an infinite number of values in the range, test generation must concentrate on a small selected set of operating conditions. We discuss the selection of these conditions and demonstrate that N-detection test generation with multiple operating conditions is effective in covering the range of operation conditions almost completely.

We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.

Testing of delay faults require two pattern tests. Broadside and skewed-load testing are two approaches to test for delay faults in scan designs. The broadside approach is often preferred over the skewed-load approach in designs that also use the system clock for scan operations, since skewed-load requires a fast (at-speed) scan enable signal while broadside testing does not. In this paper, we propose new scan flip-flops to improve delay fault coverage for circuits with scan using broadside tests. The proposed flip-flops do not require a control signal to switch at-speed. This is a distinct advantage as the design effort required for timing closure of such control signals is significant. We also propose a circuit topology based flip-flop selection procedure that offers a scalable method for increasing the transition fault coverage. Experimental results on industrial circuits are included

We describe a procedure for forming n-detection test sets for n > 1 without applying a test generation procedure to target faults. The proposed procedure accepts a one-detection test set. It extracts test cubes for target faults from the one-detection test set. It then merges the cubes in different ways to obtain an n-detection test set. We demonstrate that the resulting test set is as effective as an n-detection test set generated by a deterministic test generation procedure in detecting untargeted faults. Merging of cubes does not require test generation or fault simulation. Fault simulation is required for extracting test cubes for target faults

The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test application time of a test set for a scan circuit is determined by the sum of the number of scan shifts required for applying the test set and the number of primary input vectors in the test set. Compaction procedures that view a full-scan circuit as a combinational circuit reduce the number of test vectors, where a test vector consists of a scan vector and a primary input vector. However, this is not sufficient, and effective procedures must reduce the number of scan operations further than the combinational circuit view allows. Procedures to reduce the test application time by dropping scan operations and applying several primary input vectors between scan operations have been proposed earlier. The compaction procedures proposed in this work reduce the test application time further by using limited scan operations. Under a limited scan operation, the number of shifts is smaller than the length of a scan chain. Scan operations that cannot be dropped are replaced by limited scan operations under the proposed procedures.

Design for testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the circuit outputs. This should be done without masking the detection of other faults of the original circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.

It is shown that fault equivalence and fault dominance relations defined based on the sets of completely specified test vectors that detect each fault may not hold when incompletely specified test vectors are used together with three-value simulation. Experimental results are presented to demonstrate the extent of this phenomenon. Its effects are discussed in general and in the context of a specific application. Possible solutions are also discussed.

Current designs may contain several identical copies of the same circuit (or functional unit). Such circuits can be tested by comparing the output vectors they produce under identical input vectors. This alleviates the need to observe the output response, and facilitates online testing. We show that testing of identical circuits by output comparison can be done effectively even when the input vectors applied to the circuits are not identical. This allows concurrent online testing even when the circuits are not driven from the same source during functional operation. We investigate several issues related to this observation. We investigate the use of both structural and functional analysis to identify situations where nonidentical input vectors can be used for fault detection based on output comparison. We also consider the use of observation points to improve the fault coverage. We present experimental results to support the discussion and the use of nonidentical input vectors for concurrent online testing of identical circuits.

We propose a design-for-testability technique for synchronous sequential circuits called autoscan. Autoscan uses scan chains similar to conventional scan. However, it gives up the external scan inputs and outputs in order to eliminate the test data volume associated with them. Scan operations under autoscan improve the circuit testability by allowing the circuit state to be modified through shifting. Due to the removal of the scan inputs and outputs, synthesis of scan chains under autoscan does not have to satisfy all the constraints imposed on conventional scan chains. We describe a synthesis procedure for autoscan chains, and demonstrate that autoscan allows us to detect almost all the faults that are detectable using conventional scan. We use random sequences in order to show that sequential test generation is not necessary under autoscan. We also describe a test generation procedure, and discuss the effect of autoscan on fault diagnosis.

We study properties of a subset of single stuck-at faults defined based on dominance relations and referred to as maximally dominating faults. These faults were shown to be effective in n-detection test generation and in diagnosis. The properties described here can be useful in additional applications. We suggest two such applications. The first is weighted random pattern generation using three weights, 0, 0.5 and 1. The second application is static test compaction that drops unnecessary tests from a given test set in order to reduce its size.

Test sets for path delay faults in circuits with large numbers of paths are typically generated for faults associated with the longest circuit paths. Such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures. A dynamic test enrichment procedure proposed earlier increases the number of faults associated with the next-to-longest paths that are detected by a test set in order to improve its quality without increasing its size. The earlier procedure is referred to as dynamic since the decision as to which faults associated with next-to-longest paths will be detected is done during test generation. In this work, we describe a postprocessing procedure for test enrichment that accepts a given test set. By processing the tests in reverse order, the proposed procedure increases the number of detected faults associated with next-to-longest paths without increasing the number of tests. We demonstrate the effectiveness of the proposed reverse order test enrichment procedure when applied following, and instead of dynamic test enrichment.

Detecting single stuck-at faults more than once has been shown to be an effective way to achieve high defect coverage. Recently it was observed that the number of tests required to achieve n-detection of single-stuck-at faults using pseudo-random sources may increase as n.logn with increasing values of n. In this paper, we investigate weighted pseudo-random BIST for n-detection of single stuck-at faults. We propose a hardware efficient weighted pseudo-random test pattern generator. Experimental results show that the proposed test pattern generator achieves n-detection of single stuck-at faults with test set sizes growing linearly with n. The hardware overhead grows modestly with n.

This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.

Design-for-testability (DFT) for synchronous sequential circuits allows the generation and application of tests that rely on non-functional operation of the circuit. This can result in unnecessary yield loss due to the detection of faults that do not affect normal circuit operation. Considering single stuck-at faults in full-scan circuits, a test vector consists of a primary input vector U and a state S .We say that the test vector consisting of U and S relies on non-functional operation if S is an unreachable state, i.e., a state that cannot be reached from all the circuit states. Our goal is to obtain test sets with states S that are reachable states. Given a test set C, the solution we explore is based on a simulation-based procedure to identify reachable states that can replace unreachable states in C. No modifications are required to the test generation procedure and no sequential test generation is needed. Our results demonstrate that the proposed procedure is able to produce test sets that detect many of the circuit faults, which are detectable using scan, and practically all the sequentially irredundant faults, by using test vectors with reachable states. The procedure is applicable to any type of scan-based test set, including test sets for delay faults.

We demonstrate that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result we show that built-in test-pattern generation for scan circuits can be based on transition probabilities instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. We demonstrate that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits.

We describe a new approach to fault collapsing that extends fault collapsing based on fault equivalence and fault dominance. The new approach is based on a metric called level of similarity between faults. Informally, a fault f/sub j/ is said to be similar to a fault f/sub i/ with a level of similarity SL/sub i,j/ /spl les/ 1 if a fraction SL/sub i,j/ of the tests for f/sub i/ also detect f/sub j/. If SL/sub i,j/ is high enough, one may exclude f/sub j/ from the set of target faults and rely on the test for f/sub i/ (and tests for other faults) to detect f/sub j/. We describe a procedure for fault collapsing based on the level of similarity, and study its effectiveness experimentally.

We define the concepts of z-sets and z-detections for combinational circuits (or the combinational logic of scan circuits). Based on these concepts we define structural characteristics and characteristics based on fault simulation. We show that these characteristics determine the numbers of fault pairs that are guaranteed to be distinguished by a given fault detection test set. These fault pairs do not need to be considered during diagnostic fault simulation or test generation. We demonstrate that benchmark circuits as well as industrial circuits have these characteristics to a larger extent than may be expected. As a result, only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. In addition, these fault pairs can be identified efficiently.

We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive test compaction compared to other approaches. We demonstrate that, unlike other approaches that provide high levels of test compaction for partial scan circuits, this approach does not increase the number of undetectable faults. We also discuss the monotonicity of the number of undetectable faults with increased levels of scan.

We address the problem of design-for-diagnosability, i.e., improving the accuracy of fault diagnosis or reducing its complexity through the insertion of observation points. To perform design-for-diagnosability efficiently, we use a procedure developed earlier for computing the number of fault pairs, N/sub P/, that are not guaranteed to be distinguished by a given test set. By using the concept of z -detection, N/sub P/ can be computed efficiently without enumerating fault pairs and without performing non-fault dropping fault simulation. We study the possibility of increasing the diagnosability of a circuit by inserting observation points so as to reduce N/sub P/. Our results include the following. (1) We find experimentally the number of observation points that need to be inserted in order to achieve a close-to-minimum value for N/sub P/. (2) We describe an efficient procedure for inserting a given number of observation points so as to reduce N/sub P/. We present experimental results for benchmark circuits to demonstrate the accuracy of using N/sub P/ to guide a design-for-diagnosability process.

A circuit may produce unknown output values during simulation of a test set, e.g., due to an unknown initial state or due to the existence of tristate elements. Unknown output values in the output response of a circuit make it impossible to determine a single unique signature for the fault-free circuit when built-in self-test is used for testing the circuit. We consider the problem of synthesizing a logic block that replaces unknown output values in the output response of a circuit with a known constant. The logic block is constructed from building blocks called comparison units. The synthesis procedure ensures that the built-in self-test scheme will be able to detect all the faults detectable by the test set applied to the circuit while allowing a single unique signature to be computed. Two variations of the synthesis procedure are considered, a two-dimensional version suitable for synchronous sequential circuits without scan and for scan circuits with multiple scan chains and a one-dimensional version suitable for scan circuits with a single scan chain.

When storage requirements or limits on test application time do not allow a complete (compact) test set to be used for a circuit, a partial test set that detects as many faults as possible is required. Motivated by this application, we address the following problem. Given a test sequence T of length L for a synchronous sequential circuit and a length M

N-detection test sets are useful in improving the coverage of unmodeled faults. We introduce a measure of quality that allows us to compare two test sets in terms of their ability to detect unmodeled faults based on the concept of n-detections. Using this measure, we describe a procedure for ordering an n-detection test set for stuck-at faults such that the quality of a test set comprised of the first K tests of the test set is as high as possible. This is useful when only K tests of the test set can be accommodated in the tester memory or to help ensure that unmodeled faults are detected as early as possible during the test application process. We present experimental results demonstrating that the proposed ordering yields test sets with increased coverage of unmodeled faults.

A new class of static compaction procedures is described that generate test sets with reduced test application times for scan circuits. The proposed class of procedures combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with a short primary input sequence included in every test and one that tends to generate small numbers of tests with a long, primary input sequence included in one of the tests. A procedure of the proposed class starts from an initial test set that has a large number of tests and long primary input sequences and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time. Several ways of computing the primary input sequences for the initial test set are considered. The most compact test sets are obtained when a test sequence for the nonscan circuit is available and this sequence is used as part of every test in the initial test set. However, it is shown that high levels of compaction can also be achieved without the overhead of test generation for the nonscan circuit. Specifically, we show that the industry practice of holding a primary input vector constant between scan operations can be accommodated. We estimate the ability of the procedure to achieve optimum test sets by computing a lower bound on the number of tests and demonstrating that the procedure achieves or approaches this lower bound.

We describe a constrained test-generation procedure for synchronous sequential circuits embedded in a large design where scan is used to provide access to the inputs of the individual circuits. The constrained test-generation procedure generates test sequences, where each vector is obtained from the previous one by shifting the scan chain a limited number of positions. Such constrained sequences can be applied through a scan chain with minimal test-application time overhead due to scan. When a shift by a single position is used to obtain each vector from the previous one, the constrained test sequences can allow functional (at-speed) testing of the circuit. Although constrained test sequences cannot achieve complete fault coverage, they reduce the overall test-application time required to achieve complete fault coverage when used together with unconstrained test sequences. We demonstrate these features through experimental results.

For a scan design with multiple scan chains, we say that a scan chain is P-testable if it is possible to achieve complete fault coverage for the circuit (i.e., detect all the detectable target faults) when the scan chain is driven from a source that produces values having a property P. For example, a scan chain is random-testable if it is possible to achieve complete fault coverage for the circuit when the scan chain is driven from a source of pseudorandom values for the complete test application process. In a similar way, we define periodic-testable and combination-testable scan chains. All the sources we consider for P-testable scan chains are simple to implement on-chip. By identifying P-testable scan chains and driving them from the appropriate on-chip sources, we reduce the number of scan chains that need to be driven from an external tester. In this way, we reduce the number of scan inputs that a tester needs to control and the amount of test data that the external tester needs to store and apply to the circuit. Existing test data compression techniques can be used to further reduce the test data volume.

The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a synchronous sequential circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted from the test sequence initially, to start the restoration process. We also propose a specific procedure for the initial omission process. Experimental results for a variety of circuits and test sequences demonstrate that this procedure has a significant effect on the compacted test sequence length. Intuitively, the new procedure postpones the point at which the compaction procedure saturates, thus allowing smaller test lengths to be obtained before saturation is reached. The importance of continuing to explore this problem is related to the fact that static compaction procedures for synchronous sequential circuits are important for scan circuits as well.

We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults for test generation efficiently, when it is impractical to target all the bridging faults (or all the realistic bridging faults). We demonstrate that the faults selected based on the proposed characterization are indeed hard-to-detect by performing the following experiments. 1) We show that the fault coverage of a given test set, with respect to the selected subset of bridging faults, is lower and more sensitive to the test set than the fault coverage obtained with respect to a random subset of bridging faults of the same size, with respect to the complete set of bridging faults, and when possible, with respect to a subset of realistic bridging faults of the same size. 2) We demonstrate that a test set generated for the selected subset of bridging faults detects other bridging faults more effectively than when a test set is derived for a randomly selected subset of bridging faults of the same size. We also describe an efficient procedure for selecting hard-to-detect bridging faults according to the proposed characterization. This procedure avoids enumeration of all the faults in order to select the hard-to-detect ones. This is important for large circuits where even enumeration of all the bridging faults may not be feasible.

Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional test sequence can still be applied at-speed; however, a higher stuck-at fault coverage is achieved.

We consider circuits represented as interconnections of logic blocks. In such circuits, the goal of fault isolation is to identify which one of the blocks is faulty based on a faulty output response produced by the circuit. We study this issue and demonstrate that perfect or close-to-perfect fault isolation is possible with tests that propagate fault effects through pairs of blocks. We relate this phenomenon to the numbers of fault effects observed on the circuit outputs for faults in different blocks. For cases where fault isolation is not perfect, we insert observation points to ensure perfect fault isolation. We also study the number of tests required to achieve perfect fault isolation. The study is performed for single stuck-at faults in combinational (or full scan) blocks.

We propose a new DFT approach for path delay faults in interconnected circuits. The proposed approach places multiplexers on the interface between two circuits in order to create new testable paths through the interconnection. The new testable paths allow us to increase the number of paths tested in each circuit. This approach does not require interconnected circuits to be isolated by test wrappers.

We explore an approach to input test data compression called realignment. Realignment changes a test sequence T consisting of n-bit vectors into a sequence T(m) consisting of m-bit vectors for m /spl ges/ n. It then compresses T(m) instead of T to achieve larger levels of compression for T(m) than for T. By controlling m, realignment provides a range of possible solutions that differ in the data volume reduction and the amount of memory required between the decompressor and the circuit. The memory is required in order to translate m-bit vectors produced by the decompressor into n-bit vectors required by the circuit. We present experimental results to demonstrate this tradeoff for synchronous sequential circuits.

Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.

We consider the relationship between test data compression and the ability to perform comprehensive testing of a circuit under an n-detection test set. The size of an n-detection test set grows approximately linearly with n. Therefore, one may expect a decompresser that can decompress a compressed n-detection test set to be larger than a decompresser required for a compact conventional test set. The results presented in this work demonstrate that it is possible to use a decompresser designed based on a compact one-detection test set in order to apply an n-detection test set. Thus, the design of the decompresser does not have to be changed as n is increased. We describe a procedure that generates an n-detection test set to achieve this result.

Due to their simplicity transition faults are often used as targets for test generation to detect delay defects. However, one concern documented in the literature is that of overtesting. One of the reasons for overtesting is that DFT approaches, such as scan, change sequentially untestable faults into testable faults. One approach to reducing overtesting is to identify sequentially untestable and redundant faults and not target them during test generation for the circuit with scan. Another application of identifying untestable transition faults is its use in logic optimization. We investigate efficient procedures to identify untestable and redundant transition faults in nonscan synchronous sequential circuits. Experimental results for ISCAS-89 benchmark circuits are presented.

We propose a method to find don't care (X) values in a test sequence for a sequential circuit. Given a fully specified test sequence generated by a sequential ATPG, the proposed method produces a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence.