We present MARCO (Multi-Agent Reinforcement learning with Conformal Optimization), a hardware-aware neural architecture search (NAS) framework for resource-constrained edge devices. MARCO combines multi-agent reinforcement learning (MARL) with Conformal Prediction (CP) to efficiently explore architectures under strict memory and latency budgets. Unlike once-for-all (OFA) supernets that require expensive pretraining, MARCO separates the NAS task into a Hardware Configuration Agent and a Quantization Agent, coordinated via a centralized-critic, decentralized-execution (CTDE) paradigm. A calibrated CP surrogate model offers distribution-free guarantees to filter low-reward candidates before costly training or simulation, significantly accelerating the search. Experiments on MNIST, CIFAR-10, and CIFAR-100 show MARCO achieves $3-4 \times$ faster search than OFA while maintaining accuracy within 0.3% and reducing latency. Validation on the MAX78000 confirms simulator fidelity with less than 5% error.

We present FAIR-SIGHT, a post-hoc framework that enforces statistical fairness in computer vision models without retraining or access to internal parameters. The method computes a fairness-aware non-conformity score combining prediction error and demographic disparity and uses conformal prediction to calibrate a threshold that guarantees a user-specified violation rate under finite-sample, distribution-free conditions. Inputs exceeding this threshold are automatically repaired through lightweight adjustments (such as logit shifts for classification or confidence scaling for detection) to reduce group disparities while preserving accuracy. Experiments on CelebA, UTKFace, GeoDE, and COCO show over 30% reductions in DPD/EOD and detection gaps with negligible utility loss and only ∼0.5ms/img overhead, establishing FAIR-SIGHT as a practical, scalable solution for bias mitigation in black-box vision systems.

This article presents Flex-NTT, a flexible (configurable) and area-efficient number theoretic transform (NTT) architecture featuring novel unified memory access patterns. The proposed design offers compile-time configurability (CTC) to support various parallel butterfly units (BUs) and run-time configurability (RTC) to accommodate diverse NTT operation sizes without recompilation. A single hardware instance is reconfigurable for NTT, inverse NTT (INTT), and point-wise multiplication, improving hardware utilization. The proposed coefficient and twiddle-factor memory access schemes achieve the theoretical minimum memory sizes, eliminate intermediate buffers, and enable natural-order outputs without additional reordering. FPGA evaluations demonstrate that Flex-NTT achieves up to$4.25 \times $BRAM savings and$2.82 \times $performance improvements over prior NTT/INTT designs. When applied to polynomial multiplication, it delivers up to$2.35 \times $performance and$2.93 \times $BRAM utilization improvements under the same metric.

We present a heuristic algorithm designed to solve Quadratic Unconstrained Binary Optimization (QUBO) problems efficiently. The algorithm, referred to as IC-D2S, leverages a hybrid approach using Ising and classical machines to address very large problem sizes. Considering the practical limitation on the size of the Ising machine (IM), our algorithm partitions the QUBO problem into a collection of QUBO subproblems (called subQUBOs) and utilizes the IM to solve each subQUBO. Our proposed heuristic algorithm uses a set of control parameters to generate the subQUBOs and explore the search space. Also, it utilizes an annealer based on cosine waveform and applies a mutation operator at each step of the search to diversify the solution space and facilitate the process of finding the global minimum of the problem. We have evaluated the effectiveness of our IC-D2S algorithm on three large-sized problem sets and compared its efficiency in finding the (near-)optimal solution with three QUBO solvers. One of the solvers is a software-based algorithm (D2TS), while the other one (D-Wave) employs a similar approach to ours, utilizing both classical and Ising machines. The results demonstrate that for large-sized problems (≥ 5000) the proposed algorithm identifies superior solutions. Additionally, for smaller-sized problems (= 2500), IC-D2S efficiently finds the optimal solution in a significantly faster manner.

This paper introduces a novel Dynamic Co-Optimization Compiler (DCOC), which employs an adaptive Multi-Agent Reinforcement Learning (MARL) framework to enhance the efficiency of mapping machine learning (ML) models, particularly Deep Neural Networks (DNNs), onto diverse hardware platforms. DCOC incorporates three specialized actor-critic agents within MARL, each dedicated to different optimization facets: one for hardware and two for software. This cooperative strategy results in an integrated hardware/software co-optimization approach, improving the precision and speed of DNN deployments. By focusing on high-confidence configurations, DCOC effectively reduces the search space, achieving remarkable performance over existing methods. Our results demonstrate that DCOC enhances throughput by up to 37.95% while reducing optimization time by up to 42.2% across various DNN models, outperforming current state-of-the-art frameworks.

The inherent quadratic complexity of the attention mechanism in transformer models has driven the research community to explore alternative architectures with sub-quadratic complexity, such as state-space models. Mamba has established itself as a leading model within this emerging paradigm, achieving state-of-the-art results in various language modeling benchmarks. However, despite its impressive performance, Mamba's effectiveness is limited by its pre-training context length, resulting in a pronounced degradation when the model is tasked with handling longer contexts. Our investigation reveals that Mamba's inability to generalize effectively to long contexts is primarily due to the out-of-distribution (OOD) discretization steps. To address this critical limitation, we introduce _**MambaExtend**_, a novel framework designed to significantly enhance the context extension capabilities of Mamba. Specifically, MambaExtend leverages a _**training-free**_ approach to calibrate _only_ the scaling factors of discretization modules for different layers. We demonstrate both gradient-based and gradient-free zeroth-order optimization to learn the optimal scaling factors for each Mamba layer, requiring orders of magnitude fewer updates as opposed to the parameter fine-tuning-based alternatives. Using this approach, we achieve a training-free context extension of up to 32x, expanding the context from 2k to 64k tokens with minimal increases in perplexity. In contrast to existing fine-tuning methods, MambaExtend selectively calibrates the scaling factors, requiring up to $\mathbf{5.42 * 10^6} \times$ fewer parameter updates and incurring up to $\mathbf{3.87} \times$ lower peak memory usage, while delivering comparable or superior long-context performance across multiple tasks. Codes and checkpoints are available here$^1$.

We propose FACTER, a fairness-aware framework for LLM-based recommendation systems that integrates conformal prediction with dynamic prompt engineering. By introducing an adaptive semantic variance threshold and a violation-triggered mechanism, FACTER automatically tightens fairness constraints whenever biased patterns emerge. We further develop an adversarial prompt generator that leverages historical violations to reduce repeated demographic biases without retraining the LLM. Empirical results on MovieLens and Amazon show that FACTER substantially reduces fairness violations (up to 95.5%) while maintaining strong recommendation accuracy, revealing semantic variance as a potent proxy of bias.

Ensuring fairness is essential for ethical decision-making in various domains. Informally, a neural network is considered fair if and only if it treats similar individuals similarly in a given task. We introduce FaVeR (Fairness Verification and Repair), a framework for efficiently verifying and repairing pre-trained neural networks with respect to individual fairness properties. FaVeR ensures fairness via iterative search of high-sensitivity neurons and backward adjustment of their weights, guided by counterexamples generated from fairness verification using satisfiability modulo convex programming. By addressing fairness at the neuron level, FaVeR minimizes the impact of neural network repair on the overall performance. Experimental evaluations on common fairness datasets show that FaVeR achieves a 100% fairness repair rate across all models, with accuracy reduction of less than 2.27%. Moreover, its significantly lower average runtime makes it suitable for practical applications.

Multi-channel keyword spotting (KWS) has become crucial for voice-based applications in edge environments. However, its substantial computational and energy requirements pose significant challenges. We introduce ASAP-FE (Agile Sparsity-Aware Parallelized-Feature Extractor), a hardware-oriented front-end designed to address these challenges. Our framework incorporates three key innovations: (1) Half-overlapped Infinite Impulse Response (IIR) Framing: This reduces redundant data by approximately 25% while maintaining essential phoneme transition cues. (2) Sparsity-aware Data Reduction: We exploit frame-level sparsity to achieve an additional 50% data reduction by combining frame skipping with stride-based filtering. (3) Dynamic Parallel Processing: We introduce a parameterizable filter cluster and a priority-based scheduling algorithm that allows parallel execution of IIR filtering tasks, reducing latency and optimizing energy efficiency. ASAP-FE is implemented with various filter cluster sizes on edge processors, with functionality verified on FPGA prototypes and designs synthesized at 45 nm. Experimental results using TC-ResNet8, DS-CNN, and KWT-1 demonstrate that ASAP-FE reduces the average workload by 62.73% while supporting real-time processing for up to 32 channels. Compared to a conventional fully overlapped baseline, ASAP-FE achieves less than a 1% accuracy drop (e.g., 96.22% vs. 97.13% for DS-CNN), which is well within acceptable limits for edge AI. By adjusting the number of filter modules, our design optimizes the trade-off between performance and energy, with 15 parallel filters providing optimal performance for up to 25 channels. Overall, ASAP-FE offers a practical and efficient solution for multi-channel KWS on energy-constrained edge devices.

This paper introduces a dynamic precision analog multiplier architecture for analog mixed-signal machine learning (ML) accelerators. The proposed architecture, built on the C2C ladder structure, enables runtime adjustment of the multiplier bit weights from the least significant bit (LSB) to the most significant bit (MSB), allowing for flexible implementation of mixed-precision ML models. By adjusting the bit position weights of learnable neural network weights, the representable numbers can be tailored to the required precision for a given node or filter in the ML model. To determine the optimal bit weights for our proposed multiplier, we propose a non-uniform quantization-aware training algorithm that trains the multiplier bit weights and fine-tunes the pre-trained ML model weights to utilize the suggested multiplication engine efficiently. We implemented the proposed multiplier in 12nm technology and evaluated its performance on low-bit-width BERT and GPT2 models for eight natural language processing (NLP) tasks. The results show that the 32×32 crossbar of the proposed 4-bit multiplier achieves 100 TOPS/W energy efficiency. Moreover, our proposed analog multiplier achieves scores comparable to those of FP32 models when using 4-bit models, demonstrating its efficacy.

We recently proposed Radar-PIM, a Processing-in-Memory (PIM) solution for real-time, low-power UWB radar respiration detection. To meet stringent energy constraints for UAV-based rescue operations, we further developed Radar-PIM-Lite, significantly reducing resource usage and power consumption. We implemented a processor based on our proposed technology and validated its superior ultra-low-power performance and reliable real-time detection capability through FPGA prototyping and application demonstrations. We will showcase this FPGA-based Radar-PIM-Lite prototype through a live demonstration at ISLPED 2025.

This paper introduces an innovative framework for training low-precision deep neural networks (DNNs) using the 8-bit Posit (Posit8) number system. The framework utilizes a ‘fake’ quantization strategy where all computations are performed in high precision (e.g., 32-bit floating-point, FP32) while weights, activations, loss, and gradients are quantized to Posit8. This approach significantly reduces off-chip memory requirements during training, lowering energy consumption by decreasing the data bandwidth between computing engines and off-chip memory. Our training framework dynamically adjusts the exponent size within the Posit number system to effectively balance dynamic range and precision needs. Additionally, we incorporate a tensor-wise scaling technique to mitigate precision loss associated with the reduced representation bandwidth of Posit8. We also propose a specialized rounding mechanism for the quantization process from FP32 to Posit8, aimed at minimizing accuracy degradation in low-precision training. To evaluate the effectiveness of our approach, we implemented it in PyTorch and conducted experiments using several benchmark neural networks on the CIFAR-10, CIFAR-100, and Tiny ImageNet datasets. In addition, we compared its performance against an FP8 training framework. Experiment results indicate an accuracy drop of approximately 0.86% compared to high-precision training, with energy consumption reduced by 1.7x. At the same time, our framework achieves an average improvement of up to ~1.1% (and as much as 2.28%) in accuracy over models trained with FP8 quantization with ~2% more energy consumption.

Large language models (LLMs), despite their impressive performance across a wide range of tasks, often struggle to balance two competing objectives in open-ended text generation: fostering diversity and creativity while preserving logical coherence. Existing truncated sampling techniques, including temperature scaling, top-*p* (nucleus) sampling, and min-*p* sampling, aim to manage this trade-off. However, they exhibit limitations, particularly in the effective incorporation of the confidence of the model into the corresponding sampling strategy. For example, min-*p* sampling relies on a single top token as a heuristic for confidence, eventually underutilizing the information of the probability distribution. To effectively incorporate the model confidence, this paper presents **_top-H_ decoding**. We first establish the theoretical foundation of the interplay between creativity and coherence in truncated sampling by formulating an **entropy-constrained minimum divergence** problem. We then prove this minimization problem to be equivalent to an **entropy-constrained mass maximization (ECMM)** problem, which is NP-hard. Finally, we present top-H decoding, a computationally efficient greedy algorithm to solve the ECMM problem. Extensive empirical evaluations demonstrate that top-H outperforms the state-of-the-art (SoTA) alternative of min-*p* sampling by up to **25.63%** on creative writing benchmarks, while maintaining robustness on question-answering datasets such as GPQA, GSM8K, and MT-Bench. Additionally, an *LLM-as-judge* evaluation confirms that top-H indeed produces coherent outputs even at higher temperatures, where creativity is especially critical. In summary, top-H advances SoTA in open-ended text generation and can be *easily integrated* into creative writing applications. The code is available at [https://github.com/ErfanBaghaei/Top-H-Decoding](https://github.com/ErfanBaghaei/Top-H-Decoding).

The adoption of ultrawideband (UWB) radar technology in IoT and healthcare applications for respiration detection is rapidly expanding, opening up a wide array of potential use cases. Despite its burgeoning utility, the integration of UWB radar-based respiration detection in IoT end node devices faces significant challenges due to the memory-intensive nature of these tasks, which strain the capabilities of IoT processors. This article introduces a streamlined UWB radar-based respiration detection application designed for operation on IoT processors, emphasizing that when executed on conventional IoT processors, the limited processing power still results in significant data loss, underscoring the need for enhanced processing solutions. To address these challenges, we propose the adoption of processing-in-memory (PIM) technology and unveil the novel Radar-PIM architecture. This architecture is meticulously engineered to boost the efficiency of respiration detection while ensuring seamless integration with existing embedded processor frameworks. This article extensively describes the Radar-PIM architecture and its operational mechanisms. We further demonstrate its superior performance by implementing and empirically testing a Radar-PIM processor prototype. Next, we present an optimization strategy tailored for designing energy-efficient Radar-PIM processors, specifically adapted for diverse UWB radar-based respiration detection applications. For instance, a Radar-PIM processor prototype, optimized for a particular application, achieved approximately 42% energy savings compared to its unoptimized counterpart and delivered performance nearly three times greater than that of a multicore processor with equivalent power consumption. This demonstrates the transformative potential of our proposed solution in enhancing the capabilities of radar-based respiration detection systems for IoT end nodes.

Given the ever-growing complexity and computational requirements of deep learning models, it has become imperative to efficiently optimize neural network architectures. This paper presents an automated, search-based method for opti-mizing the bit-width and layer-width of individual neural network layers, achieving substantial reductions in the size and processing requirements of these models. Our unique approach employs Hessian-based search space pruning to discard unpromising so-lutions, greatly reducing the search space. We further refine the optimization process by introducing a novel, adaptive algorithm that combines k-means clustering with tree-structured Parzen estimation. This allows us to dynamically adjust a figure of merit used in tree-structured Parzen estimation, i.e., the desirability of a particular bit-width and layer-width configuration, thereby expediting the identification of optimal configurations. Through extensive experiments on benchmark datasets, we validate the efficacy of our method. More precisely, our method outperforms existing techniques by achieving an average 20 % reduction in model size without sacrificing any output accuracy. It also boasts a$12\times$acceleration in search time compared to the most advanced search-based approaches.

Positioned as a highly promising post-CMOS computing technology, superconductor electronics (SCE) offer the potential for unparalleled performance and energy efficiency gains compared to end-of-roadmap CMOS circuits. However, achieving very large-scale integration poses numerous challenges. These challenges span from the modeling and analysis of superconducting devices and logic gates to the intricate design of complex SCE circuits and systems. Addressing power and clock distribution issues, minimizing adverse effects of flux trappings, and mitigating stray electromagnetic fields in sensitive SCE circuitry are key challenges that need attention. Verification and testing of SCE circuits also remain open problems. Moreover, scaling the minimum feature sizes of SCE circuits, currently set at 150nm, presents critical scaling and physical design challenges that must be overcome. This review aims to delve into these issues, providing detailed insights while exploring existing or potential solutions to overcome them.

This paper introduces NeuroBlend, a novel neural network architecture featuring a unique building block known as the Blend module. This module incorporates binary and fixed-point convolutions in its main and skip paths, respectively. There is a judicious deployment of batch normalizations on both main and skip paths inside the Blend module and in between consecutive Blend modules. Additionally, we present a compiler and hardware architecture designed to map NeuroBlend models onto FPGA devices, aiming to minimize inference latency while maintaining high accuracy. Our NeuroBlend-20 (NeuroBlend-18) model, derived from ResNet-20 (ResNet-18) trained on CIFAR-10 (CIFAR-100), achieves 88.0% (73.73%) classification accuracy, outperforming state-of-the-art binary neural networks by 0.8% (1.33%), with an inference time of 0.38ms per image, 1.4x faster than previous FPGA implementation for BNNs. Similarly, our BlendMixer model for CIFAR-10 attains 90.6% accuracy(1.59% less than full precision MLPMixer), with a 3.5x reduction in model size compared to full precision MLPMixer. Furthermore, leveraging DSP blocks for 48-bit bitwise logic operations enables low-power FPGA implementation, yielding a 2.5x reduction in power consumption.

In this paper, we present a mixed-signal implementation of iterative Montgomery multiplication algorithm (called X-IMM) for using in large arithmetic word size (LAWS) computations. LAWS is mainly utilized in security applications such as lattice-based cryptography, where the width of the input operands may be equal to or larger than 1,024 bits. The proposed architecture is based on the iterative implementation of the Montgomery multiplication (MM) algorithm, where some critical parts of the multiplication are computed in the analog domain by mapping them on the memristor crossbar. Using a memristor crossbar reduces the area usage and latency of the modular multiplication unit compared to its fully digital implementation. The devised mixed-signal MM implementation is scalable by cascading the smaller X-IMMs to support dynamically adjustable larger operand sizes at runtime. The effectiveness of the proposed MM structure is assessed in the 45nm technology and the comparative studies show that the proposed 1,024-bit Radix-4 (Radix-16) Montgomery multiplication architecture provides about 13% (22%) higher GOPS/mm2 compared to the state-of-the-art digital ASIC implementations of the iterative MM. Also, owing to analog computing, the proposed structure reduces energy consumption considerably as well.

The deployment of Vision Transformers (ViTs) on hardware platforms, specially Field-Programmable Gate Arrays (FPGAs), presents many challenges, which are mainly due to the substantial computational and power requirements of their non-linear functions, notably layer normalization, softmax, and Gaussian Error Linear Unit (GELU). These critical functions pose significant obstacles to efficient hardware implementation due to their complex mathematical operations and the inherent resource count and architectural limitations of FPGAs. PEANO-ViT offers a novel approach to streamlining the implementation of the layer normalization layer by introducing a division-free technique that simultaneously approximates the division and square root function. Additionally, PEANO-ViT provides a multi-scale division strategy to eliminate division operations in the softmax layer, aided by a Padé-based approximation for the exponential function. Finally, PEANO-ViT introduces a piece-wise linear approximation for the GELU function, carefully designed to bypass the computationally intensive operations associated with GELU. In our comprehensive evaluations, PEANO-ViT exhibits minimal accuracy degradation ≤ 0.5% for DeiT-B) while significantly enhancing power efficiency, achieving improvements of 1.91X, 1.39X, and 8.01X for layer normalization, softmax, and GELU, respectively. This improvement is achieved through substantial reductions in DSP, LUT, and register counts for these non-linear operations. Consequently, PEANO-ViT enables efficient deployment of Vision Transformers on resource- and power-constrained FPGA platforms.

Graphics Processing Units (GPUs) are the accelerator of choice in a variety of application domains, because they can accelerate massively parallel workloads and can be easily programmed using general-purpose programming frameworks such as CUDA and OpenCL. Each Streaming Multiprocessor (SM) contains an L1 data cache (L1D) to exploit the locality in data accesses. L1D misses are costly for GPUs for two reasons. First, L1D misses consume a lot of energy as they need to access the L2 cache (L2) via an on-chip network and the off-chip DRAM in case of L2 misses. Second, L1D misses impose performance overhead if the GPU does not have enough active warps to hide the long memory access latency. We observe that threads running on different SMs share 55% of the data they read from the memory. Unfortunately, as the L1Ds are in the non-coherent memory domain, each SM independently fetches data from the L2 or the off-chip memory into its L1D, even though the data may be currently available in the L1D of another SM. Our goal is to service L1D read misses via other SMs, as much as possible, to cut down costly accesses to the L2 or the off-chip DRAM. To this end, we propose a new data-sharing mechanism, called Cross-Core Data Sharing (CCDS) . CCDS employs a predictor to estimate whether the required cache block exists in another SM. If the block is predicted to exist in another SM’s L1D, then CCDS fetches the data from the L1D that contain the block. Our experiments on a suite of 26 workloads show that CCDS improves average energy and performance by 1.30× and 1.20×, respectively, compared to the baseline GPU. Compared to the state-of-the-art data-sharing mechanism, CCDS improves average energy and performance by 1.37× and 1.11×, respectively.

In this article, we present the HiCoP architecture, a high-performance, conflict-free memory access, modular polynomial multiplication design that accelerates the number-theoretic transform (NTT), inverse NTT (INTT), and modular polynomial multiplications. To optimize hardware costs, the HiCoP architecture utilizes a high-radix reconfigurable butterfly unit (RBU) that can be dynamically configured to perform NTT, INTT, and point-wise multiplications, alongside an area-efficient Montgomery modular multiplier (MMM) tailored for NTT-friendly modulus. Moreover, by integrating pre-processing, post-processing, and Montgomery domain transformations into NTT and INTT operations, we effectively minimize the cycle count for modular polynomial multiplication. Additionally, we propose a novel conflict-free memory access algorithm that simplifies the control logic and eliminates the need for ping-pong memory in the HiCoP architecture. Experimental results of modular polynomial multiplications demonstrate significant performance gains for the HiCoP architecture implemented on the Xilinx Virtex-7 field-programmable gate array (FPGA) platform, with up to$8.75\times $,$4.15\times $,$10.57\times $, and$8.50\times $improvements in throughput-to-hardware-cost ratio for LUT count, FF count, BRAM count, and DSP count, respectively.

The increasing interest in RISC-V from both academia and industry has motivated the development and release of a number of free, open-source cores based on the RISC-V instruction set architecture. Specifically, the use of lightweight RISC-V cores in processors tailored for IoT endnode devices is on the rise. As the range and complexity of these applications grow, there is an increasing demand for multicore processors that can handle floating-point operations. This poses a significant challenge because most lightweight RISC-V cores are integer cores lacking a floating-point unit (FPU). This limitation makes it difficult to design processors optimized for applications that require floating-point operations concurrently with integer operations. While it is inefficient to have a dedicated FPU per core in a multicore processor (because it would give rise to unnecessary power consumption), it is crucial to find a solution that balances performance and energy efficiency. To address this challenge, we propose to utilize an external lightweight FPU that can be added to any RISC-V integer core, along with a low-power multicore architecture that shares the said FPU. We have applied this concept to design a RISC-V processor that integrates these technologies, implemented it on an FPGA device, and completed the fabrication of a System-on-Chip for functional verification. Our experiments, which involved testing various applications on different processor prototypes, demonstrated significant energy savings of up to 79.6% in a quad-core processor prototype, highlighting the potential energy efficiency of our proposed technology.

This article presents a mixed-computation neural network processing approach for edge applications that incorporates low-precision (low-width) Posit and low-precision fixed point (FixP) number systems. This mixed-computation approach uses 4-bit Posit (Posit4), which has higher precision around 0, for representing weights with high sensitivity, while it uses 4-bit FixP (FixP4) for representing other weights. A heuristic for analyzing the importance and the quantization error of the weights is presented to assign the proper number system to different weights. In addition, a gradient approximation for Posit representation is introduced to improve the quality of weight updates in the backpropagation process. Due to the high energy consumption of the fully Posit-based computations, neural network operations are carried out in FixP or Posit/FixP. An efficient hardware implementation of an MAC operation with a first Posit operand and FixP for a second operand and accumulator is presented. The efficacy of the proposed low-precision mixed-computation approach is extensively assessed on vision and language models. The results show that on average, the accuracy of the mixed-computation is about 1.5% higher than that of FixP with a cost of 0.19% energy overhead.

Modular multiplication (MM) is a fundamental operation in many cryptographic and arithmetic applications. In this article, we present an improved Barrett modular multiplication (BMM) algorithm and its hardware-efficient implementation. The proposed algorithm leverages parallel computation of quotient and intermediate results, enhancing overall efficiency. To further optimize the algorithm, two optimizations are introduced, replacing expensive multiplications and additions with more efficient compression and encoding operations at each iteration. We first introduce a novel data model that enables the use of a 2-bit adder to handle potential overflow in signed addition. Moreover, by employing a 3-bit addition on intermediate results, we eliminate the need for complete round operations while ensuring the desired result range. The experimental results demonstrate significant improvements in terms of area and computation time compared to existing classic BMM and Montgomery modular multiplication (MMM) designs. Our improved BMM outperforms these designs, particularly in high-radix scenarios. This work provides a valuable contribution to the field of MM, offering a hardware-efficient solution for achieving improved performance in cryptographic and arithmetic systems.

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget.

As applications running on lightweight RISC-V processors become increasingly diverse and complex, the need for multicore processors supporting floating-point units (FPUs) is riseing, making processor designs using existing open-source RISC-V cores challenging. With the exception of a very few, most open lightweight RISC-V cores are integer cores without FPUs, which greatly reduces the design exploration space, making it impossible to design a processor optimized for each application. For example, most of these applications mainly perform integer operations, but occasionally perform floating-point operations. For them, a multicore processor with FPU per core is overkill and wastes power, which is a critical problem for processors where low-power design is paramount. To address the problem, we propose an external lightweight FPU that can be attached to any RISC-V integer core and a low-power multicore architecture using the designed FPU. For verification, we designed a RISC-V processor that implements all the proposed technologies, prototyped it on an FPGA device, and finally fabricated it as a System-on-Chip. Through experiments, it was confirmed that the proposed technology can cut energy consumption energy by up to 23%.

Ring-Learning-with-Errors (RLWE) has emerged as the foundation of many important techniques for improving security and privacy, including homomorphic encryption and post-quantum cryptography. While promising, these techniques have received limited use due to their extreme overheads of running on general-purpose machines. In this paper, we present a novel vector Instruction Set Architecture (ISA) and microarchitecture for accelerating the ring-based computations of RLWE. The ISA, named B512, is developed to meet the needs of ring processing workloads while balancing high-performance and general-purpose programming support. Having an ISA rather than fixed hardware facilitates continued software improvement post-fabrication and the ability to support the evolving workloads. We then propose the ring processing unit (RPU), a high-performance, modular implementation of B512. The RPU has native large word modular arithmetic support, capabilities for very wide parallel processing, and a large capacity highbandwidth scratchpad to meet the needs of ring processing. We address the challenges of programming the RPU using a newly developed SPIRAL backend. A configurable simulator is built to characterize design tradeoffs and quantify performance. The best performing design was implemented in RTL and used to validate simulator performance. In addition to our characterization, we show that a RPU using 20.5mm2of GF12nm can provide a speedup of 1485× over a CPU running a 64k, 128-bit NTT, a core RLWE workload.

Existing models that achieve state-of-the-art (SOTA) performance on both clean and adversarially-perturbed images rely on convolution operations conditioned with feature-wise linear modulation (FiLM) layers. These layers require additional parameters and are hyperparameter sensitive. They significantly increase training time, memory cost, and potential latency which can be costly for resource-limited or real-time applications. In this paper, we present a fast learnable once-for-all adversarial training (FLOAT) algorithm, which instead of the existing FiLM-based conditioning, presents a unique weight conditioned learning that requires no additional layer, thereby incurring no significant increase in parameter count, training time, or network latency compared to standard adversarial training. In particular, we add configurable scaled noise to the weight tensors that enables a trade-off between clean and adversarial performance. Extensive experiments show that FLOAT can yield SOTA performance improving both clean and perturbed image classification by up to ~6% and ~10%, respectively. Moreover, real hardware measurement shows that FLOAT can reduce the training time by up to 1.43× with fewer model parameters of up to 1.47× on iso-hyperparameter settings compared to the FiLM-based alternatives. Additionally, to further improve memory effi ciency we introduce FLOAT sparse (FLOATS), a form of non-iterative model pruning and provide detailed empirical analysis in yielding a three-way accuracy-robustness-complexity trade-off for these new class of pruned conditionally trained models.

This paper presents a highly efficient iterative Montgomery modular multiplication algorithm, wherein the computations of quotient and intermediate result in each iteration are done in parallel. This parallelism breaks the data dependency and thus reduces the computation latency. Moreover, this paper replaces required multiplications and additions in each iteration with compressions and encoding, thereby achieving a computation latency of order$d+6$where$d=\left\lceil N/m \right\rceil +2$is the number of iterations,$N$denotes the bitwidth of modulus$M$, and$m$is the number of bits of the multiplier that are processed in each iteration of the algorithm. Hardware realization of the proposed Montgomery modular multiplication on a Xilinx Virtex-7 FPGA device shows$> 41\%$computation latency saving and$>31\%$area saving when$N=1,024$and$m=8$, compared with the best of previous state-of-art references. These savings amount to more than 63% reduction in terms of the area-latency product metric.

This paper investigates a runtime accuracy reconfigurable implementation of an energy efficient deep learning accelerator. It is based on voltage overscaling (VOS) technique which provides dynamic adjustment of approximation level as well as improving lifetime/reliability of the accelerator. The technique is applied to both computing and memory units where based on the minimum required accuracy, the applied voltage is adjusted during the runtime. The implementation of the network is performed using NVDLA which is an open-source CNN (Convolutional Neural Network) accelerator. The approximation is applied to both the accelerator MAC array employed for the required network computations and to the accelerator SRAM memory utilized for storing the inputs (images), weights, and activation data. To control the accuracy degradation of the approximate accelerator (called X-NVDLA), the reduced voltage is applied only to LSB bits of the MAC array and SRAM unit. To assess the efficacy of the proposed energy efficient accelerator, the energy-accuracy characteristics of X-NVDLA when running LeNet-5 and ResNet-50 networks with 8-bit (integer) precision are investigated. In addition, the characteristic of bias temperature instability (BTI), as one of the lifetime deteriorating phenomena is determined. The study includes energy improvement versus accuracy degradation as a function of overscaled voltages and number of approximate the least significant bits using a 15nm FinFET technology.

In this work, to limit the number of required attention inference hops in memory-augmented neural networks, we propose an online adaptive approach called [Formula: see text]-memory-augmented neural network (MANN). By exploiting a small neural network classifier, an adequate number of attention inference hops for the input query are determined. The technique results in the elimination of a large number of unnecessary computations in extracting the correct answer. In addition, to further lower computations in [Formula: see text]-MANN, we suggest pruning weights of the final fully connected (FC) layers. To this end, two pruning approaches, one with negligible accuracy loss and the other with controllable loss on the final accuracy, are developed. The efficacy of the technique is assessed by applying it to two different MANN structures and two question answering (QA) datasets. The analytical assessment reveals, for the two benchmarks, on average, 50% fewer computations compared to the corresponding baseline MANNs at the cost of less than 1% accuracy loss. In addition, when used along with the previously published zero-skipping technique, a computation count reduction of approximately 70% is achieved. Finally, when the proposed approach (without zero skipping) is implemented on the CPU and GPU platforms, on average, a runtime reduction of 43% is achieved.

In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

In this paper, a mixed-signal coarse-grained reconfigurable architecture (CGRA) for accelerating inference in deep neural networks (DNNs) is presented. It is based on performing dot-product computations using analog computing to achieve a considerable speed improvement. Other computations are performed digitally. In the proposed structure (called MX-CGRA), analog tiles consisting of memristor crossbars are employed. To reduce the overhead of converting the data between analog and digital domains, we utilize a proper interface between the analog and digital tiles. In addition, the structure benefits from an efficient memory hierarchy where the data is moved as close as possible to the computing fabric. Moreover, to fully utilize the tiles, we define a set of micro instructions to configure the analog and digital domains. Corresponding context words used in the CGRA are determined by these instructions (generated by a companion compiler tool). The efficacy of the MX-CGRA is assessed by modeling the execution of state-of-the-art DNN architectures on this structure. The architectures are used to classify images of the ImageNet dataset. Simulation results show that, compared to the previous mixed-signal DNN accelerators, on average, a higher throughput of 2.35 × is achieved.

Recent efforts for improving the performance of neural network (NN) accelerators that meet today’s application requirements have given rise to a new trend of logic-based NN inference relying on fixed function combinational logic. Mapping such large Boolean functions with many input variables and product terms to digital signal processors (DSPs) on Field-programmable gate arrays (FPGAs) needs a novel framework considering the structure and reconfigurability of DSP blocks during this process. The proposed methodology in this article maps the fixed function combinational logic blocks to a set of Boolean functions where Boolean operations corresponding to each function are mapped to DSP devices rather than look-up tables on the FPGAs to take advantage of the high performance, low latency, and parallelism of DSP blocks. This article also presents an innovative design and optimization methodology for compilation and mapping of NNs, utilizing fixed function combinational logic to DSPs on FPGAs employing high-level synthesis flow. Our experimental evaluations across several datasets and selected NNs demonstrate the comparable performance of our framework in terms of the inference latency and output accuracy compared to prior art FPGA-based NN accelerators employing DSPs.

This article presents an error estimation technique for a data-flow graph (DFG) representation of an approximate computing (AC) circuit. The technique, which may be used during the high-level design of digital circuits, estimates error metrics for the outputs of the approximate circuit. The proposed technique receives as an input, output error characterizations of arithmetic modules in a high-level library. The error modeling of a library module is accomplished by dividing the input (operand) ranges into intervals and then characterizing the output error for different combinations of these input intervals. Subsequently, the error for each combination is stored in a lookup table (LUT). The module error models are integrated into a design space exploration (DSE) framework to evaluate different combinations of exact and approximate realizations of various operations in the DFG. The DSE, which performs error calculation and propagation from inputs to outputs of the target DFG, may be used to explore trade-offs between the output error and other design metrics of the approximate circuit, e.g., energy efficiency. The efficacy of the proposed method is assessed for three image processing benchmarks. Results for these benchmarks demonstrate that the framework can efficiently generate the Pareto frontier (PF) in the trade-off space of accuracy versus energy efficiency for the targeted benchmarks. Compared to a purely simulation-based exploration, the proposed technique provides an average of$92\times $speed improvement.

Large DNNs with mixed-precision quantization can achieve ultra-high compression while retaining high classification performance. However, because of the challenges in finding an accurate metric that can guide the optimization process, these methods either sacrifice significant performance compared to the 32-bit floating-point (FP-32) baseline or rely on a compute-expensive, iterative training policy that requires the availability of a pre-trained baseline. To address this issue, this paper presents BMPQ, a training method that uses bit gradients to analyze layer sensitivities and yield mixed-precision quantized models. BMPQ requires a single training iteration but does not need a pre-trained baseline. It uses an integer linear program (ILP) to dynamically adjust the precision of layers during training, subject to a fixed hardware budget. To evaluate the efficacy of BMPQ, we conduct extensive experiments with VGG16 and ResNet18 on CIFAR-10, CIFAR-100, and Tiny-ImageNet datasets. Compared to the baseline FP-32 models, BMPQ can yield models that have 15.4x fewer parameter bits with negligible drop in accuracy. Compared to the SOTA “during training”, mixed-precision training scheme, our models are 2.1 x, 2.2x, and 2.9x smaller, on CIFAR-10, CIFAR-100, and Tiny-ImageNet, respectively, with an improved accuracy of up to 14.54%.

Computation-in-memory (CIM) is one of the most appealing computing paradigms, especially for implementing artificial neural networks. Non-volatile memories like ReRAMs, PCMs, etc., have proven to be promising candidates for the realization of CIM processors. However, these devices and their driving circuits are subject to non-idealities. This paper presents a comprehensive platform, named SysCIM, for simulating memristor-based CIM systems. SySCIM considers the impact of the non-idealities of the CIM components, including memristor device, memristor crossbar (interconnects), analog-to-digital converter, and transimpedance amplifier, on the vector-matrix multiplication performed by the CIM unit. The CIM modules are described in SystemC and SystemC-AMS to reach a higher simulation speed while maintaining high simulation accuracy. Experiments under different crossbar sizes show SySCIM performs simulations up to 117 x faster than HSPICE with less than 4% accuracy loss. The modular design of SySCIM provides researchers with an easy design-space exploration tool to investigate the effects of various non-idealities.

The control of cryogenic qubits in today’s super-conducting quantum computer prototypes presents significant scalability challenges due to the massive costs of generating/routing the analog control signals that need to be sent from a classical controller at room temperature to the quantum chip inside the dilution refrigerator. Thus, researchers in industry and academia have focused on designing in-fridge classical controllers in order to mitigate these challenges. Due to the maturity of CMOS logic, many industrial efforts (Microsoft, Intel) have focused on Cryo-CMOS as a near-term solution to design in-fridge classical controllers. Meanwhile, Supercon-ducting Single Flux Quantum (SFQ) is an alternative, less mature classical logic family proposed for large-scale in-fridge controllers. SFQ logic has the potential to maximize scalability thanks to its ultra-high speed and very low power consumption. However, architecture design for SFQ logic poses challenges due to its unconventional pulse-driven nature and lack of dense memory and logic. Thus, research at the architecture level is essential to guide architects to design SFQ-based classical controllers for large-scale quantum machines.In this paper, we present DigiQ, the first system-level design of a Noisy Intermediate Scale Quantum (NISQ)-friendly SFQ-based classical controller. We perform a design space exploration of SFQ-based controllers and co-design the quantum gate decompositions and SFQ-based implementation of those decompositions to find an optimal SFQ-friendly design point that trades area and power for latency and control while ensuring good quantum algorithmic performance. Our co-design results in a single instruction, multiple data (SIMD) controller architecture, which has high scalability, but imposes new challenges on the calibration of control pulses. We present software-level solutions to address these challenges, which if unaddressed would degrade quantum circuit fidelity given the imperfections of qubit hardware.To validate and characterize DigiQ, we first implement it using hardware description languages and synthesize it using state-of-the-art/validated SFQ synthesis tools. Our synthesis results show that DigiQ can operate within the tight power and area budget of dilution refrigerators at >42,000-qubit scales. Second, we confirm the effectiveness of DigiQ in running quantum algorithms by modeling the execution time and fidelity of a variety of NISQ applications. We hope that the promising results of this paper motivate experimentalists to further explore SFQ-based quantum controllers to realize large-scale quantum machines with maximized scalability.

Single Flux Quantum (SFQ) superconducting technology provides significant power and performance benefits in the era of diminishing CMOS scaling. Recent advances in design tools and fabrication facilities have brought SFQ based computing to the forefront. One challenge faced by SFQ technology is to have a compact and robust on-chip memory, which can be used for implementing register files and cache memory. While dense memories are being investigated through the development of three-terminal devices such as Nanocryotrons, in this work, we build on a novel memory cell built using traditional Josephson junctions (JJs). In particular, we design a high capacity register file, called HiPerRF, that builds on a High Capacity Destructive ReadOut (HC-DRO) cell in SFQ technology. HC-DRO design can store up to three fluxon pulses, thereby providing the equivalent of 2-bit storage in a single cell. However, these cells provide only destructive readout capability, namely each value can be read only once. However, CPU register file contents are read multiple times in any program, and hence a destructive readout complicates register file design. HiPerRF provides the non-destructive property using a loopback write mechanism, thereby preserving the higher density of HC-DRO cells without compromising the multi-read demands of a register file. HiPerRF reduces the JJ count of the register file design, after accounting for all the peripheral access circuitry costs, by 56.1% and reduces the static power by 46.2%. Furthermore, HiPerRF reduces the JJ count by 16.3% even when considering an entire in-order RISC-V CPU core.

This paper introduces the sparse periodic systolic (SPS) dataflow, which advances the state-of-the-art hardware accelerator for supporting lightweight neural networks. Specifically, the SPS dataflow enables a novel hardware design approach unlocked by an emergent pruning scheme, periodic pattern-based sparsity (PPS). By exploiting the regularity of PPS, our sparsity-aware compiler optimally reorders the weights and uses a simple indexing unit in hardware to create matches between the weights and activations. Through the compiler-hardware codesign, SPS dataflow enjoys higher degrees of parallelism while being free of the high indexing overhead and without model accuracy loss. Evaluated on popular benchmarks such as VGG and ResNet, the SPS dataflow and accompanying neural network compiler outperform prior work in convolutional neural network (CNN) accelerator designs targeting FPGA devices. Against other sparsity-supporting weight storage formats, SPS results in 4.49 × energy efficiency gain while lowering storage requirements by 3.67 × for total weight storage (non-pruned weights plus indexing) and 22,044 × for indexing memory.

The proposed herein is a scalable high-radix (i.e.,$2^m$2m) Montgomery Modular (MM) Multiplication circuit replacing the integer multiplications in each iteration of the Montgomery MM algorithm (related to the product of$m$mbits of the multiplier and the multiplicand) with carry-save compressions and completely eliminating costly multiplications. Furthermore, the proposed Montgomery MM decomposes the multiplicand itself using a radix of$2^w$2wwith$w\geq 2m$w≥2m, thereby achieving a scalable design, which can deliver an issue latency of one cycle and a cycle (count) latency of$O(N^2/(wmp))$O(N2/(wmp))where$p$pdenotes the number of available processing elements, each of which is designed to complete the above iteration by computing in part the product of$w$wbits of the multiplicand and$m$mbits of the multiplier. The area complexity of the proposed Montgomery MM is$O(wmp)$O(wmp), and thus, the Area-Latency-Product complexity is$O(N^{2})$O(N2).

In this article, we present a main memory system for improving the lifetime and security of phase-change main memories. Storing encrypted data increases the bit-flip rates in memory cells, which adversely affects the lifetime of the phase-change memory cells. Thus, to improve the lifetime and security, the proposed system reduces the bit-flip rates by introducing two techniques. The first technique is a memory-side encryption which provides security against DIMM stealing attacks. To prevent unauthorized accesses, in this technique, the encrypted data are not saved in the main memory. As the second technique, we suggest an adaptive partial encryption approach, which makes use of behavior tracking of the application in the CPU side to minimize the latency overhead of the first technique. Additionally, it prevents the loss of data against application-based attacks. This technique uses a recurrent neural network (RNN) to do sequence classification and detect malicious applications. In addition, an auxiliary method, called periodic encryption (PE), which overcomes the security loss in some applications induced by the low accuracy of the employed neural network, is presented. The efficacy of the proposed method is evaluated using gem5 simulator and some benchmarks. Compared to DEUCE and Crypto-Comp methods, the results for the lifetime evaluation show an average bit-flip rate reduction of 11%. In addition, the security improvements against the DIMM stealing and application-based attacks are about 100% and 92.5%, respectively.

We present a dynamic network rewiring (DNR) method to generate pruned deep neural network (DNN) models that both are robust against adversarially generated images and maintain high accuracy on clean images. In particular, the disclosed DNR training method is based on a unified constrained optimization formulation using a novel hybrid loss function that merges sparse learning with robust adversarial training. This training strategy dynamically adjusts inter-layer connectivity based on per-layer normalized momentum computed from the hybrid loss function. To further improve the robustness of the pruned models, we propose DNR++, an extension of the DNR method where we introduce the idea of sparse parametric Gaussian noise tensor that is added to the weight tensors to yield robust regularization. In contrast to existing robust pruning frameworks that require multiple training iterations, the proposed DNR and DNR++ achieve an overall target pruning ratio with only a single training iteration and can be tuned to support both irregular and structured channel pruning. To demonstrate the efficacy of the proposed method under the no-increased-training-time “free” adversarial training scenario, we finally present FDNR++, a simple yet effective training modification that can yield robust yet compressed models requiring training time comparable to that of an unpruned non-adversarial training. To evaluate the merits of our disclosed training methods, experiments were performed with two widely accepted models, namely VGG16 and ResNet18, on CIFAR-10 and CIFAR-100 as well as with VGG16 on Tiny-ImageNet. Compared to the baseline uncompressed models, our methods provide over 20× compression on all the datasets without any significant drop of either clean or adversarial classification performance. Moreover, extensive experiments show that our methods consistently find compressed models with better clean and adversarial image classification performance than what is achievable through state-of-the-art alternatives. We provide insightful observations to help make various model, parameter density, and prune-type selection choices and have open-sourced our saved models and test codes to ensure reproducibility of our results.

In this work, we present an energy-efficient posit processing element (PE) for utilization in array-based deep neural network (DNN) accelerators along with an approximation method for further reducing the energy consumption of the unit. The posit arithmetic used in the proposed PE provides high precision for the considered data widths even when approximation is used for operations. Using some modification/simplification approaches and proposing a speculative posit adder (SPA) unit, we reduce the complexity of the employed posit multiply–accumulator (MAC) in the proposed PE. The effectiveness of the proposed PE is studied using a 45-nm CMOS technology. The results reveal$3.5\times $and 92% improvements in the delay and energy consumption, respectively, compared to those of the state-of-the-art posit PE. To assess the efficacy of the proposed PE, we have modeled an 8-bit DNN accelerator and employed it for the implementation of some DNN architectures. The results indicate that the proposed PE and its approximate one provide, on average, 19.3% and 29.6% lower energy consumptions compared to that of the latest prior work when providing 10.6% and 5.8% higher accuracies, respectively.

This paper presents a dynamic network rewiring (DNR) method to generate pruned deep neural network (DNN) models that are robust against adversarial attacks yet maintain high accuracy on clean images. In particular, the disclosed DNR method is based on a unified constrained optimization formulation using a hybrid loss function that merges ultra-high model compression with robust adversarial training. This training strategy dynamically adjusts inter-layer connectivity based on per-layer normalized momentum computed from the hybrid loss function. In contrast to existing robust pruning frameworks that require multiple training iterations, the proposed learning strategy achieves an overall target pruning ratio with only a single training iteration and can be tuned to support both irregular and structured channel pruning. To evaluate the merits of DNR, experiments were performed with two widely accepted models, namely VGG16 and ResNet-18, on CIFAR-10, CIFAR-100 as well as with VGG16 on Tiny-ImageNet. Compared to the baseline uncompressed models, DNR provides over 20x compression on all the datasets with no significant drop in either clean or adversarial classification accuracy. Moreover, our experiments show that DNR consistently finds compressed models with better clean and adversarial image classification performance than what is achievable through state-of-the-art alternatives. Our models and test codes are available at https://github.com/ksouvik52/DNR_ASP_DAC2021.

Synthesizing general nonlinear sequential circuits in superconducting Single Flux Quantum (SFQ) technology is a challenging task involving the proper leveling of cyclic digraphs, handling nested feedback loops, and ensuring the full path balancing property throughout the synthesis process. This paper presents a precise definition of the level of a node in a cyclic digraph and a polynomial time algorithm for the corresponding level assignment and full path balancing in sequential SFQ circuits, including SFQ Finite State Machines (FSMs). A case study is conducted on a 3-bit counter, as an FSM, which has a power consumption of $44. 7 \mu W$ and $1. 4 \mu W$ using rapid SFQ and energy-efficient rapid RSFQ cells, respectively, with the local clock frequency of 55GHz (throughput of 11GHz) which is significantly higher than the typical CMOS clock frequencies. More results on larger SFQ circuits are also presented.

Two-level logic minimization has found applications in new problems such as efficient realization of deep neural network inference. Important characteristics of these new applications are that they tend to produce very large Boolean functions (in terms of the supporting variables and/or initial sum of product representation) and have don't-care-sets that are much larger in size than the on-set and off-set sizes. Applying conventional single-threaded logic minimization heuristics to these problems becomes unwieldy. This work introduces ESPRESSO-GPU, a parallel version of ESPRESSO-II, which takes advantage of the computing capabilities of general-purpose graphics processors to achieve a huge speedup compared to existing serial implementations. Simulation results show that ESPRESSO-GPU achieves an average speedup of 97x compared to ESPRESSO-II.

While there is a large body of research on efficient processing of deep neural networks (DNNs) [1]-[31], ultra-low-latency realization of these models for applications with stringent, sub-microsecond latency requirements continues to be an unresolved, challenging problem. Field-programmable gate array (FPGA)-based DNN accelerators are gaining traction as a serious contender to replace graphics processing unit/central processing unit-based platforms considering their performance, flexibility, and energy efficiency. NullaNet (2018) [32], LUTNet (2019) [33], and LogicNets (2020) [34] are among accelerators specifically designed to benefit from FPGAs' capabilities.

Single flux quantum (SFQ) circuits as an example of superconducting electronics (SCE) have the potential to replace CMOS circuits as they possess a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude higher speed. Despite its benefits, the SCE community lacks a reliable open source formal verification solution. This paper proposes a verification framework called qMC, a model checker for SFQ circuits using formal techniques. qMC offers an automated process that constructs a SystemVerilog testbench consisting of formal assertions to verify the SFQ-specific properties of the circuits and produce system correctness results and counterexamples using model checking (MC). Instead of creating an MC tool from scratch, we have built qMC based on well established open source back-end verification engines for MC of CMOS circuits, including Yosys-SMTBMC and EBMC. qMC allows for properties to be given in SystemVerilog formal assertions, time-limited SystemVerilog assertions, or linear temporal logic (LTL). qMC provides an improvement in terms of verification time and coverage when compared to state-of-the-art semi-formal based SFQ verification frameworks. For instance, verification time for a 4-bit array multiplier is sped up by 19.5x.

Existing two-level logic minimization methods suffer from scalability problems, i.e. they cannot handle the optimization of Boolean functions with more than about 50k or so product terms. However, applications have arisen that produce Boolean functions with hundreds of thousands to millions of minterms. To ameliorate the aforesaid scalability problem, this work presents a suite of heuristics that enables exact or approximate two-level logic minimization of such large Boolean functions by employing a divide and conquer technique. All proposed heuristics first deploy a decision tree to iteratively partition the original specification of a given Boolean function. Next, they apply one of different leaf optimization techniques (e.g., those based on support vector machines or error budgets) to each leaf node of the tree, and, finally, they merge the locally optimized leaves at the root of the tree to perform one round of the global optimization. We show that our support vector machine-based heuristic compresses Boolean functions with 300,000 minterms by a factor of about 100 (i.e. 3,000 cubes in the optimized function), and achieves 98% accuracy. Similarly, our error-budget-driven heuristic compresses a Boolean function with about 3,000,000 minterms by a factor of 1,273, and achieves 95 % accuracy while it only takes 67 seconds to complete the whole optimization process. This is a significant improvement compared to well-known two-level logic minimization tools such as ESPRESSO-II and BOOM, which fail to optimize the same Boolean functions even after running for a few days.

Low-latency deep spiking neural networks (SNNs) have become a promising alternative to conventional artificial neural networks (ANNs) because of their potential for increased energy efficiency on event-driven neuromorphic hardware. Neural networks, including SNNs, however, are subject to various adversarial attacks and must be trained to remain resilient against such attacks for many applications. Nevertheless, due to prohibitively high training costs associated with SNNs, an analysis and optimization of deep SNNs under various adversarial attacks have been largely overlooked. In this paper, we first present a detailed analysis of the inherent robustness of low-latency SNNs against popular gradient-based attacks, namely fast gradient sign method (FGSM) and projected gradient descent (PGD). Motivated by this analysis, to harness the model’s robustness against these attacks we present an SNN training algorithm that uses crafted input noise and incurs no additional training time. To evaluate the merits of our algorithm, we conducted extensive experiments with variants of VGG and ResNet on both CIFAR-10 and CIFAR-100 dataset. Compared to standard trained direct-input SNNs, our trained models yield improved classification accuracy of up to 13.7% and 10.1% on FGSM and PGD attack generated images, respectively, with negligible loss in clean image accuracy. Our models also outperform inherently-robust SNNs trained on rate-coded inputs with improved or similar classification performance on attack-generated images while having up to 25× and ∼4.6× lower latency and computation energy, respectively. For reproducibility, we have open-sourced the code at github.com/ksouvik52/hiresnn2021.

This paper presents a fast architecture for Barrett modular multiplication. By replacing the integer multiplications in each iteration with carry-save compressions and using Booth coding plus operation rescheduling to increase parallelism, we eliminate costly multiplications while concurrently avoiding large-bitwidth additions. Our detailed error analysis proves that intermediate results are always less than twice the modulus. Experimental results show that the removal of multiplication eliminates the need for any DSPs. Even not accounting for this key benefit, compared to the best of prior art results, the proposed design results in 46.8% latency reduction with a similar area.

Knowledge distillation (KD) has recently been identified as a method that can unintentionally leak private information regarding the details of a teacher model to an unauthorized student. Recent research in developing undistillable nasty teachers that can protect model confidentiality has gained significant attention. However, the level of protection these nasty models offer has been largely untested. In this paper, we show that transferring knowledge to a shallow sub-section of a student can largely reduce a teacher’s influence. By exploring the depth of the shallow subsection, we then present a distillation technique that enables a skeptical student model to learn even from a nasty teacher. To evaluate the efficacy of our skeptical students, we conducted experiments with several models with KD on both training data-available and data-free scenarios for various datasets. While distilling from nasty teachers, compared to the normal student models, skeptical students consistently provide superior classification performance of up to ∼59.5%. Moreover, similar to normal students, skeptical students maintain high classification accuracy when distilled from a normal teacher, showing their efficacy irrespective of the teacher being nasty or not. We believe the ability of skeptical students to largely diminish the KD-immunity of potentially nasty teachers will motivate the research community to create more robust mechanisms for model confidentiality. We have open-sourced the code at https://github.com/ksouvik52/Skeptical2021

The increasing demand for on-chip edge intelligence has motivated the exploration of algorithmic techniques and specialized hardware to reduce the computation energy of current machine learning models. In particular, deep spiking neural networks (SNNs) have gained interest because their event-driven hardware implementations can consume very low energy. However, minimizing average spiking activity and thus energy consumption while preserving accuracy in deep SNNs remains a significant challenge and opportunity. This paper proposes a novel two-step SNN compression technique to reduce their spiking activity while maintaining accuracy that involves compressing specifically-designed artificial neural networks (ANNs) that are then converted into the target SNNs. Our approach uses an ultra-high ANN compression technique that is guided by the attention-maps of an uncompressed meta-model. We then evaluate the firing threshold of each ANN layer and start with the trained ANN weights to perform a sparse-learning-based supervised SNN training to minimize the number of time steps required while retaining compression. To evaluate the merits of the proposed approach, we performed experiments with variants of VGG and ResNet, on both CIFAR-10 and CIFAR-100, and VGG16 on Tiny-ImageNet. SNN models generated through the proposed technique yield state-of-the-art compression ratios of up to 33.4× with no significant drop in accuracy compared to baseline unpruned counterparts. As opposed to the existing SNN pruning methods we achieve up to 8.3× better compression with no drop in accuracy. Moreover, compressed SNN models generated by our methods can have up to 12.2× better compute energy-efficiency compared to ANNs that have a similar number of parameters.

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 °C and 0.44 V at 80 °C while continuing to operate at a target 50-MHz clock frequency.

Maintaining safe chip and device skin temperatures in small form-factor mobile devices (such as smartphones and tablets) while continuing to add new functionalities and provide higher performance has emerged as a key challenge. This article presentsTherminator 2, an early stage, fast, full-device thermal analyzer, which generates accurate transient- and steady-state temperature maps of an entire smartphone starting from the application processor and other key device components, extending to the skin of the device itself. Therminator 2 uses advanced numerical optimization techniques to perform steady-state simulations 1.6 times faster than the prior art technique and is capable of performing transient-state simulations in real time and 1.25 times faster than the prior art method. The thermal analysis is sensitive to detailed device specifications (including its material composition and 3-D layout) as well as different use cases (each case specifying the set of active device components and their activity levels.) Therminator 2 considers all major components within the device, builds a corresponding compact thermal model for each component and the whole device, and produces their transient- and steady-state temperature maps. Temperature results obtained by using Therminator 2 have been validated against a commercial computational fluid dynamics (CFDs)-based tool, i.e., Autodesk Simulation CFD, and thermocouple measurements on a Qualcomm Mobile Developer Platform and Google Nexus 5. A case study on a Samsung Galaxy S4 using Therminator 2 is provided to relate the device performance to the skin temperature and investigate the thermal path design.

In this paper, a method for offline training of inverter-based memristive neural networks (IM-NNs), called ERIM, is presented. In this method, the output voltage of the inverter is modeled very accurately by considering the loading effect of the memristive crossbar. To properly choose the size of each inverter, its output load and the required slope of its voltage transfer characteristic (VTC) for an acceptable level of resiliency to the circuit element non-idealities are taken into account. The efficacy of ERIM is investigated by comparing its accuracy to those of two recently proposed offline training methods for IM-NNs (RIM and PHAX). The study is performed using IRIS, BCW, MNIST, and Fashion MNIST datasets. Simulation results show that 72% (56%) reduction in average energy consumption of the trained networks is achieved compared to RIM (PHAX) thanks to proper sizing of the inverters. In addition, due to the higher accuracy of the NN mathematical model, ERIM results in significant improvements in the match between the results of high-level modeling and HSPICE simulations while exhibiting lower sensitivity to circuit element variations.

In this paper, the sensitivity of the neural network (NN) outputs to device parameter uncertainties (non-idealities) in inverter-based memristor (IM) crossbar neuromorphic circuits is mathematically modeled and verified using exhaustive circuit and system-level simulations. The NN sensitivity is obtained by modeling the sensitivity of theIMneuron output to the non-idealities of its circuit elements. The analysis reveals a higher sensitivity of the output voltage of theIMneuron to the non-idealities of the inverters compared to the conductance variation of the memristors. Among the inverter non-idealities, horizontal shift of the inverters voltage transfer characteristic (VTC) shows the highest impact on the output voltage of the neuron. To reduce the accuracy loss due to the variations, a training approach which includes a sensitivity term in the cost function of the training phase, is suggested. The achievable improvements through the said NN training approach are evaluated. In the evaluation, the California Housing, MNIST, and Fashion MNIST datasets are employed. The results show up to 50% reduction in the NN output variations in the presence of circuit elements’ non-idealities.

Deep learning models are being deployed in many mobile intelligent applications. End-side services, such as intelligent personal assistants, autonomous cars, and smart home services often employ either simple local models on the mobile or complex remote models on the cloud. However, recent studies have shown that partitioning the DNN computations between the mobile and cloud can increase the latency and energy efficiencies. In this paper, we propose an efficient, adaptive, and practical engine, JointDNN, for collaborative computation between a mobile device and cloud for DNNs in both inference and training phase. JointDNN not only provides an energy and performance efficient method of querying DNNs for the mobile side but also benefits the cloud server by reducing the amount of its workload and communications compared to the cloud-only approach. Given the DNN architecture, we investigate the efficiency of processing some layers on the mobile device and some layers on the cloud server. We provide optimization formulations at layer granularity for forward- and backward-propagations in DNNs, which can adapt to mobile battery limitations and cloud server load constraints and quality of service. JointDNN achieves up to 18 and 32 times reductions on the latency and mobile energy consumption of querying DNNs compared to the status-quo approaches, respectively.

Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.

In this article, we present a low-energy inference method for convolutional neural networks in image classification applications. The lower energy consumption is achieved by using a highly pruned (lower-energy) network if the resulting network can provide a correct output. More specifically, the proposed inference method makes use of two pruned neural networks (NNs), namely mildly and aggressively pruned networks, which are both designed offline. In the system, a third NN makes use of the input data for the online selection of the appropriate pruned network. The third network, for its feature extraction, employs the same convolutional layers as those of the aggressively pruned NN, thereby reducing the overhead of the online management. There is some accuracy loss induced by the proposed method where, for a given level of accuracy, the energy gain of the proposed method is considerably larger than the case of employing any one pruning level. The proposed method is independent of both the pruning method and the network architecture. The efficacy of the proposed inference method is assessed on Eyeriss hardware accelerator platform for some of the state-of-the-art NN architectures. Our studies show that this method may provide, on average, 70% energy reduction compared to the original NN at the cost of about 3% accuracy loss on the CIFAR-10 dataset.

In this article, we present an approach for adjusting the approximation levels of the cache memories in the memory hierarchy of an approximate processing system. The technique, which is called online management of cache approximation level (OPTIMA), adjusts the approximation levels of the caches under a predefined accuracy constraint. OPTIMA may also be employed for multicore processors, which comprise cores with private and shared caches running applications with different error constraints. To reduce the energy consumption, OPTIMA determines the proper approximation level of each cache memory using heuristic algorithms in two main steps. In the first step, the approximate levels are adjusted to maximize the power efficiency by dropping the application accuracy to a level that still meets a desirable minimum output quality. In the second step, output accuracy variations due to input pattern changes are compensated by fine tuning. We suggest two algorithms (with different adjustment speeds of approximate levels) for the first step and another algorithm for the second step. To assess the efficacy of OPTIMA, we integrate it in the gem5 simulator and simulate some multiprocessor configurations by running eight approximate benchmarks. The results show that the proposed approach provides up to 44% power consumption reduction in the memory hierarchy.

This paper presents a novel timing driven global placement approach utilizing the alternating direction method of multipliers (ADMM) targeting superconductive electronic circuits. The proposed algorithm models the placement problem as an optimization problem with constraints on the maximum wirelength delay of timing-critical paths and employs the ADMM algorithm to decompose the problem into two sub-problems, one minimizing the total wirelength of the circuit and the other minimizing the delay of timing-critical paths of the circuit. Through an iterative process, a placement solution is generated that simultaneously minimizes the total wirelength and satisfies the setup time constraints. Compared to an state-of-the-art academic global placement tool, the proposed method (called TDP-ADMM) improves the worst and total negative slack for seven single flux quantum benchmark circuits by an average of 26% and 44%, respectively, with an average overhead of 1.98% in terms of total wirelength.

There have been many recent attempts to extend the successes of convolutional neural networks (CNNs) from 2-dimensional (2D) image classification to 3-dimensional (3D) video recognition by exploring 3D CNNs. Considering the emerging growth of mobile or Internet of Things (IoT) market, it is essential to investigate the deployment of 3D CNNs on edge devices. Previous works have implemented standard 3D CNNs (C3D) on hardware platforms, however, they have not exploited model compression for acceleration of inference. This work proposes a hardware-aware pruning approach that can fully adapt to the loop tiling technique of FPGA design and is applied onto a novel 3D network called R(2+1)D. Leveraging the powerful ADMM, the proposed pruning method achieves simultaneous high accuracy and significant acceleration of computation on FPGA. With layer-wise pruning rates up to 10× and negligible accuracy loss, the pruned model is implemented on a Xilinx ZCU102 FPGA board, where the pruned model achieves 2.6× speedup compared with the unpruned version, and 2.3× speedup and 2.3× power efficiency improvement compared with state-of-the-art FPGA implementation of C3D.

Superconducting single flux quantum (SFQ) technology using Josephson junctions (JJs) is an excellent choice for the computing fabrics of the future. Current recycling is a necessary technique for the implementation of large SFQ circuits with energy-efficiency, where circuit partitions with similar bias current requirements are biased serially. Though this technique has been verified for small scale circuits, it has not been implemented for large circuits as there is no trivial way to partition the circuit into circuit blocks with separate ground planes. The major constraints for partitioning are (1) equal bias current and (2) equal area for all the partitions; (3) minimize the connections between adjacent ground planes with high-cost for non-adjacent planes. For the first time, all these constraints are formulated into a cost function and it is minimized with the gradient descent method. The algorithm takes a circuit netlist and the intended number of partitions as inputs and gives the output as groups of cells belonging to separate ground planes. It minimizes the connections among different ground planes and gives a solution on which the current recycling technique can be implemented. The parameters of cost function have been initialized randomly along with minimizing the dimensions to find the solution quickly. On average, 30% of connections are between non-adjacent ground planes for the given benchmark circuits.

This paper presents a low-cost, timing uncertainty-aware synchronous clock tree topology generation algorithm for single flux quantum (SFQ) logic circuits. The proposed method considers the criticality of the data paths in terms of timing slacks as well as the total wirelength of the clock tree and generates a (height-) balanced binary clock tree using a bottom-up approach and an integer linear programming (ILP) formulation. The statistical timing analysis results for ten benchmark circuits show that the proposed method improves the total wirelength and the total negative hold slack by 4.2% and 64.6%, respectively, on average, compared with a wirelength-driven state-of-the-art balanced topology generation approach.

Machine learning applied to architecture design presents a promising opportunity with broad applications. Recent deep reinforcement learning (DRL) techniques, in particular, enable efficient exploration in vast design spaces where conventional design strategies may be inadequate. This paper proposes a novel deep reinforcement framework, taking routerless networks-on-chip (NoC) as an evaluation case study. The new framework successfully resolves problems with prior design approaches, which are either unreliable due to random searches or inflexible due to severe design space restrictions. The framework learns (near-)optimal loop placement for routerless NoCs with various design constraints. A deep neural network is developed using parallel threads that efficiently explore the immense routerless NoC design space with a Monte Carlo search tree. Experimental results show that, compared with conventional mesh, the proposed deep reinforcement learning (DRL) routerless design achieves a 3.25x increase in throughput, 1.6x reduction in packet latency, and 5x reduction in power. Compared with the state-of-the-art routerless NoC, DRL achieves a 1.47x increase in throughput, 1.18x reduction in packet latency, 1.14x reduction in average hop count, and 6.3% lower power consumption.

Retiming, which is a circuit transformation whereby registers are relocated to optimize performance, area, or energy consumption, has reached a high level of maturity in CMOS designs. However, the recent emergence and rapid rise of non-CMOS technologies are introducing new and important variants of the standard retiming problems. This paper presents a path-balancing retiming transformation, taking superconductive designs as an evaluation case study, where the retiming solution must achieve full path balancing of the circuit while simultaneously minimizing the energy consumption of inserted registers with performance constraints. This optimization problem, which is called a constrained register energy minimization (CREM) problem, is precisely formulated and polynomially solved. Next, the CREM problem formulation is extended to retime the circuit under a dual clocking architecture requiring partially (bounded depth difference) path balanced (PPB) characteristics only. It is shown that the PPB-CREM problem is NP-complete. We thus propose a polynomial-time approximation algorithm with a bounded error to solve this retiming variant. Compared to prior work, our approach reduces 38% of register count and 50% of register energy consumption of 14 benchmark circuits on average. Moreover, the competitive ratio of the register energy consumption between our approximate solution and the optimal solution is on average only 1.08.

Machine learning models differ in terms of accuracy, computational/memory complexity, training time, and adaptability among other characteristics. For example, neural networks (NNs) are well-known for their high accuracy due to the quality of their automatic feature extraction while brain-inspired hyperdimensional (HD) learning models are famous for their quick training, computational efficiency, and adaptability. This work presents a hybrid, synergic machine learning model that excels at all the said characteristics and is suitable for incremental, on-line learning on a chip. The proposed model comprises an NN and a classifier. The NN acts as a feature extractor and is specifically trained to work well with the classifier that employs the HD computing framework. This work also presents a parameterized hardware implementation of the said feature extraction and classification components while introducing a compiler that maps any arbitrary NN and/or classifier to the aforementioned hardware. The proposed hybrid machine learning model has the same level of accuracy (i.e. ±1%) as NNs while achieving at least 10% improvement in accuracy compared to HD learning models. Additionally, the end-to-end hardware realization of the hybrid model improves power efficiency by 1.60x compared to state-of-the-art, high-performance HD learning implementations while improving latency by 2.13x. These results have profound implications for the application of such synergic models in challenging cognitive tasks.

We propose a learning algorithm to design a lightweight neural multiplexer that given the input and computational resource requirements, calls the model that will consume the minimum compute resources for a successful inference. Mobile devices can use the proposed algorithm to offload the hard inputs to the cloud while inferring the easy ones locally. Besides, in the large scale cloud-based intelligent applications, instead of replicating the most-accurate model, a range of small and large models can be multiplexed from depending on the input's complexity which will save the cloud's computational resources. The input complexity or hardness is determined by the number of models that can predict the correct label. For example, if no model can predict the label correctly, then the input is considered as the hardest. The proposed algorithm allows the mobile device to detect the inputs that can be processed locally and the ones that require a larger model and should be sent a cloud server. Therefore, the mobile user benefits from not only the local processing but also from an accurate model hosted on a cloud server. Our experimental results show that the proposed algorithm improves mobile's model accuracy by 8.52 % which is because of those inputs that are properly selected and offloaded to the cloud server. In addition, it saves the cloud providers' compute resources by a factor of 2.85 × as small models are chosen for easier inputs.

Quantum computers are growing in size, and design decisions are being made now that attempt to squeeze more computation out of these machines. In this spirit, we design a method to boost the computational power of nearterm quantum computers by adapting protocols used in quantum error correction to implement “Approximate Quantum Error Correction (AQEC):” By approximating fully-fledged error correction mechanisms, we can increase the compute volume (qubits $\times$ gates, or “Simple Quantum Volume (SQV)”) of near-term machines. The crux of our design is a fast hardware decoder that can approximately decode detected error syndromes rapidly. Specifically, we demonstrate a proof-of-concept that approximate error decoding can be accomplished online in near-term quantum systems by designing and implementing a novel algorithm in superconducting Single Flux Quantum (SFQ) logic technology. This avoids a critical decoding backlog, hidden in all offline decoding schemes, that leads to idle time exponential in the number of T gates in a program [58]. Our design utilizes one SFQ processing module per physical quantum bit. Employing state-of-the-art SFQ synthesis tools, we show that the circuit area, power, and latency are within the constraints of typical, contemporary quantum system designs. Under a pure dephasing error model, the proposed accelerator and AQEC solution is able to expand SQV by factors between 3,402 and 11,163 on expected near-term machines. The decoder achieves a 5% accuracy threshold as well as pseudo-thresholds of approximately 5%, 4.75%, 4.5%, and 3.5% physical error rates for code distances 3, 5, 7, and 9, respectively. Decoding solutions are achieved in a maximum of $\sim$20 nanoseconds on the largest code distances studied. By avoiding the exponential idle time in offline decoders, we achieve a 10x reduction in required code distances to achieve the same logical performance as alternative designs.

Recent efforts for finding novel computing paradigms that meet today's design requirements have given rise to a new trend of processing-in-memory relying on non-volatile memories. In this paper, we present HIPE-MAGIC, a technology-aware synthesis and mapping flow for highly parallel execution of the memristor-based logic. Our framework is built upon two fundamental contributions: balancing techniques during the logic synthesis, mainly targeting benefits of the parallelism offered by memristive crossbar arrays (MCAs), and an efficient technology mapping framework to maximize the performance and area-efficiency of the memristor-based logic. Our experimental evaluations across several benchmark suites demonstrate the superior performance of HIPE-MAGIC in terms of throughput and energy efficiency compared to recently developed synthesis and mapping flows targeting MCAs, as well as the conventional CPU computing.

This paper aims at integrating three powerful techniques namely Deep Learning, Approximate Computing, and Low Power Design into a strategy to optimize logic at the synthesis level. We utilize advances in deep learning to guide an approximate logic synthesis engine to minimize the dynamic power consumption of a given digital CMOS circuit, subject to a predetermined error rate at the primary outputs. Our framework, Deep-PowerX1, focuses on replacing or removing gates on a technology-mapped network and uses a Deep Neural Network (DNN) to predict error rates at primary outputs of the circuit when a specific part of the netlist is approximated. The primary goal of Deep-PowerX is to reduce the dynamic power whereas area reduction serves as a secondary objective. Using the said DNN, Deep-PowerX is able to reduce the exponential time complexity of standard approximate logic synthesis to linear time. Experiments are done on numerous open source benchmark circuits. Results show significant reduction in power and area by up to 1.47× and 1.43× compared to exact solutions and by up to 22% and 27% compared to state-of-the-art approximate logic synthesis tools while having orders of magnitudes lower run-time.

Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10 −19 J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2.68× and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit.

This article presents an overview of circuit-level techniques used for approximate computing (AC), including both computation and data storage units. After providing some background concept and methodology review, this article proceeds to provide a detailed review of prior art in circuit-level approximation techniques for data path and memory. The focus is on identifying key circuit-level approximation techniques that are applicable to the computational blocks in general and for both volatile and nonvolatile memory circuit technologies. Emphasis is also placed on the error metrics used to assess the output quality of approximate compute and memory units and whether the accuracy setting is dynamically reconfigurable. This article is concluded with a summary of the key distinguishing features of the reviewed prior art.

The high energy cost of processing deep convolutional neural networks impedes their ubiquitous deployment in energy-constrained platforms such as embedded systems and IoT devices. This article introduces convolutional layers with pre-defined sparse 2D kernels that have support sets that repeat periodically within and across filters. Due to the efficient storage of our periodic sparse kernels, the parameter savings can translate into considerable improvements in energy efficiency due to reduced DRAM accesses, thus promising significant improvements in the trade-off between energy consumption and accuracy for both training and inference. To evaluate this approach, we performed experiments with two widely accepted datasets, CIFAR-10 and Tiny ImageNet in sparse variants of the ResNet18 and VGG16 architectures. Compared to baseline models, our proposed sparse variants require up to ~82% fewer model parameters with 5.6× fewer FLOPs with negligible loss in accuracy for ResNet18 on CIFAR-10. For VGG16 trained on Tiny ImageNet, our approach requires 5.8× fewer FLOPs and up to ~83.3% fewer model parameters with a drop in top-5 (top-1) accuracy of only 1.2% (~2.1%). We also compared the performance of our proposed architectures with that of ShuffleNet and MobileNetV2. Using similar hyperparameters and FLOPs, our ResNet18 variants yield an average accuracy improvement of ~2.8%.

In this article, we present an energy-efficient approximate CGRA (X-CGRA). Instead of conventional exact arithmetic units, it employs configurable approximate adders and multipliers in the so-called quality-scalable processing elements (QSPEs). Furthermore, the structure and functionality of the other architectural components, like context memory, are modified based on the quality-scalable operating modes of the QSPEs. The quality reconfigurability of the X-CGRA makes it amenable for both error-resilient and nonresilient applications. To map the applications on the X-CGRA, a mapping technique is proposed that efficiently utilizes the QSPEs and selects appropriate approximation modes in order to lower the energy consumption while satisfying a user-defined quality constraint. We evaluate the efficacy of our X-CGRA for several benchmark applications from different domains, including image/video processing, signal processing, and scientific computations. Different sizes of X-CGRA are synthesized using a 15-nm FinFET technology. For these benchmarks, the results indicate energy consumption reduction of up to $3.21\times $ compared to those of a typical exact CGRA, at the cost of 4% quality loss.

Imprecise computations allow scheduling algorithms developed for energy-constrained computing devices to trade off output quality with utilization of system resources. The goal of such scheduling algorithms is to utilize imprecise computations to find a feasible schedule for a given task graph while maximizing the quality of service (QoS) and satisfying a hard deadline and an energy bound. This work presents a heuristic for scheduling tasks with potentially imprecise computations, represented with directed acyclic graphs, on multiprocessor platforms. Furthermore, it presents a mixed integer linear program formulation of the same problem, which provides the optimal reference scheduling solutions, enabling evaluation of the efficacy of the proposed heuristic. Both the heuristic and mathematical program take account of potentially imprecise inputs of tasks on their output quality. Furthermore, the presented heuristic is capable of finding feasible schedules even under tight energy budgets. Through extensive experiments, it is shown that in some cases, the proposed heuristic is capable of finding the same QoS as the ones found by MILP. Furthermore, for those task graphs that MILP outperforms the proposed heuristic, QoS values obtained with the proposed heuristic are, on average, within 1.24% of the optimal solutions while improving the runtime by a factor of 100 or so. This clearly demonstrates the advantage of the proposed heuristic over the exact solution, especially for large task graphs where solving the mathematical problem is hampered by its lengthy runtime.

This article investigates an energy-efficient accuracy-configurable Dadda (X-Dadda) multiplier. The structure employs the voltage overscaling and approximate width setting as the approximation knobs for improving the energy consumption as well as the reliability and lifetime of the multiplier. While the former may be set in the design time as well as the runtime, the latter may only be invoked in the design time. For a given accuracy level, the partial product columns and the overscaled voltage for optimizing the energy are determined. Normally, to have the error within a tolerable limit, the voltage overscaled columns are those at lower bit significances which have higher switching activities. The structure makes use of a low number of level shifters for a low-overhead realization. The approximate columns which start from the first column are contiguous. To further improve the efficiency of the multiplier, four-bit truncation of the multiplier output is also suggested. The efficiency of the X-Dadda structure is investigated using a 15-nm FinFET technology. The results indicate that, for example, when the approximate mode with the mean relative error distance (MRED) of 0.11 is considered, up to 43% energy saving is achieved. In addition, for this case, the Bias temperature instability (BTI)-induced delay degradation of the multiplier decreases up to 9.9% compared to 50% in the case of the exact mode. Also, the impact of process variations on the accuracy of the X-Dadda is studied. Finally, the efficacy of the X-Dadda multiplier, when used in neural networks for image classification and image-processing applications, is assessed.

In this brief, a low resource utilization field-programmable gate array (FPGA)-based long short-term memory (LSTM) network architecture for accelerating the inference phase is presented. The architecture has low-power and high-speed features that are achieved through overlapping the timing of the operations and pipelining the datapath. Moreover, this architecture requires negligible internal memory size for storing the intermediate data leading to low resource utilization and simple routing, which provides lower interconnect delay (higher operating frequency). A designer may adjust the resource utilization (as well as the latency) of the proposed architecture readily at the register-transfer level (RTL) design by adjusting the amount of parallelization. This makes the process of mapping the architecture onto different types of FPGAs, subject to defined constraints, a simple one. The efficacy of the proposed architecture is assessed by implementing an LSTM network on different types of FPGAs. Compared with the recent works, the proposed architecture provides up to about 1.6x , 43.6x , 21.9x , and 114.5x improvements in frequency, power efficiency, GOP/s, and GOP/s/W, respectively. Finally, our proposed architecture operates at 17.64 GOP/s, which is 2.31 faster than the best previously reported results.

In this article, we present a simple, yet energy- and area-efficient method for tolerating the stuck-at faults caused by an endurance issue in secure-resistive main memories. In the proposed method, by employing the random characteristics of the encrypted data encoded by the Advanced Encryption Standard (AES) as well as a rotational shift operation, a large number of memory locations with stuck-at faults could be employed for correctly storing the data. Due to the simple hardware implementation of the proposed method, its energy consumption is considerably smaller than that of other recently proposed methods. The technique may be employed along with other error correction methods, including the error correction code (ECC) and the error correction pointer (ECP). To assess the efficacy of the proposed method, it is implemented in a phase-change memory (PCM)based main memory system and compared with three error tolerating methods. The results reveal that for a stuck-at fault occurrence rate of 10-2and with the uncorrected bit error rate of 2 × 10-3, the proposed method achieves 82% energy reduction compared to the state-of-the-art method. More generally, using a simulation analysis technique, we show that the fault coverage of the proposed method is similar to that of the state-of-the-art method.

In this article, the accuracy of inverter-based memristive neural networks (NNs) for function approximation applications is improved under the presence of process variations. The improvement is achieved by using a design approach, called INTERSTICE (Inverter-based Memristive Neural Networks Dis cretization for Function Approximation Applications), which discretizes the output values by employing a classifier. More precisely, in the INTERSTICE approach, the output range is divided into K subranges where each subrange is considered as a class. To train the classifier, the training samples are labeled where each label shows belonging to a specific class. To evaluate the efficacy of the design technique, some function approximation applications such as BlackScholes, FFT, K-means, and Sobel are considered. Compared to PHAX, a recently published inverter-based memristive NN, INTERSTICE provides lower mean squared error (MSE) values in the presence of memristor and transistor variations. More specifically, the improvements in the mean of MSE (μMSE) are in the range of 40%-80% when considering 10% variations in the memristor resistance and transistor parameters. In addition, for most of the benchmarks, INTERSTICE improves the μMSE values of the nominal case (the case where all circuit elements are ideal) compared to PHAX. As another advantage compared to the PHAX, in INTERSTICE, digital outputs can be generated based on the selected classes which eliminates the need for an analog-to-digital converter at the output port connected to the digital part of the system. Finally, achieving lower μMSE values using fewer memristors and consuming lower energy is also attainable with this design approach.

In this article, we propose a framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications. The framework aims at optimizing the configuration for employing approximate memories in a computing system. It is based on considering data footprints at different memory hierarchy levels and an expected output quality to determine the amount of approximations at each memory hierarchy level. The problem of finding a suitable memory approximation configuration is performed using a branch-and-bound algorithm considering all possible memory approximation arrangements. The best configuration leading to the lowest power consumption when meeting the expected output quality is selected. The efficacy of the proposed framework for two memory hierarchies with different cache topologies is evaluated by comparing energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets. For example, with 28 dB as a peak signal to noise ratio (PSNR) constraint, the study, which is performed for four image processing applications, indicates up to 54% and 22% power consumption improvements for the SRAM cache and the DRAM memory, respectively.

Transfer-learning and meta-learning are two effective methods to apply knowledge learned from large data sources to new tasks. In few-class, few-shot target task settings (i.e. when there are only a few classes and training examples available in the target task), meta-learning approaches that optimize for future task learning have outperformed the typical transfer approach of initializing model weights from a pretrained starting point. But as we experimentally show, metalearning algorithms that work well in the few-class setting do not generalize well in many-shot and many-class cases. In this paper, we propose a joint training approach that combines both transfer-learning and meta-learning. Benefiting from the advantages of each, our method obtains improved generalization performance on unseen target tasks in both few- and many-class and few- and many-shot scenarios.

Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) are two major techniques for reducing energy consumption in such embedded systems. Furthermore, MPSoCs are becoming more popular for many real-time applications. One of the challenges of integrating DPM with DVFS and task scheduling of real-time applications on MPSoCs is the modeling of idle intervals on these platforms. In this paper, we present a novel approach for modeling idle intervals in MPSoC platforms which leads to a mixed integer linear programming (MILP) formulation integrating DPM, DVFS, and task scheduling of periodic task graphs subject to a hard deadline. We also present a heuristic approach for solving the MILP and compare its results with those obtained from solving the MILP.

Deep neural networks have been successfully deployed in a wide variety of applications including computer vision and speech recognition. To cope with computational and storage complexity of these models, this paper presents a training method that enables a radically different approach for realization of deep neural networks through Boolean logic minimization. The aforementioned realization completely removes the energy-hungry step of accessing memory for obtaining model parameters, consumes about two orders of magnitude fewer computing resources compared to realizations that use floating-point operations, and has a substantially lower latency.

Efficiently recognizing the functionality of a circuit is key to many applications, such as formal verification, reverse engineering, and security. We present a scalable framework for gate-level circuit recognition that leverages deep learning and a convolutional neural network (CNN)-based circuit representation. Given a standard cell library, we present a sparse mapping algorithm to improve the time and memory efficiency of the CNN-based circuit representation. Sparse mapping allows encoding only the logic cell functionality, independently of implementation parameters such as timing or area. We further propose a data structure, termed level-dependent decaying sum (LDDS) existence vector, which can compactly represent information about the circuit topology. Given a reference gate in the circuit, an LDDS vector can capture the function of the gates in the input and output cones as well as their distance (number of stages) from the reference. Compared to the baseline approach, our framework obtains more than an-order-of-magnitude reduction in the average training time and 2× improvement in the average runtime for generating CNN-based representations from gate-level circuits, while achieving 10% higher accuracy on a set of benchmarks including EPFL and ISCAS'85 circuits.

Single Flux Quantum (SFQ) logic with switching energy of 100zJ1 and switching delay of 1ps is a promising post-CMOS candidate. Logic synthesis of these magnetic-pulse-based circuits is a very important step in their design flow with a big impact on the total area, power consumption, and critical path delay. SFQ circuits has some properties different from CMOS which should be taken into consideration in the design and implementation flow of these circuits. One of these properties is requirement of path balancing in the standard SFQ circuit design. Standard CMOS-based rewriting and factorization algorithms fail to preserve the balancing property of SFQ circuits. Therefore, they end up generating circuits with huge path balancing overheads. Our proposed balanced factorization and rewriting algorithms are designed specifically to solve this problem. Experimental results show that a combination of balanced factorization and rewriting algorithms reduces the path balancing overhead by an average of 63% for 15 benchmark circuits, and area by up to 23% compared to state-of-the-art logic synthesis tools.

In this paper, we propose a novel hybrid verification framework (HVF) which uses Reinforcement Learning (RL) and Deep Neural Networks (DNNs) to accelerate the verification of complex systems. More precisely, our HVF incorporates RL to generate all possible sequences of vectors needed to approach a target state as well as the corresponding path to the target state which contains a potential design error. Furthermore, HVF utilizes DNNs to accelerate the verification of complex data paths in the target states. We have tested our framework on several circuits including multi-core designs as well as bus-arbiters and confirmed its significant verification speedup when compared to prior work. For example, HVF provides a total speedup of 4.5x for a quad-core MIPS processor verification.

Path balancing technology mapping is a method of mapping a technology-independent logical description of a circuit, such as a Boolean network, into a technology-dependent, gate-level netlist. For a gate-level netlist generated by the path balancing mapper, the difference between lengths of the longest and the shortest paths in the circuit is minimized. To achieve full path balancing, it may be necessary to add buffers on signal paths, and in such a case, the cost of buffers must be properly accounted for. This paper presents a dynamic programming-based technology mapping algorithm that generates a minimum-area mapping solution which is guaranteed to be fully path balanced. The fully path balanced mapping solution is essential to conventional superconductive single flux quantum circuits, which will fail otherwise. The balanced mapping solution is also useful in CMOS circuits to avoid (or minimize) unwanted hazard activity and the resulting wasteful dynamic power dissipation as well as to achieve the maximum throughput in a wave-pipelined circuit. Experimental results show that our path balancing technology mapping algorithm decreases total area, static power consumption, and path balancing overhead of single flux quantum circuits by large factors. For example, it reduces the circuit area by up to 111% and by an average of 26.3% compared to state-of-the-art technology mappers.

The miniaturization of transistors down to 5nm and beyond, plus the increasing complexity of integrated circuits, significantly aggravate short channel effects, and demand analysis and optimization of more design corners and modes. Simulators need to model output variables related to circuit timing, power, noise, etc., which exhibit nonlinear behavior. The existing simulation and sign-off tools, based on a combination of closed-form expressions and lookup tables are either inaccurate or slow, when dealing with circuits with more than billions of transistors. In this work, we present CSM-NN, a scalable simulation framework with optimized neural network structures and processing algorithms. CSM-NN is aimed at optimizing the simulation time by accounting for the latency of the required memory query and computation, given the underlying CPU and GPU parallel processing capabilities. Experimental results show that CSM-NN reduces the simulation time by up to 6× compared to a state-of-the-art current source model based simulator running on a CPU. This speedup improves by up to 15× when running on a GPU. CSM-NN also provides high accuracy levels, with less than 2% error, compared to HSPICE.

In this paper, we propose qCG, a multi-domain design and verification framework, which utilizes clock gating and frequency scaling to optimize dynamic power dissipation. SFQ circuits are ultra-deep pipelined at the logic level, resulting in large clock distribution networks which account for a considerable part of overall power dissipation. We have shown that qCG significantly increases power efficiency, not only for SFQ circuits, but also their clock networks and inherently cooling systems. The verification engine of qCG learns to increase the quality of results in terms of verification time and coverage. Datapath and coverage meters are embedded to verify the pulse integrity of clock signals, SFQ fanout, and path-balancing properties. Our experiments on several SFQ benchmark circuits show that qCG provides 3X power reductions for the chip. Results also confirm that when compared to a traditional random-based coverage-driven approach, qCG provides significant verification quality improvement including 2.33X verification speedup.

Recent studies have shown the latency and energy consumption of deep neural networks can be significantly improved by splitting the network between the mobile device and cloud. This paper introduces a new deep learning architecture, called BottleNet, for reducing the feature size needed to be sent to the cloud. Furthermore, we propose a training method for compensating for the potential accuracy loss due to the lossy compression of features before transmitting them to the cloud. BottleNet achieves on average 5.1× improvement in end-to-end latency and 6.9× improvement in mobile energy consumption compared to the cloud-only approach with no accuracy loss.

Researchers have been trying to exploit the temperature effect inversion (TEI) phenomenon to improve energy efficiency of system-on-chip (SoC) designs without sacrificing its performance. However, TEI-aware low power methods have a critical limitation in that they can only be applied to components within the SoC that do not contain long (global) wires. This is because wire delays continue to increase with rising temperatures irrespective of the operating supply voltage level, which tends to cancel out positive effects of the TEI phenomenon in SoCs. To tackle this limitation and thoroughly utilize the TEI-aware methods, this paper presents new TEI-inspired SoC platform (called TIP), which relies on network-on-chip architecture (called μNoC) to realize system interconnects. The μNoC successfully reduces the total number and length of global wires. By fabricating a TIP prototyping chip in Samsung 28nm FD-SOI technology, we verify the effectiveness of TIP. Extensive post-fabrication measurements demonstrate that the chip while continuing to operate at a target 50MHz clock frequency can lower its supply voltage from 0.54V to 0.48V at 25°C and to 0.44V at 80°C, which results in up to 35% power saving.

Temperature effect inversion (TEI) phenomenon in ultralow power (ULP) very large scale integration circuits has been identified as an important effect by both academia and industry. Although a number of ULP methods that attempt to exploit the TEI phenomenon have been proposed, the small size of the design exploration space when applying these methods to ULP circuits hinders them from achieving their full potential. This is mainly due to the limited granularity of the supply voltage level control. Starting with an intuition that the body biasing (BB) technique is a key to overcome this limitation, this paper exploits the BB technique along with the TEI-aware voltage scaling (TEI-VS) method and TEI-aware frequency scaling (TEI-FS) method, so as to substantially increase the design spaces of these methods. Techniques for optimally combining the BB technique with TEI-VS and TEI-FS are introduced. Simulation results with the latest commercial CMOS process technologies for ULP designs demonstrate the effectiveness of the proposed methodology.

In this paper, we present an accuracy-aware design framework [called accuracy-aware high-level synthesis (Achilles)], which synthesizes a high-level description of an input application with the objective of minimizing the energy consumption of the synthesized circuit. The proposed framework includes two main parts of Achilles and light-weight predictor selection. The framework leverages light-weight error predictors (i.e., machine learning-based classifiers) to achieve more energy reduction by dynamically managing the output quality level (exact or approximate) of the synthesized circuit. To synthesize the input application, first, we exploit a heuristic algorithm to determine the quality level required for each operation in the data flow graph (DFG) representation of the input application. Next, for synthesizing the input application, we propose an effective Achilles algorithm which utilizes the flexibility of the available multiquality arithmetic units in a high-level cell library to synthesize the datapath. To improve the efficiency, the process starts by iteratively reducing the number of functional units required for synthesizing the DFG. Then, a proper light-weight error predictor satisfying the user expected quality is chosen from the available predictors in the framework. Based on the quality requirements, three different quality management modes are considered. The efficacy of the proposed framework is assessed for benchmarks from image and signal processing as well as robotics domains. The study of these benchmarks indicates that Achilles may reduce the energy consumption up to 51% (36% on average), up to 72% (51% on average), and up to 57% (33% on average) in threshold, average, and hybrid modes, respectively, for the studied cases. Moreover, the results show that relative coverage of large errors may be increased from 21% to 55% by employing synthetic minority oversampling technique method.

A scalable approximate multiplier, called truncation- and rounding-based scalable approximate multiplier (TOSAM) is presented, which reduces the number of partial products by truncating each of the input operands based on their leading one-bit position. In the proposed design, multiplication is performed by shift, add, and small fixed-width multiplication operations resulting in large improvements in the energy consumption and area occupation compared to those of the exact multiplier. To improve the total accuracy, input operands of the multiplication part are rounded to the nearest odd number. Because input operands are truncated based on their leading one-bit positions, the accuracy becomes weakly dependent on the width of the input operands and the multiplier becomes scalable. Higher improvements in design parameters (e.g., area and energy consumption) can be achieved as the input operand widths increase. To evaluate the efficiency of the proposed approximate multiplier, its design parameters are compared with those of an exact multiplier and some other recently proposed approximate multipliers. Results reveal that the proposed approximate multiplier with a mean absolute relative error in the range of 11%-0.3% improves delay, area, and energy consumption up to 41%, 90%, and 98%, respectively, compared to those of the exact multiplier. It also outperforms other approximate multipliers in terms of speed, area, and energy consumption. The proposed approximate multiplier has an almost Gaussian error distribution with a near-zero mean value. We exploit it in the structure of a JPEG encoder, sharpening, and classification applications. The results indicate that the quality degradation of the output is negligible. In addition, we suggest an accuracy configurable TOSAM where the energy consumption of the multiplication operation can be adjusted based on the minimum required accuracy.

Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number generators: 1) the RAM-based Linear Feedback Gaussian Random Number Generator (RLF-GRNG), which is inspired by the properties of binomial distribution and linear feedback logics; and 2) the Bayesian Neural Network-oriented Wallace Gaussian Random Number Generator. To achieve high scalability and efficient memory access, we propose a deep pipelined accelerator architecture with fast execution and good hardware utilization. Experimental results demonstrate that the proposed VIBNN implementations on an FPGA can achieve throughput of 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J while maintaining similar accuracy as its software counterpart.

Coarse-Grained Reconfigurable Architectures (CGRAs) provide tradeoff between the energy-efficiency of Application Specific Integrated Circuits (ASICs) and the flexibility of General Purpose Processors (GPPs). State-of-the-art CGRAs only support exact architectures and precise application executions. However, a majority of the streaming applications such as multimedia and digital signal processing, which are amenable to CGRAs, are inherently error resilient. Therefore, these applications can greatly benefit from the emerging trend of Approximate Computing that leverages this error-resiliency to provide higher energy efficiency proportional to the tolerable accuracy loss (can even be constrained). This paper, for the first time, introduces the novel concept of Polymorphic Approximate CGRA (PX-CGRA) that employs heterogeneous tiles of Polymorphic-Approximated ALU Clusters (PACs) connected in a 2-D mesh style connection. These PACs can implement different approximate modes as well as accurate modes depending upon their selected configuration as per the run-time requirements of executing applications. For designing an efficient PX-CGRA, we propose a bottom-up design flow. In addition, the flow of application mapping on PX-CGRA is discussed including accuracy-level mapping, scheduling, and binding steps. To comprehensively evaluate the efficacy of the proposed CGRA, the complete PX-CGRA architecture in different sizes as well as with different PACs configurations are synthesized using a 15-nm FinFET technology. Our results show up to 15%-45% energy efficiency improvement for 5%-35% output quality degradation, respectively, when compared to the state-of-the-art exact-mode CGRA. Our proposed architecture and design methodology enable a new era of accuracy-configurable CGRAs to provide significant energy gains.

Deep learning has delivered its powerfulness in many application domains, especially in image and speech recognition. As the backbone of deep learning, deep neural networks (DNNs) consist of multiple layers of various types with hundreds to thousands of neurons. Embedded platforms are now becoming essential for deep learning deployment due to their portability, versatility, and energy efficiency. The large model size of DNNs, while providing excellent accuracy, also burdens the embedded platforms with intensive computation and storage. Researchers have investigated on reducing DNN model size with negligible accuracy loss. This work proposes a Fast Fourier Transform (FFT)-based DNN training and inference model suitable for embedded platforms with reduced asymptotic complexity of both computation and storage, making our approach distinguished from existing approaches. We develop the training and inference algorithms based on FFT as the computing kernel and deploy the FFT-based inference model on embedded platforms achieving extraordinary processing speed.

This paper presents a novel clustering based placement algorithm for single flux quantum (SFQ) family of super-conductive electronic circuits. In these circuits nearly all cells receive a clock signal and a placement algorithm that ignores the clock routing cost will not produce high quality solutions. To address this issue, proposed approach simultaneously minimizes the total wirelength of the signal nets and area overhead of the clock routing. Furthermore, construction of a perfect H-tree in SFQ logic circuits is not viable solution due to the resulting very high routing overhead and the in-feasibility of building exact zero-skew clock routing trees. Instead a hybrid clock tree must be used whereby higher levels of the clock tree (i.e., those closer to the clock source) are based on H-tree construction whereas lower levels of the clock tree follow a linear (i.e., chain-like) structure. The proposed approach is able to reduce the overall half-perimeter wirelength by 15% and area by 8% compared with state-of-the-art techniques.

This paper presents a novel method for accurate margin calculation of single flux quantum (SFQ) logic cells in a superconducting electronic circuit. The proposed method can be utilized as a figure of merit to estimate the robustness of a logic cell without the need for expensive Monte-Carlo simulations. This is achieved through efficient state-space exploration of all parameters in the cell structure. Using the proposed approach, distinct parameter dispersion (DPD) based yield of SFQ cells increases by 55% on average, compared with state-of-the-art techniques.

In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetime and reliability of coarse-grained reconfigurable architectures (GCRAs) is presented. The proposed technique, which may be applied to CGRAs used as accelerators for low-power, error-tolerant applications, reduces the (strongly voltage-dependent) wearout effects and the energy consumption of processing elements (PEs) whenever the error impact on the output quality degradation can be tolerated. This provides us with the ability to lessen the wearout and reduce energy consumption of PEs when accuracy requirement for the results is rather low. Multiple degrees of computational accuracy can be achieved by using different overscaled voltage levels for the PEs. The efficacy of the proposed technique is studied by considering the bias temperature instability. The study is performed for two error-resilient applications. The CGRAs are implemented with 15nm FinFET operating at a nominal supply voltage of 0.8V. In addition, supply voltages of 0.75, 0.7, 0.65, and 0.6V are considered as overscaled voltage levels for this technology. Based on the quality constraint requirements of the benchmarks, optimum overscaled voltage levels for various PEs are determined and utilized. The approach may provide considerable lifetime and energy consumption improvements over those of the conventional exact and approximate computation approaches.

In today's computing technology scene, mobile devices are considered to be computationally weak, while large cloud servers are capable of handling expensive workloads, therefore, intensive computing tasks are typically offloaded to the cloud. Recent advances in learning techniques have enabled Deep Neural Networks (DNNs) to be deployed in a wide range of applications. Commercial speech based intelligent personal assistants (IPA) like Apple's Siri, which employs DNN as its recognition model, operate solely over the cloud. The cloud-only approach may require a large amount of data transfer between the cloud and the mobile device. The mobile-only approach may lack performance efficiency. In addition, the cloud server may be slow at times due to the congestion and limited subscription and mobile devices may have battery usage constraints. In this paper, we investigate the efficiency of offloading only some parts of the computations in DNNs to the cloud. We have formulated an optimal computation offloading framework for forward propagation in DNNs, which adapts to battery usage constraints on the mobile side and limited available resources on the cloud. Our simulation results show that our framework can achieve 1.42x on average and up to 3.07x speedup in the execution time on the mobile device. In addition, it results in 2.11x on average and up to 4.26x reduction in mobile energy consumption.

With the increasing demand of high-speed mobile data transmission, densely deployed small cell base stations capable of caching popular contents have recently emerged as a promising technique to improve the quality of service for mobile users. In this paper, we investigate the cooperative transmission and power management problem for a set of ``off-grid'' base stations in a cellular network hierarchy that are powered solely by on-site renewable energy sources. The network throughput maximization problem is mathematically formulated as a mixed-integer non-linear programming problem. In the proposed formulation, a base station can adjust its transmission power in a coordinated multipoint communication scheme and/or switch to a "sleep mode" for energy saving. Based on the Lyapunov optimization theory, an efficient near-optimal solution method is proposed with provable bound of the optimality gap. Experimental results on a realistic setup show that the proposed algorithm can achieve up to 2.96x download throughput per user compared to some baseline algorithms.

Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.

The rise of machine learning (ML) has introduced many opportunities for computer-aided-design, VLSI design, and their intersection. Related to computer-aided design, we review several classical CAD algorithms which can benefit from ML, outline the key challenges, and discuss promising approaches. In particular, because some of the existing ML accelerators have used asynchronous design, we review the state-of-the-art in asynchronous CAD support, and identify opportunities for ML within these flows.

This article presents a framework for empowering automated cognition and decision making in complex cyber-physical systems (CPS). The key idea is for each cyber-physical component in the system to be able to construct from observations and actions a reduced model of its behavior and respond to external stimuli in the form of a (timed) probabilistic automaton such as a semi-Markov decision process. The reduced order behavioral models of various cyber-physical components can then be integrated into an optimization and decision-making module to determine the best actions for the components under different operating scenarios and cost/payoff functions by solving a bounded-rationality global decision-making problem.

Single flux quantum (SFQ) logic is a promising candidate to replace the CMOS logic for high speed and low power applications due to its superiority in providing high performance and energy efficient circuits. However, developing effective Electronic Design Automation (EDA) tools, which cater to special characteristics and requirements of SFQ circuits such as depth minimization and path balancing, are essential to automate the whole process of designing large SFQ circuits. In this paper, a novel technology mapping tool, called SFQmap, is presented, which provides optimization methods for minimizing first the circuit depth and path balancing overhead and then the worst-case stage delay of mapped SFQ circuits. Compared with the state-of-the-art technology mappers, SFQmap reduces the depth and path balancing overhead by an average of 14% and 31%, respectively.

Major advancements in building general-purpose and customized hardware have been one of the key enablers of versatility and pervasiveness of machine learning models such as deep neural networks. To sustain this ubiquitous deployment of machine learning models and cope with their computational and storage complexity, several solutions such as low-precision representation of model parameters using fixed-point representation and deploying approximate arithmetic operations have been employed. Studying the potency of such solutions in different applications requires integrating them into existing machine learning frameworks for high-level simulations as well as implementing them in hardware to analyze their effects on power/energy dissipation, throughput, and chip area. Lop is a library for design space exploration that bridges the gap between machine learning and efficient hardware realization. It comprises a Python module, which can be integrated with some of the existing machine learning frameworks and implements various customizable data representations including fixed-point and floating-point as well as approximate arithmetic operations. Furthermore, it includes a highly-parameterized Scala module, which allows synthesizing hardware based on the said data representations and arithmetic operations. Lop allows researchers and designers to quickly compare quality of their models using various data representations and arithmetic operations in Python and contrast the hardware cost of viable representations by synthesizing them on their target platforms (e.g., FPGA or ASIC). To the best of our knowledge, Lop is the first library that allows both software simulation and hardware realization using customized data representations and approximate computing techniques.

In1 this paper, we present a highly accurate and energy efficient non-iterative divider, which uses multiplication as its main building block. In this structure, the division operation is performed by first reforming both dividend and divisor inputs, and then multiplying the rounded value of the scaled dividend by the reciprocal of the rounded value of the scaled divisor. Precisely, the interval representing the fractional value of the scaled divisor is partitioned into non-overlapping sub-intervals, and the reciprocal of the scaled divisor is then approximated with a linear function in each of these sub-intervals. The efficacy of the proposed divider structure is assessed by comparing its design parameters and accuracy with state-of-the-art, non-iterative approximate dividers as well as exact dividers in 45nm digital CMOS technology. Circuit simulation results show that the mean absolute relative error of the proposed structure for doing 1 32-bit division is less than 0.2%, while the proposed structure has significantly lower energy consumption than the exact divider. Finally, the effectiveness of the proposed divider in one image processing application is reported and discussed.

In this paper, we propose an ultra low-power analog neuromorphic circuit to be trained to process sensory data in the Internet of Things smart sensors where low-power and are efficient computing is required. To reduce the operating voltage of the circuit while maintaining the performance, we focus on designing a memristive neuromorphic circuit without employing operational amplifiers. Therefore, we use the CMOS inverters as the neurons in our memristive neuromorphic circuit. We also propose ultra low-power mixed-signal input/output interfaces to make the circuit connectable to other digital components such as embedded processor. To assess the efficacy of the proposed circuit and its interfaces which include memristive neural network based A/D and D/A converters, HSPICE simulations are utilized. The results indicate that at the operating voltage of ±0.25 V, at least 108× (278×) reduction in the power consumption of the output (input) interface compared to that of the conventional structures is achieved. Additionally, the effectiveness of the neuromorphic circuit enhanced by the proposed interfaces is evaluated under some applications such as image recognition, human behavior analysis, and air quality predictions. The results of the study reveal that the designed neuromorphic circuits, along with the proposed A/D and D/A converters, provide an average power saving (speedup) of 2960× (37×) over the ASIC implementation in a 90-nm CMOS technology.

In this paper, we propose a training framework for an inverter-based memristive neuromorphic hardware. The framework, which is called PHAX, is a physical characteristics aware one relying on anex-situtraining approach. The considered neuromorphic circuit is highly energy efficient hybrid CMOS-memristive implementation of neuromorphic circuits. To solve the problem of high sensitivity of the training to the mismatches between the high-level mathematical modeling of the neurons and the corresponding physical characteristics, an approach for analytical yet accurate modeling of the memristive crossbar and neuron circuits is suggested. The approach, which is based on SPICE simulations, models the inverter-based neurons using a hyperbolic tangent function. To increase the training efficacy, the backpropagation training algorithm is modified by considering some constraints based on the physical characteristics of the memristive circuit. This modification along with the accurate back-annotation of the physical characteristics considerably improve the effectiveness of theex-situtraining method of the neuromorphic circuit. The results of this paper show an average reduction of 1805× in the training runtime compared to that of thein-situtraining approach. Furthermore, the results of applying the approach on the kernels of some applications such as image recognition, image processing, and financial analysis reveal that the designed neuromorphic circuits provide an average power saving (speed up) of 1478× (5.2×) over the ASIC implementation in a 90-nm CMOS technology.

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern of system-on-chip designers. Ultralow power (ULP) very large-scale integration circuits have been receiving considerable interest from both academia and industry as the best-suited techniques for IoT devices, which can take full advantage of power-saving that voltage scaling potentially achieves. Consequently, research on ULP designs has begun to yield tangible outcomes, namely ULP circuits. However, little attention has been paid to ULP network-on-chip (NoC), although the NoC is an essential of the ULP chips, and its power consumption accounts for a significant portion of the total power. This paper focuses on ULP NoCs, and presents a new power management method that exploits delay versus temperature characteristics of ULP circuits. Recent studies on ULP circuits show that delay versus temperature characteristics are fundamentally different from normal circuits, i.e., the delay of the ULP circuits implemented in state-of-the-art bulk CMOS operating at low supply voltages or in FinFET technologies decreases with increasing temperature, a phenomenon known as the temperature effect inversion (TEI). Starting with an intuition that at a certain temperature point, power savings without performance penalty can be achieved by increasing the router frequency to create the opportunity to turn off some routers in ULP NoCs, or by decreasing the NoC supply voltage level, an optimization method is presented to maximize the power savings with minor performance penalty. To validate the proposed method, a concrete ULP NoC simulator, TEI-Noxim, has been developed. Experimental results demonstrate that TEI-aware NoC achieves an average of 36.0% power reduction over 21 applications.

Thermal stress including temperature gradients in time and space, as well as thermal cycling, influences lifetime reliability and performance of modern multiprocessor systems-on-chip (MPSoCs). Conventional power and temperature management techniques considering the peak temperature/power consumption do not provide a comprehensive solution to avoid high spatial and temporal thermal variations. This work presents TheSPoT, a novel multilevel thermal stress-aware power and thermal management approach for MPSoCs. At the top level, core consolidation and deconsolidation is performed based on peak temperature, thermal stress, and power consumption constraints. These constraints are also used at the next level, where operating frequencies are determined. At this level, we obtain optimal core frequencies by solving a convex optimization problem. However, thereafter, to reduce the runtime overhead in large MPSoCs, we alternatively propose to use a fast heuristic algorithm. The efficacy of the proposed approaches in reducing the thermal cycles and temporal/spatial temperature gradients is evaluated by comparing the results with the state-of-the-art methods. The evaluation performed on 4-core, 8-core, and 16-core MPSoCs, using PARSEC benchmarks, reveals a considerable reduction in thermal stress. For the 8-core MPSoC case study, on average, for the proposed heuristic(optimal) approach, the mean time to failure improved by 47(35)% compared to the state-of-the-art techniques with only 6(4)% performance degradation. Also, our simulations show that TheSPoT is more efficient in thermal stress reduction when more heterogeneous workloads are used.

In this article, we present a critical path selection method that efficiently finds true (sensitizable) critical paths of a circuit in the presence of process variations. The method, which is based on the viability analysis, tries to select the least number of true critical paths that cover all of circuit critical gates. Critical gates are those that make a path critical with a probability higher than a predefined threshold value. Selecting fewer critical paths leads to less computation time for the algorithm and shorter test time of fabricated chips. For this purpose, an efficient Statistical Static Timing Analysis– (SSTA) based technique is suggested. This technique tries to find circuit-critical gates whose process parameter variations cover a major part of the process space. Improving the process space coverage using fewer paths is achieved by considering both spatial (proximity of gates) and structural (having common gates) correlations in the analysis of choosing the critical paths. In the selection process, paths with low similarities in their characteristics are preferred. In addition, only true paths whose delays affect the maximum delay of the circuit are included. The selected paths can be used in the test process of the fabricated chips to determine if the chip meets its timing requirements. Also, a modified viability analysis that incorporates statistical computations is used in the SSTA. The efficacy of the proposed method is evaluated by comparing its results for combinational and sequential ISCAS benchmarks with those obtained by exhaustive search. Results indicate although, on average, only 4.38% of all the critical paths found by the exhaustive search are selected by the proposed method, the maximum probability of criticality for the paths that are not considered in our method is, on average, less than 4%.

Improving the energy efficiency of cloud computing systems has become an important issue because the electric energy bill for 24/7 operation of these systems can be quite large. The focus of this paper is on the virtual machine consolidation in a cloud computing system as a way of lowering daily energy consumption of the system. In contrast to the existing works that assume resource demands of virtual machines are given as scalar variables, this paper treats these demands as random variables with known means and standard deviations because the demands are not deterministic in many situations. These random variables may be correlated with one another, and there are several types of resources which can be performance bottlenecks. Therefore, both correlations and resource type heterogeneity must be considered. The virtual machine consolidation problem is thus formulated as a multi-capacity stochastic bin packing problem. This problem is NP-hard, so we present a heuristic method to efficiently solve the problem. Simulation results show that, in spite of its simplicity and scalability, the proposed method produces high quality solutions.

Independent Component Analysis (ICA) is a dimensionality reduction technique that can boost efficiency of machine learning models that deal with probability density functions, e.g. Bayesian neural networks. Algorithms that implement adaptive ICA converge slower than their nonadaptive counterparts, however, they are capable of tracking changes in underlying distributions of input features. This intrinsically slow convergence of adaptive methods combined with existing hardware implementations that operate at very low clock frequencies necessitate fundamental improvements in both algorithm and hardware design. This paper presents an algorithm that allows efficient hardware implementation of ICA. Compared to previous work, our FPGA implementation of adaptive ICA improves clock frequency by at least one order of magnitude and throughput by at least two orders of magnitude. Our proposed algorithm is not limited to ICA and can be used in various machine learning problems that use stochastic gradient descent optimization.

Rapid Single Flux Quantum (RSFQ) logic cells have traditionally been limited to driving one fanout cell because of the difficulty in distributing the single flux quantum pulse to multiple fanouts. This paper presents a method to modify the standard RSFQ cells at their input/output interfaces to other cells in order to support a multiple-fanout drive capability. This capability is especially useful for clock distribution in RSFQ logic. This is because RSFQ logic is requires the clock signal to be provided to every logic gate. This is why this paper focuses on the clock signal driving more than one cell without the use of splitters. The potential tradeoff is in lower margins for the cells. However, by careful design of the RSFQ cells, the yield is not compromised by our proposed technique.

In this paper, an approach for increasing the sustainability of inverter-based memristive neuromorphic circuits in the presence of process variation is presented. The approach works based on extracting the impact of process variations on the neurons characteristics during the test phase through a proposed algorithm. In this method, first, some combinations of inputs and weights (based on the neuromorphic circuit structure) are injected into the circuit and the features of the neurons are determined. Next, these features which are back-annotated, are utilized in an efficient ex-situ training approach to determine the proper weights of the neurons. The approach provides a considerable improvement in the output accuracy. To evaluate the effectiveness of the proposed approach, some approximate applications are studied using 90nm CMOS technology. The results of the study reveal that using this framework provides, on average, 17X higher output accuracy compared to the cases that the impact of the process variation is not considered at all.

As a result of the Temperature Effect Inversion (TEI) in FinFET-based designs, gate delays decrease with the increase of temperature. In contrast, the resistive characteristic and hence delay of global interconnects increase with the temperature. However, as shown in this paper, if buffers are judiciously inserted in global interconnects, the buffer delay decrease is more pronounced than the interconnect delay increase, resulting in an overall performance improvement at higher temperatures. More specifically, this work models the delay of buffer-inserted global interconnects vs. temperature in order to derive the optimal number and size of buffers for a given interconnect length and temperature. Furthermore, the paper addresses the problem of minimizing the buffered interconnect energy consumption by changing the supply voltage level or FinFET threshold voltage, and also presents a temperature-aware optimization policy for solving this problem. Simulation results show average interconnect energy savings of 16% with no performance penalty for five different benchmarks implemented on a 14nm FinFET technology.

In this paper, we present a high speed yet energy efficient approximate divider where the division operation is performed by multiplying the dividend by the inverse of the divisor. In this structure, truncated value of the dividend is multiplied exactly (approximately) by the approximate inverse value of divisor. To assess the efficacy of the proposed divider, its design parameters are extracted and compared to those of a number of prior art dividers in a 45nm CMOS technology. Results reveal that this structure provides 66% and 52% improvements in the area and energy consumption, respectively, compared to the most advanced prior art approximate divider. In addition, delay and energy consumption of the division operation are reduced about 94.4% and 99.93%, respectively, compared to those of an exact SRT radix-4 divider. Finally, the efficacy of the proposed divider in image processing application is studied.

GPU adoption for general purpose computing has been accelerating. To support a large number of concurrently active threads, GPUs are provisioned with a very large register file (RF). The RF power consumption is a critical concern. One option to reduce the power consumption dramatically is to use near-threshold voltage(NTV) to operate the RF. However, operating MOSFET devices at NTV is fraught with stability and reliability concerns. The adoption of FinFET devices in chip industry is providing a promising path to operate the RF at NTV while satisfactorily tackling the stability and reliability concerns. However, the fundamental problem of NTV operation, namely slow access latency, remains. To tackle this challenge in this paper we propose to build a partitioned RF using FinFET technology. The partitioned RF design exploits our observation that applications exhibit strong preference to utilize a small subset of their registers. One way to exploit this behavior is to cache the RF content as has been proposed in recent works. However, caching leads to unnecessary area overheads since a fraction of the RF must be replicated. Furthermore, we show that caching is not efficient as we increase the number of issued instructions per cycle, which is the expected trend in GPU designs. The proposed partitioned RF splits the registers into two partitions: the highly accessed registers are stored in a small RF that switches between high and low power modes. We use the FinFET's back gate control to provide low overhead switching between the two power modes. The remaining registers are stored in a large RF partition that always operates at NTV. The assignment of the registers to the two partitions will be based on statistics collected by the a hybrid profiling technique that combines the compiler based profiling and the pilot warp profiling technique proposed in this paper. The partitioned FinFET RF is able to save 39% and 54% of the RF leakage and the dynamic energy, respectively, and suffers less than 2% performance overhead.

Bayesian neural networks (BNNs) have been proposed to address the problem of model uncertainty in training. By introducing weights associated with conditioned probability distributions, BNN is capable to resolve overfitting issues commonly seen in conventional neural networks. Frequent usage of Gaussian random variables requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware realization of BNN challenging. In this paper, a new hardware acceleration architecture for variational inference in BNNs is proposed to facilitate the applicability of BNN in larger-scale applications. In addition, the proposed implementation introduced the RAM based Linear Feedback based GRNG (RLF-GRNG) for effective weight sampling in BNNs. The RAM based Linear Feedback method can effectively utilize RAM resources for parallel Gaussian random number generation while requiring limited and sharable control logic. Implementation on an Altera Cyclone V FPGA suggests that the RLF-GRNG utilizes much less RAM resources compared to other GRNG methods. Experiments results show that the proposed hardware implementation of a BNN can still attain similar accuracy compared to software implementation.

Plug-in electric vehicles (PEVs) are considered the key to reducing fossil fuel consumption and an important part of the smart grid. The plug-in electric vehicle-to-grid (V2G) technology in the smart grid infrastructure enables energy flow from PEV batteries to the power grid so that the grid stability is enhanced and the peak power demand is shaped. PEV owners will also benefit from V2G technology, as they will be able to reduce energy cost through proper PEV charging and discharging scheduling. Moreover, power regulation service (RS) reserves have been playing an increasingly important role in modern power markets. It has been shown that by providing RS reserves, the power grid achieves a better match between energy supply and demand in presence of volatile and intermittent renewable energy generation. This article starts with the problem of PEV charging under dynamic energy pricing, properly taking into account the degradation of battery state-of-health (SoH) during V2G operations as well as RS provisioning. An overall optimization throughout the whole parking period is proposed for the PEV and an adaptive control framework is presented to dynamically update the optimal charging/discharging decision at each hour to mitigate the effect of RS tracking error. As more and more PEVs are being plugged into the power grid, the control or management issue of PEV charging arises, since mass unregulated charging processes of PEVs may result in degradation of power quality and damage utility equipments and customer appliances. To solve this problem, this article also presents an SoH-aware charging aggregator design, which decides the control sequences of a group of PEVs. An energy storage system is used in the charging aggregator to do a peak power shaving, and future parking PEVs are properly taken care of. Experimental results show that the proposed optimal charging algorithm minimizes the combination of electricity cost and battery aging cost in the RS provisioning power market. Experimental results also show that the introduction of charging aggregator can significantly reduce the peak power consumption caused by simultaneous PEV charging.

FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm technology nodes. However, based on the temperature effect inversion (TEI) phenomenon observed in FinFET devices, the delay characteristics of FinFET circuits in sub-, near-, and superthreshold voltage regimes may be fundamentally different from those of CMOS circuits with nominal voltage operation. For example, FinFET circuits may run faster in higher temperatures. Therefore, the existing CMOS-based and TEI-unaware dynamic power and thermal management techniques would not be applicable. In this article, we present TEI-power, a dynamic voltage and frequency scaling--based dynamic thermal management technique that considers the TEI phenomenon and also the superlinear dependencies of power consumption components on the temperature and outlines a real-time trade-off between delay and power consumption as a function of the chip temperature to provide significant energy savings, with no performance penalty—namely, up to 42% energy savings for small circuits where the logic cell delay is dominant and up to 36% energy savings for larger circuits where the interconnect delay is considerable.

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), on-chip networks are facing serious challenges in providing fast communication among various tasks and cores. One promising on-chip network design approach shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate routers, thereby reducing packet latency. This approach not only changes the packet latency models, but also greatly affects network traffic behaviors, both of which have not been fully exploited in existing mapping algorithms. In this article, we explore the opportunities in optimizing application mapping for flattened butterfly, a popular express channel-based on-chip network. Specifically, we identify the unique characteristics of flattened butterfly, analyze the opportunities and new challenges, and propose an efficient heuristic mapping algorithm. The proposed algorithm Contention-Aware Latency Minimal (CALM) is able to reduce unnecessary turns that would otherwise impose additional router pipeline latency to packets, as well as adjust forwarding traffic to reduce network contention latency. Simulation results show that the proposed algorithm can achieve, on average, 3.4X reduction in the number of turns, 24.8% reduction in contention latency, and 14.12% reduction in the overall packet latency.

In this brief, we propose an effective adaptation of viability analysis in statistical static timing analysis. The adaption benefits well from a dynamic programming implementation of the viability function. For a rapid identification of statistical longest true paths, the technique makes use of a fast preprocessing step identifying the gates with a small probability of being viable in the circuit, and a number of simple optimization techniques. This makes the approach fast without lowering its accuracy. The efficacy of the proposed statistical timing analysis is assessed using ISCAS benchmark circuits and carry skip adders. The results show that the proposed technique leads to, on average, 18× higher speed compared to those of the state-of-the-art technique. This improvement is achieved at the cost of -1.7% precision lost compared to that of the Monte-Carlo method.

In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy. Each of these compressors has its own level of accuracy in the approximate mode as well as different delays and power dissipations in the approximate and exact modes. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors in a 32-bit Dadda multiplier are evaluated in a 45-nm standard CMOS technology by comparing their parameters with those of the state-of-the-art approximate multipliers. The results of comparison indicate, on average, 46% and 68% lower delay and power consumption in the approximate mode. Also, the effectiveness of these compressors is assessed in some image processing applications.

In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The approach is to round the operands to the nearest exponent of two. This way the computational intensive part of the multiplication is omitted improving speed and energy consumption at the price of a small error. The proposed approach is applicable to both signed and unsigned multiplications. We propose three hardware implementations of the approximate multiplier that includes one for the unsigned and two for the signed operations. The efficiency of the proposed multiplier is evaluated by comparing its performance with those of some approximate and accurate multipliers using different design parameters. In addition, the efficacy of the proposed approximate multiplier is studied in two image processing applications, i.e., image sharpening and smoothing.

The usage of energy storage devices in data centers has been widely studied for the purpose of peak shaving in the context of dynamic utility pricing. To effectively achieve peak shaving in a data center with energy storage capability, a joint optimization framework is proposed to solve the task assignment problem and the energy storage management problem. The power hierarchy of a data center is modeled as a tree with battery arrays connected to each node, which is a generalization of common energy storage deployment topologies including the centralized structure and the rack/server-level distributed structure. A multi-dimensional resource request model is adopted based on released cluster traces in order to capture the complex dynamics of the workload of a data center. In addition, the rate capacity effect and aging effect are considered when modeling the batteries. A progressive refinement approach is used to solve the optimization problem. Experimental results show that the proposed algorithm consistently outperforms some baseline algorithms.

This paper investigates the hierarchical deployment and over-provisioning of energy storage devices (ESDs) in data ceners by (i) adopting a realistic power delivery architecture (from Intel) for centralized ESD structure as the starting point, (ii) presenting a novel and realistic power delivery architecture, borrowing the best features of the centralized ESD structure from Intel and distributed single-level ESD structures from Google and Microsoft, and supporting the case that different types of ESDs are employed for each of the data center, rack, and server levels, (iii) providing an optimal design (i.e., determining the ESD type, and ESD provisioning at each level) and control (i.e., scheduling the charging and discharging of various ESDs) framework to maximize the amortized profit of the hierarchical ESD structure. The amortized one-time capital cost (capex), operating cost (opex), and cost associated with battery aging and replacement are considered in the profit optimization. Constraints on ESD volume and realistic characteristics of ESDs and power conversion circuitries are accounted for in the framework. (iv) conducting experiments using real data center workload traces from Google based on realistic data center specifications, demonstrating the effectiveness of the proposed design and control framework.

The heating, ventilation and air conditioning (HVAC) system accounts for half of the energy consumption of a typical building. Additionally, the need for HVAC changes over hours and days as does the electric energy price. Level of comfort of the building occupants is, however, a primary concern, which tends to overwrite pricing. Dynamic HVAC control under a dynamic energy pricing model while meeting an acceptable level of occupants' comfort is thus critical to achieving energy efficiency in buildings in a sustainable manner. Finally, there is the possibility that the building is equipped with some renewable source of power such as solar panels mounted on the rooftop. The presence of a battery energy storage system in a target building would enable peak power shaving by adopting a suitable charge and discharge schedule for the battery, while simultaneously meeting building energy efficiency and user satisfaction. Achieving this goal requires detailed information (or predictions) about the amount of local power generation from the renewable source plus the power consumption load of the building. This paper addresses the coscheduling problem of HVAC control and battery management to achieve energy-efficient buildings, while also accounting for the degradation of the battery state-of-health during charging and discharging operations (which in turn determines the amortized cost of owning and utilizing a battery storage system)aa cč A time-of-use dynamic pricing scenario is assumed and various energy loss components are considered including power dissipation in the power conversion circuitry as well as the rate capacity effect in the battery. A global optimization framework targeting the entire billing cycle is presented and an adaptive co-scheduling algorithm is provided to dynamically update the optimal HVAC air flow control and the battery charging/discharging decision in each time slot during the billing cycle to mitigate the prediction error of unknown parameters. Experimental results show that the proposed algorithm achieves up to 15% in the total electric utility cost reduction compared with some baseline methods.

The objective of this paper is to minimize the energy-delay product of static random access memory (SRAM) arrays by using a device-circuit architecture co-optimization framework. More specifically, at the device-level, high-Vt FinFETs are adopted for the 6T SRAM cell, which significantly reduces the leakage power and improves static noise margins. However, due to the lower ON current, the bit-line delay of the read access is increased. Accordingly, at the circuit-level, the voltage level of assist circuits, and at the architecture-level (i.e., the array organization), key parameters of the SRAM array are jointly optimized to derive a design that results in the minimum energy-delay product point. By using the proposed optimization framework, for SRAM array capacities ranging from 1KB to 16KB, on average 59% lower energy-delay product with maximum 12% (and on average 9%) performance penalty is achieved.

This paper deals with obtaining the minimum operating voltage of memory arrays based on TFET SRAM cells. First, we compare the I-V characteristics of two TFETs and one FDSOI using SPICE simulations based on 20nm technology models. The results reveal that TFET devices exhibit high ON/OFF current ratios at different power supply voltage levels. This observation suggests a higher stability for SRAM cells based on these devices. Next, the characteristics of 6T SRAM cells implemented using minimum sized transistors based on these three device structures are compared. The comparison, which considers two TFET cell structures, i.e., inward and outward SRAMs, is performed at different supply voltages. The results for the hold static noise margin show that at low supply voltages (i.e., below 300mV), the FDSOI SRAM cell cannot hold data whereas both the inward and outward structures of TFET have acceptable noise margins at all supply voltages. Among the two TFET structures, the outward cell is selected because of higher speed especially for the write operation. TFET SRAMs suffer from long read access latency at ultra-low supply voltages (e.g., 150mV). The problem, however, may be overcome by using the negative GND read-assist technique. The results show that for a 32×32 TFET outward SRAM array, the minimum energy consumption (energy-delay product) may be achieved at the supply voltage of 200mV (300mV) with 1.32GHz (4.55GHz) as the read access frequency

Various power management techniques have been exploited to reduce the energy consumption of data centers. In this work, we propose a reinforcement learning-based power management framework for data centers, which does not rely on any given stationary assumptions of the job arrival and job service processes. By carefully designing the state space, the action space, and the reward of a learning process, the objective of the reinforcement learning agent coincides with our goal of reducing the server pool energy consumption with reasonable average job response time. Real Google cluster data traces are used to verify the effectiveness of the proposed reinforcement learning-based data center power management framework.

It is projected that hundreds of cores can be integrated into a chip at the sub-20nm technology nodes. However, some challenges exist in the many-core architecture such as maintaining memory coherence, underutilized parallelism, and increased inter-core communication delay. This work proposes the data-center-on-a-chip (DCoC) paradigm employing virtualization technologies commonly used in today's data centers to reduce the overhead of maintaining memory coherence and inter-core communication and improve parallelism. In the DCoC paradigm, user applications with specific resource requirements need to be mapped onto different chips of a data center and different cores of a chip in the form of virtual machines (VMs). By a judicious VM mapping method, the data center performance can be maximized while satisfying the power budget and power density constraints of the chips and the resource requirements of VMs. To tackle the NP-hardness of the VM mapping problem, we propose a two-tier algorithm, which effectively solves the mapping problem with polynomial time complexity.

In this work, to increase the timing yield of Tunnel Field Effect Transistor (TFET) circuits in the presence of the process variation, we propose to use MOSFET-based gates instead of some TFET-based gates in the TFET circuits. This hybridization approach originates from the fact that TFETs are more sensitive to process variation, when compared to conventional MOSFETs. First, we investigate the impact of process variations on Homojunction InAs TFETs by extracting the distributions of electrical parameters such as threshold voltage. Then, a hybrid TFET-MOSFET circuit design approach for increasing the reliability of the TFET circuits is introduced. The power consumptions of hybrid circuits are considerably smaller than the corresponding ones realized using CMOS circuits. In the proposed hybrid approach, the circuit is basically implemented in TFET to reduce the power and energy consumption while the gates whose their variations may lead to the timing violation, are implemented using MOSFET-based gates. The decision on replacing the TFET-based gates by their corresponding MOSFET-based gates during the hybrid design is made through a heuristic algorithm. The proposed algorithm considers the sensitivity of each TFET-based gate to the process variation. To assess the efficacy of the proposed approach, the proposed algorithm is applied to some circuits of the ISCAS'85 and ISCAS'89 benchmark packages. The results show that the reliability of the TFET-MOSFET-based circuits are up to 74% larger than that of the pure TFET-based circuits. Furthermore, the energy and leakage power consumptions of the proposed hybrid circuits are up to 56% and 80%, respectively, smaller than those of the pure MOSFET-based design.

To cope with uncertainties and variations that emanate from hardware and/or application characteristics, dynamic power management (DPM) frameworks must be able to learn about the system inputs and environmental variations, and adjust the power management policy on the fly. In this paper, an online adaptive DPM technique is presented based on the model-free reinforcement learning (RL) method, which requires no prior knowledge of the state transition probability function and the reward function. In particular, this paper employs the temporal difference (TD) learning method for semi-Markov decision process (SMDP) as the model-free RL technique since the TD method can accelerate convergence and alleviate the reliance on the Markovian property of the power-managed system. In addition, a novel workload predictor based on an online Bayesian classifier is presented to provide effective estimation of the workload characteristics for the RL algorithm. Several improvements are proposed to manage the size of the action space for the learning algorithm, enhance its convergence speed, and dynamically change the action set associated with each system state. In the proposed DPM framework, power-latency tradeoffs of the power-managed system can be precisely controlled based on a user-defined parameter. Extensive experiments on hard disk drives and wireless network cards show that the maximum power saving without sacrificing any latency is 18.6 percent compared to a reference expert-based approach. Alternatively, the maximum latency saving without any power dissipation increase is 73.0 percent compared to the existing best-of-breed DPM techniques.

This paper addresses the problem of balancing the on-chip packet latencies in a chip multi-processor (CMP), which is simultaneously executing multiple applications. Specifically, this paper presents a balanced application-to-core mapping algorithm that aims to minimize the maximum on-chip packet latency of all running applications. The paper starts by formulating the balanced mapping problem for CMPs and proving its NP-completeness. Next it presents an efficient heuristic algorithm for solving the aforesaid problem, which utilizes the characteristics of on-chip cache and memory accesses in CMPs and takes into account the workload variations among applications. Simulation results on PARSEC benchmark suite show that the proposed algorithm lowers the maximum average packet latency of all applications by 11 percent while cutting the standard deviation of on-chip packet latencies by 99 percent. This is achieved by very little overhead in terms of the overall packet latency and power consumption averaged over all packets.

In this paper, we propose a single probability density function for the distributions of the delay in the presence of the process variation for different regions of operation. The delay variation model is inspired by considering the analytical current models for each operating region. Based on these models, we suggest using the log-skew-normal distribution for modeling the delay variation for a wide range of supply voltages from the subthreshold to above-threshold regions. To assess the accuracy of the proposed delay distribution, the mean, standard deviation, skewness, 99th percentile, and yield of the proposed distribution are compared with those of the normal and log-normal distributions using the Monte Carlo (MC) simulations for different circuits in both bulk and FinFET technologies. The results show a higher accuracy for the proposed distribution in all regions of operation. Also, the proposed model enables us to obtain the 3σ yield of the distribution using up to 3.4 times less MC simulation time.

Energy harvesting is a promising technique to overcome the limit on energy availability and increase the lifespan of battery-powered embedded systems. In this paper, the question of how one can achieve the prolonged lifespan1of a real-time embedded system with energy harvesting capability (RTES-EH) is investigated. The RTES-EH comprises a photovoltaic (PV) panel for energy harvesting, a supercapacitor for energy storage, and a real-time sensor node as the embedded load device. A global controller performs simultaneous optimal operating point tracking for the PV panel, state-of-charge (SoC) management for the supercapacitor, and energy-harvesting-aware real-time task scheduling with dynamic voltage and frequency scaling (DVFS) for the sensor node, while employing a precise solar irradiance prediction method. The controller employs a cascaded feedback control structure, where an outer supervisory control loop performs real-time task scheduling with DVFS in the sensor node while maintaining the optimal supercapacitor SoC for improved system availability, and an inner control loop tracks the optimal operating point of the PV panel on the fly. Experimental results show that the proposed global controller lowers the task instance drop rate by up to 63% compared with the baseline controller within the same service time (i.e., from sunrise to sunset).

This paper introduces a joint charge and thermal management problem for batteries in a battery-supercapacitor hybrid power source of a portable system, which has been equipped with a forced convection cooling technique, such as a fan. A key consideration in such a system is that the battery aging depends strongly on the battery temperature, which is in turn a function of the workload running on the device and the control policy for the fan. More precisely, this paper presents a hierarchical algorithm for maximizing the battery lifespan under given workload conditions. The algorithm relies on a combination of reinforcement learning and dynamic programming techniques. Simulation results show that the proposed algorithm achieves up to 2× improvements in battery lifespan, resulting in completion of up to 80% additional workload before the battery expires.

Hybrid electrical energy storage (HEES) systems have the potential to result in considerable cost savings by reducing the electric bills of home users. This paper first presents grid-connected dual-bank HEES system design and management to maximize the electric bill savings for residential users, and subsequently provides a comprehensive sensitivity analysis of the economic feasibility of residential HEES systems. Specifically, the paper describes a daily management policy based on energy buffering strategy with one bank as the main storage bank and the other as the energy buffering bank, and then derive the global design of HEES specifications based on the daily management results. Simulation results prove the effectiveness of energy buffering strategy and show the proposed HEES system is capable of bringing in profits under current input variables. Finally, a detailed analysis is conducted to show how each input variable affects the final design of the proposed residential HEES system and the maximum annual profits it achieves. Together with the design and control mechanism, the proposed analysis provides potential customers with the comprehensive knowledge of how HEES systems can be deployed to achieve savings in their electric bills.

In this work, a hierarchical, service level agreement (SLA) based resource management solution for cloud datacenters is presented, which considers the energy non-proportionality of existing servers, peak power constraints, and cooling power consumption. The goal of this resource manager is to minimize the operational cost of the data center. The hierarchical structure of the proposed solution makes the resource management scalable. The proposed resource management solution simultaneously considers server and cooling power consumption, guarantee-based SLA and complexity of the decision making in the resource management of the cloud computing systems. Considering SLA and state of the datacenter in determining the amount of resource that needs to be allocated to applications results in significant reduction of the operational cost in datacenter. The effectiveness of the proposed management scheme compared to previous work is demonstrated using a comprehensive cloud computing simulation tool. The proposed resource management algorithms reduce the operational cost of a datacenter by about 40 percent while satisfying SLA constraints and decrease the run-time of the management algorithms by up to 86 percent with respect to the state of the art centralized management solution.

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power-delay product was the lowest among the structures considered in this paper, while its energy-delay product was almost the same as that of the Kogge-Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

Companies operating large datacenters are focusing on how to reduce the electrical energy costs of operating datacenters. A common way of cost reduction is to perform a dynamic voltage and frequency scaling (DVFS), thereby matching the CPU's performance and power level to incoming workloads. Another power saving technique is CPU consolidation, which uses the minimum number of CPUs necessary to meet the service request demands and turns OFF the remaining unused CPUs. DVFS has been already extensively studied and verified its effectiveness. On the other hand, it is necessary to study more about the effectiveness of CPU consolidation. Key questions that must be answered are how effectively the CPU consolidation improves the energy efficiency and how to maximize the improvement. These questions are addressed in this paper. After understanding modern power management techniques and developing an appropriate power model, this paper provides an extensive set of hardware-based experimental results and makes suggestions about how to maximize energy efficiency improvement through CPU consolidation. In addition, this paper also presents new online CPU consolidation algorithms, which reduce the energy-delay product up to 13% compared with the Linux default DVFS algorithm.

This paper addresses the problem of profit maximization for a data center with battery banks deployed at various levels of the power hierarchy. An optimization framework that covers the request dispatch, server resource allocation, and battery charging management is proposed. Instead of controlling the input/output power of the batteries after knowing the power profile of all other components of the data center as in a set of prior work, an optimal management policy is proposed which adjusts the power consumption (or supply) of servers and the battery banks at the same time. A response time dependent revenue model is adopted based on the delay estimation using the generalized processor sharing model. The rate capacity effect and the state of health degradation of the batteries, as well as the conversion and transmission loss in the power delivery network, are considered for the purpose of accurate power modeling and utility cost estimation. It is shown that the problem can be transformed into a series of convex optimization problems and then solved using standard solvers.

Recent work has presented hierarchical deployment of energy storage devices (ESDs) at the data center, rack, and server levels within a data center, along with a corresponding control framework for peak power shaving and energy cost reduction under (time-of-use) dynamic energy pricing policies. However, the prior work does not use a realistic power delivery architecture of the data center with hierarchical ESD structure, and fails to account for some key characteristics such as rate capacity effect of batteries and power losses in various AC/DC and DC/DC converters in the power delivery architecture. This paper aims to overcome these shortcomings by (i) adopting a realistic power delivery architecture (from Intel) for centralized ESD structure as the starting point, (ii) presenting a novel power delivery architecture for data centers with hierarchical ESD structure, borrowing the best features of the centralized ESD structure from Intel and the distributed single-level ESD structures from Google and Microsoft, (iii) providing a mathematical framework for the optimal design (i.e., ESD provisioning) and control (i.e., Scheduling the charging and discharging of various ESDs) of the hierarchical ESD structure to minimize overall energy cost under dynamic energy pricing functions. This framework accounts for constraints on ESD volume (for each level) and the overall (annually amortized) capital cost, and power losses due to the rate capacity effect and conversion circuitry. The ESD design problem is solved by using a search-based algorithm, whereas the ESD control problem is formulated and solved as a hierarchical convex optimization algorithm. Experiments have been conducted using real Google cluster workload based on realistic data center specifications, demonstrating the effectiveness of the proposed optimal design and control framework.

Dynamic energy pricing is a promising technique in the Smart Grid to alleviate the mismatch between electricity generation and consumption. Energy consumers are incentivized to shape their power demands, or more specifically, schedule their electricity-consuming applications (tasks) more prudently to minimize their electric bills. This has become a particularly interesting problem with the availability of residential photovoltaic (PV) power generation facilities and controllable energy storage systems. This paper addresses the problem of joint task scheduling and energy storage control for energy consumers with PV and energy storage facilities, in order to minimize the electricity bill. A general type of dynamic pricing scenario is assumed where the energy price is both time-of-use and power-dependent, and various energy loss components are considered including power dissipation in the power conversion circuitries as well as the rate capacity effect in the storage system. A negotiation-based iterative approach has been proposed for joint residential task scheduling and energy storage control that is inspired by the state-of-the-art Field-Programmable Gate Array (FPGA) routing algorithms. In each iteration, it rips-up and re-schedules all tasks under a fixed storage control scheme, and then derives a new charging/discharging scheme for the energy storage based on the latest task scheduling. The concept of congestion is introduced to dynamically adjust the schedule of each task based on the historical results as well as the current scheduling status, and a near-optimal storage control algorithm is effectively implemented by solving convex optimization problem(s) with polynomial time complexity. Experimental results demonstrate the proposed algorithm achieves up to 64.22% in the total energy cost reduction compared with the baseline methods.

A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some prespecified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology.

Incorporating residential-level photovoltaic energy generation and energy storage systems have proved useful in utilizing renewable power and reducing electric bills for the residential energy consumer. This is particular true under dynamic energy prices, where consumers can use PV-based generation and controllable storage modules for peak shaving on their power demand profile from the grid. In general, accurate PV power generation and load power consumption predictions and accurate system modeling are required for the storage control algorithm in most previous works. In this work, the reinforcement learning technique is adopted for deriving the optimal control policy for the residential energy storage module, which does not depend on accurate predictions of future PV power generation and/or load power consumption results and only requires partial knowledge of system modeling. In order to achieve higher convergence rate and higher performance in non-Markovian environment, we employ the TD(Λ)-learning algorithm to derive the optimal energy storage system control policy, and carefully define the state and action spaces, and reward function in the TD(Λ)-learning algorithm such that the objective of the reinforcement learning algorithm coincides with our goal of electric bill minimization for the residential consumer. Simulation results over real-world PV power generation and load power consumption profiles demonstrate that the proposed reinforcement learning-based storage control algorithm can achieve up to 59.8% improvement in energy cost reduction.

Plug-in electric vehicles (PEVs) are considered the key to reducing the fossil fuel consumption and an important part of the smart grid. The plug-in electric vehicle-to-grid (V2G) technology in the smart grid infrastructure enables energy flow from PEV batteries to the power grid so that the grid stability is enhanced and the peak power demand is shaped. PEV owners will also benefit from V2G technology as they will be able to reduce energy cost through proper PEV charging and discharging scheduling. Moreover, power regulation service (RS) reserves have been playing an increasingly important role in modern power markets. It has been shown that by providing RS reserves, the power grid achieves a better match between energy supply and demand in presence of volatile and intermittent renewable energy generation. This paper addresses the problem of PEV charging under dynamic energy pricing, properly taking into account the degradation of battery state-of-health (SoH) during V2G operations as well as RS provisioning. An overall optimization throughout the whole parking period is proposed for the PEV and an adaptive control framework is presented to dynamically update the optimal charging/discharging decision at each time slot to mitigate the effect of RS tracking error. Experimental results show that the proposed optimal PEV charging algorithm minimizes the combination of electricity cost and battery aging cost in the RS provisioning power market.

Autonomous driving has become a major goal of automobile manufacturers and an important driver for the vehicular technology. Hybrid electric vehicles (HEVs), which represent a trade-off between conventional internal combustion engine (ICE) vehicles and electric vehicles (EVs), have gained popularity due to their high fuel economy, low pollution, and excellent compatibility with the current fossil fuel dispensing and electric charging infrastructures. To facilitate autonomous driving, an autonomous HEV controller is needed for determining the power split between the powertrain components (including an ICE and an electric motor) while simultaneously managing the power consumption of auxiliary systems (e.g., air-conditioning and lighting systems) such that the overall electromobility is enhanced. Certain (partial) prior knowledge of the future driving profile is useful information for the automatic HEV control. In this paper, methods for predicting driving profile characteristics to enhance HEV power control are first presented. Based on the prediction results and the observed HEV system state (e.g. velocity, battery state-of-charge, propulsion power demand), we propose a reinforcement learning method to determine the power source split between the ICE and electric motor while also controlling the power consumptions of the air-conditioning and lighting systems in the automobile. Experimental results demonstrate significant improvement in the overall HEV system efficiency.

The impact of dark silicon phenomenon on multicore processors under deeply-scaled FinFET technologies is investigated in this paper. To do this accurately, a cross-layer framework, spanning device, circuit, and architecture levels is initially introduced. Using this framework, leakage and dynamic power consumptions as well as frequency levels of in-order and out-of-order (OoO) processor cores, and on-chip cache memories and routers in a network-on-chip-based chip multiprocessor system synthesized in 7nm FinFET technology and operating in both super- and near-threshold voltage regimes are presented. Subsequently, total power consumptions of multicore chips manufactured with (i) OoO and (ii) in-order processor cores are reported and compared. According to our results, for a 64-core chip and 15W thermal design power budget, 64% and 39% dark silicon are observed in OoO and in-order multicores, respectively, under super-threshold regime. These percentages drop to 19% and 0% for OoO and in-order multicores operating in the near-threshold regime, respectively. Furthermore, the highest energy efficiencies are achieved by operating in the near-threshold regime, which points to the effectiveness of near-threshold computing in mitigating the effect of dark silicon phenomenon under deeply-scaled technologies.

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independent-gate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is established by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of both shorted-gate and independent-gate standard cells are then characterized according to lambda-based layout design rules for FinFET devices. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independent-gate FinFETs.

As chip designs penetrate further into the dark silicon era, innovative techniques are much needed to power off idle or under-utilized system components while having minimal impact on performance. On-chip network routers are potentially good targets for power-gating, but packets in the network can be significantly delayed as their paths may be blocked by powered-off routers. In this paper, we propose Power Punch, a novel performance-aware, power reduction scheme that aims to achieve non-blocking power-gating of on-chip network routers. Two mechanisms are proposed that not only allow power control signals to utilize existing slack at source nodes to wake up powered-off routers along the first few hops before packets are injected, but also allow these signals to utilize hop count slack by staying ahead of packets to "punch through " any blocked routers along the imminent path of packets, preventing packets from having to suffer router wakeup latency or packet detour latency. Full system evaluation on PARSEC benchmarks shows Power Punch saves more than 83% of router static energy while having an execution time penalty of less than 0.4%, effectively achieving near non-blocking power-gating of on-chip network routers.

This paper investigates the energy management problem in hybrid electric vehicles (HEVs) focusing on the minimization of the operating cost of an HEV, including both fuel and battery replacement cost. More precisely, the paper presents a nested learning framework in which both the optimal actions (which include the gear ratio selection and the use of internal combustion engine versus the electric motor to drive the vehicle) and limits on the range of the state-of-charge of the battery are learned on the fly. The inner-loop learning process is the key to minimization of the fuel usage whereas the outer-loop learning process is critical to minimization of the amortized battery replacement cost. Experimental results demonstrate a maximum of 48% operating cost reduction by the proposed HEV energy management policy.

This paper introduces ThermTap, which enables system and software developers to monitor the power consumption and temperature of various hardware components in an Android device as a function of running applications and processes. ThermTap comprises of a power analyzer, called PowerTap, and an online thermal simulator, called Therminator 2. With accurate power macro-models, PowerTap collates activity profiles of major components of a portable device from the OS kernel device drivers in an event-driven manner to generate power traces. In turn, Therminator 2 reads these traces and, using a compact thermal model of the device, generates various temperature maps including those for the device components and device skin. Fast thermal simulation techniques enable Therminator 2 to be executed in realtime. With precise per-process and per-application temperature maps that ThermTap produces, it enables software and system developers to find thermal bugs in their software. A case study is presented on identifying a thermal bug in the software running on an Android device.

Dynamic voltage scaling (DVS) has proven effective in minimizing the power consumption of OLED displays, resulting only in minimal image distortion. This technique has been extended to perform zone-specific DVS by dividing the panel area into zones and applying independent DVS to each zone based on the displayed content. The application of the latter technique to large-area OLED displays has not been done in part due to a high overhead of its dedicated DC-DC converter for each zone and low conversion efficiency when the load current of each converter lies outside the desirable range. To address this issue, this work proposes a reconfigurable power delivery network architecture, comprised of a small number of DC-DC converters, a switch network and an online controller, to realize fine-grained (zone-specific) DVS in large-area OLED display panels. The proposed framework consistently achieves high power conversion efficiency and significant energy saving while preserving the image quality. Experimental results demonstrate that up to 36% power savings can be achieved in a 65" 4K Ultra high-definition OLED display by using the proposed framework.

Photovoltaic (PV) power generation systems are usually accompanied by battery to bridge the gap between the generation and load demand. Solar tracking is also used to enhance the power stability and increase the amount of collected energy from the Sun. However, battery and tracking devices significantly increase the system cost, and they are subject to wear and tear, which makes maintenance-free installation challenging. In this work, we conduct the design optimization of a twofold three dimensional PV panel for solar-powered systems. With the proposed three dimensional arrangement, we extend the solar-powered time of the target application that is powered only with solar power. Experimental results show that the proposed architecture and control method extend the service time of the target system by up to 23% compared to a non-reconfigurable flat panel with the same PV panel area.

In contrast to conventional internal combustion engine (ICE) propelled vehicles, hybrid electric vehicles (HEVs) can achieve both higher fuel economy and lower pollutant emissions. The HEV features a hybrid propulsion system consisting of one ICE and one or more electric motors (EMs). The use of both ICE and EM increases the complexity of HEV power management, and so advanced power management policy is required for achieving higher performance and lower fuel consumption. This work aims at minimizing the HEV fuel consumption over any driving cycles, about which no complete information is available to the HEV controller in advance. Therefore, this work proposes to model the HEV power management problem as a Markov decision process (MDP) and derives the optimal power management policy using the policy iteration technique. Simulation results over real-world and testing driving cycles demonstrate that the proposed optimal power management policy improves HEV fuel economy by 23.9% on average compared to the rule-based policy.

The emerging trend toward utilizing chip multicore processors (CMPs) that support dynamic voltage and frequency scaling (DVFS) is driven by user requirements for high performance and low power. To overcome limitations of the conventional chip-wide DVFS and achieve the maximum possible energy saving, per-core DVFS is being enabled in the recent CMP offerings. While power consumed by the CMP is reduced by per-core DVFS, power dissipated by the set of voltage regulators (VRs) that are required to support per-core DVFS becomes critical. This paper focuses on the dynamic control of the VRs in a CMP platform. Starting with a proposed platform with a reconfigurable VR-to-core power distribution network (PDN), two optimization methods are presented to maximize the system-wide energy savings: 1) reactive VR consolidation (VRCon) to reconfigure the network for maximizing the power conversion efficiency of the VRs, which is performed under the predetermined DVFS levels for the cores and 2) proactive VRCon to determine new DVFS levels for maximizing the total energy savings without any performance degradation. Along with the optimization methods for the PDN composed of homogeneous VRs, we also discuss the PDN with heterogeneous VRs, which is proposed to increase the benefits of the VRCon by incorporating VRs with a larger driving capability of load current. Results from detailed simulations based on realistic experimental setups demonstrate up to 36% VR energy loss reduction and 9% total energy saving.

In this article, a heuristic custom instruction (CI) selection algorithm is presented. The proposed algorithm, which is called OPLE for “Optimization based on Partitioning and Local Exploration,” uses a combination of greedy and optimal optimization methods. It searches for the near-optimal solution by reducing the search space based on partitioning the identified CI set. The partitioning of the identified set guarantees the success of the algorithm independent of the size of the identified set. First, the algorithm finds the near-optimal CIs from the candidate CIs for each part. Next, the suggested CIs from different parts are combined to determine the final selected CI set. To improve the set of the selected CIs, the solution is evolved by calling the algorithm iteratively. The efficacy of the algorithm is assessed by comparing its performance to those of optimal and nonoptimal methods. A comparative study is performed for a number of benchmarks under different area budgets and I/O constraints. The results reveal higher speedups for the OPLE algorithm, especially for larger identified candidate sets and/or small area budgets compared to those of the nonoptimal solutions. Compared to the nonoptimal techniques, the proposed algorithm provides 30% higher speedup improvement on average. The maximum improvement is 117%. The results also demonstrate that in many cases OPLE is able to find the optimal solution.

Mobile cloud computing (MCC) offers significant opportunities in performance enhancement and energy saving for mobile, battery-powered devices. Applications running on mobile devices may be represented by task graphs. This work investigates the problem of scheduling tasks (which belong to the same or possibly different applications) in the MCC environment. More precisely, the scheduling problem involves the following steps: (i) determining the tasks to be offloaded onto the cloud, (ii) mapping the remaining tasks onto (potentially heterogeneous) local cores in the mobile device, (iii) determining the frequencies for executing local tasks, and (iv) scheduling tasks on the cores (for in-house tasks) and the wireless communication channels (for offloaded tasks) such that the task-precedence requirements and the application completion time constraint are satisfied while the total energy dissipation in the mobile device is minimized. A novel algorithm is presented, which starts from a minimal-delay scheduling solution and subsequently performs energy reduction by migrating tasks among the local cores and the cloud and by applying the dynamic voltage and frequency scaling technique. A linear-time rescheduling algorithm is proposed for the task migration. Simulation results demonstrate significant energy reduction with the application completion time constraint satisfied.

Mobile cloud computing (MCC) offers significant opportunities in performance enhancement and energy saving in mobile, battery-powered devices. An application running on a mobile device can be represented by a task graph. This work investigates the problem of scheduling tasks (which belong to the same or possibly different applications) in an MCC environment. More precisely, the scheduling problem involves the following steps: (i) determining the tasks to be offloaded on to the cloud, (ii) mapping the remaining tasks onto (potentially heterogeneous) cores in the mobile device, and (iii) scheduling all tasks on the cores (for in-house tasks) or the wireless communication channels (for offloaded tasks) such that the task-precedence requirements and the application completion time constraint are satisfied while the total energy dissipation in the mobile device is minimized. A novel algorithm is presented, which starts from a minimal-delay scheduling solution and subsequently performs energy reduction by migrating tasks among the local cores or between the local cores and the cloud. A linear-time rescheduling algorithm is proposed for the task migration. Simulation results show that the proposed algorithm can achieve a maximum energy reduction by a factor of 3.1 compared with the baseline algorithm.

Operating circuits in the near/sub-threshold regime can lower the circuit energy consumption at the expense of lowering the circuit speed. In addition near/sub-threshold can result in higher sensitivity to process-induced variations and transient noise. FinFETs have been proposed as an alternative to planar CMOS devices in sub-20nm CMOS technology nodes due to their more effective channel control, steep sub-threshold slope, high ON/OFF current ratio, low power consumption, and so on. Characteristics of FinFETs operating in the near/sub-threshold regime make it difficult to verify the timing of a circuit using conventional statistical static timing analysis (SSTA) techniques. Current source modeling (CSM) methods, which have been proposed to increase the accuracy of timing analysis in dealing with arbitrary shapes of the input signal waveforms, are the appropriate solution for performing SSTA on FinFET-based circuits. This paper thus extends the CSM to such circuits, operating in the near/sub-threshold voltage regime. In particular, FinFET devices with independent gate control and subject to process variations are modelled. The key idea of the proposed CSM approach is to combine non-linear analytical models and low-dimensional CSM lookup tables to simultaneously achieve high modeling accuracy and low time/space complexity.

Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid architectures are presented in this paper. The proposed approaches benefit from Mixed Integer Programming (MIP) formulation for the qubit placement problem. Simulation results on various benchmarks show 27% on average reduction in communication overhead between qubits compared to best results of previous work.

Advances in the thermoelectric cooling technology have made it one of the promising solutions for spot cooling in VLSI circuits. Thermoelectric coolers (TECs) generate heat during their operation. This heat plus the heat generated in the circuit should be transferred to the ambient environment in order to avoid high die temperatures. This paper describes a hybrid cooling solution in which TECs are augmented with forced-convection coolers (fans). Precisely, an optimization framework called OFTEC is presented which finds the optimum TEC driving current and the fan speed to minimize the overall power consumption of the cooling system while maintaining safe die temperatures. Simulation results on a set of eight benchmarks show the benefits of the proposed approach. In particular, a baseline system without TECs but with a fan could meet the thermal constraint for only three of the benchmarks whereas the OFTEC solution satisfied thermal constraints for all benchmarks. In addition, OFTEC resulted in 5.4% less average power consumption for the aforesaid three benchmarks while lowering the maximum die temperature by an average of 3.7°C.

Cloud computing and storage have attracted a lot of attention due to the ever increasing demand for reliable and cost-effective access to vast resources and services available on the Internet. Cloud services are typically hosted in a set of geographically distributed data centers, which we will call the cloud infrastructure. To minimize the total cost of ownership of this cloud infrastructure (which accounts for both the upfront capital cost and the operational cost of the infrastructure resources), the infrastructure owners/operators must do a careful planning of data center locations in the targeted service area (for example the US territories), data center capacity provisioning (i.e., the total CPU cycles per second that can be provided in each data center). In addition, they must have flow control policies that will distribute the incoming user requests to the available resources in the cloud infrastructure. This paper presents an approach for solving the unified problem of data center placement and provisioning, and request flow control in one shot. The solution technique is based on mathematical programming. Experimental results, using Google cluster data and placement/provisioning of up to eight data center sites demonstrate the cost savings of the proposed problem formulation and solution approach.

For modern high performance systems, aggressive technology and voltage scaling has drastically increased their susceptibility to soft errors. At the grand scale of cloud computing, it is clear that soft error induced failures will occur far more frequently, but it is unclear as to how to effectively apply current error detection and fault tolerance techniques in scale. In this paper, we focus on energy-aware fault tolerant scheduling in public, multi-user cloud systems, and explore the three-way tradeoff between reliability (in terms of soft error resiliency), performance and energy. Through a systematically optimized resource allocation, error detection approach selection, virtual machine placement, spatial/temporal redundancy augmentation and task scheduling process, the cloud service provider can achieve high error coverage and fault tolerance confidence while minimizing global energy costs under user deadline constraints. Our scheduling algorithm includes a static scheduling phase that operates on task graph based workload inputs prior to execution, and a light-weight dynamic scheduler that migrates tasks during execution in case of excessive reexecutions. All schedules are evaluated on a runtime simulation engine that (1) mimics the performance fluctuations in cloud systems, and (2) supports the injection of arbitrary fault patterns. Compared to current virtual machine or task replication techniques, we are able to reduce overall application failure rates by over 50% with approximately 76% total energy overhead.

In this paper, we propose to move the conventional extensible processor design flow to the approximate computing domain to gain more speedup. In this domain, the instruction set architecture (ISA) design flow selects both exact and approximate custom instructions (CIs). The proposed approach could be used for the applications where imprecise results may be tolerated. In the CI identification phase of the flow, the CIs which do not satisfy the maximum propagation delay but can provide approximate results also may be included in the CI candidate set. Next, in the selection phase, we propose a merit function which selects CIs with higher cycle savings and small error rates. The efficacy of the proposed approximate design flow is investigated using the case studies of the discrete cosine transform (DCT) and inverse DCT (iDCT) of the MPEG2 application. Also, the impact of the process variation on the impreciseness of the results is investigated.

This paper introduces a novel sensor-less, event-driven power analysis framework called FEPMA for providing highly accurate and nearly instantaneous estimates of power dissipation in an Android smartphone. The key idea is to collect and correctly record various events of interest within a smartphone as applications are running on the application processor within it. This is in turn done by instrumenting the Android operating system to provide information about power/performance state changes of various smartphone components at the lowest layer of the kernel to avoid time stamping delays and component state observability issues. This technique then enables one to perform fine-grained (in time and space) power metering in the smartphone. Experimental results show significant accuracy improvement compared to previous approaches and good fidelity with respect to actual current measurements. The estimation error of the proposed method is lower by a factor of two than the state-of-the-art method.

The emerging trend toward utilizing chip multi-core processors (CMPs) that support dynamic voltage and frequency scaling (DVFS) is driven by user requirements for high performance and low power. To overcome limitations of the conventional chip-wide DVFS and achieve the maximum possible energy saving, per-core DVFS is being enabled in the recent CMP offerings. While power consumed by the CMP is reduced by per-core DVFS, power dissipated by many voltage regulators (VRs) needed to support per-core DVFS becomes critical. This paper focuses on the dynamic control of the VRs in a CMP platform. Starting with a proposed platform with a configurable VR-to-core power distribution network, two optimization methods are presented to maximize the system-wide energy savings: (i) reactive VR consolidation to reconfigure the network for maximizing the power conversion efficiency of the VRs performed under the pre-determined DVFS levels for the cores, and (ii) proactive VR consolidation to determine new DVFS levels for maximizing the total energy savings without any performance degradation. Results from detailed experiments demonstrate up to 35% VR energy loss reduction and 14% total energy saving.

Hybrid electrical energy storage (HEES) systems consisting of heterogeneous electrical energy storage (EES) elements are proposed to exploit the strengths of different EES elements and hide their weaknesses. The cycle life of the EES elements is one of the most important metrics. The cycle life is directly related to the state-of-health (SoH), which is defined as the ratio of full charge capacity of an aged EES element to its designed (or nominal) capacity. The SoH degradation models of battery in the previous literature can only be applied to charging/discharging cycles with the same state-of-charge (SoC) swing. To address this shortcoming, this paper derives a novel SoH degradation model of battery for charging/discharging cycles with arbitrary patterns. Based on the proposed model, this paper presents a near-optimal charge management policy focusing on extending the cycle life of battery elements in the HEES systems while simultaneously improving the overall cycle efficiency.

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), the on-chip networks are facing serious challenges in providing fast communication for various tasks and cores. One promising solution shown in recent studies is to add express channels to the network as shortcuts to bypass intermediate routers, thereby reducing packet latency. However, this approach also greatly changes the packet delay estimation and traffic behaviors of the network, both of which have not yet been exploited in existing mapping algorithms. In this paper, we explore the opportunities in optimizing application mapping for express channel-based on-chip networks. Specifically, we derive a new delay model for this type of networks, identify their unique characteristics, and propose an efficient heuristic mapping algorithm that increases the bypassing opportunities by reducing unnecessary turns that would otherwise impose the entire router pipeline delay to packets. Simulation results show that the proposed algorithm can achieve a 2∼4X reduction in the number of turns and 10∼26% reduction in the average packet delay.

Solar photovoltaic (PV) technology has been widely deployed in large power plants operated by utility companies. However, the home owners are not yet convinced of the saving cost benefits of this technology, and consequently, in spite of government subsidies, they have been reluctant to install PV systems in their homes. The main reason for this is the absence of a complete and truthful analysis which could explain to home owners under what conditions spending money on a PV system can actually save them money over a long-term, but known, time horizon. This paper thus presents a design and management mechanism for a smart residential energy system comprising PV modules, electrical energy storage banks, and conversion circuits connected to the power grid. First, we figure out how much savings can be achieved by a system with given PV modules and EES bank capacities by optimally solving the daily energy flow control problem of such a system. Based on the daily optimization results, we come up with the optimal system specifications with a fixed budget. Experiments are conducted for various electricity prices and different profiles of PV output power and load demand. Results show that the designed system breaks even in 6 years and in the system lifetime achieves up to 8% annual profit besides paying back the budget.

Quantum algorithms for solving problems of interesting size often result in circuits with a very large number of qubits and quantum gates. Fortunately, these algorithms also tend to contain a small number of repetitively-used quantum kernels. Identifying the quantum logic blocks that implement such quantum kernels is critical to the complexity management for realizing the corresponding quantum circuit. Moreover, quantum computation requires some type of quantum error correction coding to combat decoherence, which in turn results in a large number of ancilla qubits in the circuit. Sharing the ancilla qubits among quantum operations (even though this sharing can increase the overall circuit latency) is important in order to curb the resource demand of the quantum algorithm. This paper presents a multi-core reconfigurable quantum processor architecture, called Requp, which supports a layered approach to mapping a quantum algorithm and ancilla sharing. More precisely, a scalable quantum mapper, called Squash, is introduced, which divides a given quantum circuit into a number of quantum kernels--each kernel comprises k parts such that each part will run on exactly one of k available cores. Experimental results demonstrate that Squash can handle large-scale quantum algorithms while providing an effective mechanism for sharing ancilla qubits.

FinFET has been proposed as an alternative for bulk CMOS in the ultra-low power designs due to its more effective channel control, reduced random dopant fluctuation, higher ON/OFF current ratio, lower energy consumption, etc. The characteristics of FinFETs operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper introduces an analytical transregional FinFET model with high accuracy in both subthrehold and near-threshold regions. The unique feature of independent gate controls for FinFET devices is exploited for achieving a tradeoff between energy consumption and delay, and balancing the rise and fall times of FinFET gates. This paper proposes an effective design framework of FinFET standard cells based on the adaptive independent gate control method such that they can operate properly at all of subthreshold, near-threshold and super-threshold regions. The optimal voltage for independent gate control is derived so as to achieve equal rise and fall times or minimal energy-delay product at any supply voltage level.

Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation. Digital circuits supporting such burst-mode applications should work in both the near-threshold regime and the super-threshold regime for brief time periods. This work proposes the structure support of fine-grained ultra dynamic voltage scaling (UDVS) from the traditional strong-inversion region to the near-threshold region, with limitations on the number of power rails. The number, type, and size of the power switches are jointly optimized to minimize the overall energy consumption of the UDVS circuit block, meanwhile satisfying the target delay or frequency requirement at each DVS level. The proposed optimization framework properly accounts for the dynamic energy consumption as well as the leakage energy consumption through all the power switches during both the operation time and stand-by time of the circuit block. Experimental results on 22nm Predictive Technology Model demonstrate the effectiveness of the proposed optimization framework.

Due to the limited battery capacity in mobile devices, the concept of mobile cloud computing (MCC) is proposed where some applications are offloaded from the local device to the cloud for higher energy efficiency. The portion of applications or tasks to be offloaded for remote processing should be judiciously determined. In this paper, the problem of optimal task dispatch, transmission, and execution in the MCC system is considered. Dynamic voltage and frequency scaling (DVFS) is applied to the local mobile processor, whereas the RF transmitter of the mobile device can choose from multiple modulation schemes and bit rates. The power consumptions of the mobile components that cannot be directly controlled, e.g., the touch screen, GPU, audio codec, and I/O ports, are also accounted for through capturing their correlation with the mobile processor and RF transmitter. Finally, a realistic and accurate battery model is adopted in this work in order to estimate the battery energy loss rate in a more accurate way. This paper presents a semi-Markov decision process (SMDP)-based optimization framework, with the actions of different DVFS levels and modulation schemes/transimission bit rates and the objective of minimizing both the energy drawn from the battery and the average latency in request servicing. This paper derives the optimal solution, including the optimal DVFS policy, offloading rate, and transmission scheme, using linear programming combined with a heuristic search. Experiments are conducted on Qualcomm Snapdragon Mobile Development Platform MSM8660 to find the correlations among the power consumptions of the CPU, RF components, and other components. Simulation results show that the proposed optimal solution consistently outperforms some baseline algorithms.

Compared to conventional internal combustion engine (ICE) propelled vehicles, hybrid electric vehicles (HEVs) can achieve both higher fuel economy and lower pollution emissions. The HEV consists of a hybrid propulsion system containing one ICE and one or more electric motors (EMs). The use of both ICE and EM increases the complexity of HEV power management, and therefore requires advanced power management policies to achieve higher performance and lower fuel consumption. Towards this end, our work aims at minimizing the HEV fuel consumption over any driving cycle (without prior knowledge of the cycle) by using a reinforcement learning technique. This is in clear contrast to prior work, which requires deterministic or stochastic knowledge of the driving cycles. In addition, the proposed reinforcement learning technique enables us to (partially) avoid reliance on complex HEV modeling while coping with driver specific behaviors. To our knowledge, this is the first work that applies the reinforcement learning technique to the HEV power management problem. Simulation results over real-world and testing driving cycles demonstrate the proposed HEV power management policy can improve fuel economy by 42%.

Energy efficiency has always been an important design criterion for portable embedded systems. To compensate for the shortcomings of electrochemical batteries such as low power density, limited cycle life, and the rate capacity effect, supercapacitors have been employed as complementary power supplies for electrochemical batteries, i.e., hybrid power supplies comprised of batteries and supercapacitors have been proposed. In this work, we consider a portable embedded system with a hybrid power supply and executing periodic real-time tasks. We perform system power management from both the power supply side and the power consumption side to maximize the system service time. Specifically, we use feedback control for maintaining the supercapacitor energy at a certain level by regulating the discharging current of the battery, such that the supercapacitor has the capability to buffer the load current fluctuation. At the power consumption side, we perform task scheduling to assist supercapacitor energy maintenance. Experimental results demonstrate that the proposed joint optimization framework of task scheduling and power supply control successfully prolongs the total service time by up to 57%.

Spin-Transfer Torque Magnetic RAM (STT-MRAM) technology requires a high current in order to write data into memory cells, which gives rise to large access transistors in conventional MOS-accessed cells. On the other hand, FinFET devices offer higher ON current and denser layout compared with planar CMOS transistors. This paper thus proposes the design of an energy-efficient STT-MRAM cell which utilizes a FinFET access transistor. To assess the performance of the new cell, optimal layout-related parameters of the FinFET access transistor and the MTJ are analytically derived in order to minimize the STT-MRAM cell area. Afterwards, detailed cell- and architecture-level comparisons between FinFET- vs. MOS-accessed STT-MRAMs are performed. According to the comparison results, while the area of the MOS-accessed STT-MRAM increases significantly under 3ns write pulse width (τw), the FinFET-based design can effectively function under τw= 2ns, at the cost of slight increase in the memory area. Hence, the FinFET-accessed STT-MRAM offers denser area and higher energy efficiency compared with the conventional MOS-accessed counterpart.

Power gating is a very effective method in reducing the leakage energy during the standby mode in VLSI circuits at the cost of increased circuit delay. This method has been well studied and widely used for circuits fabricated by using traditional CMOS technology nodes operating at super-threshold supply voltage regime. However, for advanced technology nodes with small feature sizes and low supply voltages, the propagation delay becomes very sensitive to the high process-induced variations. Therefore, this paper first analyzes how the circuit delay depends on the size of the sleep transistor under the process-induced variation for the 7nm gate length FinFET technology. Then a joint optimization problem is formulated to minimize the total energy consumption, while both supply voltage and sleep transistor size are considered as optimization variables. A near-optimal heuristic is presented to solve the optimization problem and determine the energy-optimal supply voltage and sleep transistor size. Experimental results based on HSPICE simulations show that more than 98% energy reduction for applications with relaxed deadline constraints after applying the joint optimization technique, compared to FinFET circuits without using the power gating method.

As cloud computing is becoming the new generation of computing paradigm because of its many attractive attributes, huge data centers are built and operated to host the cloud services. Since these data centers usually incur a high electricity bill, the problem of reducing the electricity cost and maximizing the profit for a data center operator arises naturally. Because of the trend of dynamic pricing policies in the energy market, in which the electricity price changes across different hours of a day, the use of energy storage devices, such as batteries and supercapacitors, in a data center can be extended in addition to judicious computing/memory/storage resource management policies as another way to cut down on the operational cost. In this paper, we formulate a generalized optimization problem to minimize the linear combination of the electricity cost and the average request response time in a data center with energy storage devices. Solutions based on convex optimization techniques are proposed and the experimental results are discussed to demonstrate the effectiveness of the proposed formulation and the solution methods.

To improve the cycle efficiency and peak output power density of energy storage systems in electric vehicles (EVs), supercapacitors have been proposed as auxiliary energy storage elements to complement the mainstream Lithium-ion (Li-ion) batteries. The performance of such a hybrid electrical energy storage (HEES) system is highly dependent on the implemented management policy. This paper presents a model-free reinforcement learning-based approach to dynamically manage the current flows from and into the battery and supercapacitor banks under various scenarios (combinations of EV specs and driving patterns). Experimental results demonstrate that the proposed approach achieves up to 25% higher efficiency compared to a Li-ion battery only storage system and outperforms other online HEES system control policies in all test cases.

As the number of cores continues to grow in chip multiprocessors (CMPs), application-to-core mapping algorithms that leverage the non-uniform on-chip resource access time have been receiving increasing attention. However, existing mapping methods for reducing overall packet latency cannot meet the requirement of balanced on-chip latency when multiple applications are present. In this paper, we address the looming issue of balancing minimized on-chip packet latency with performance-awareness in the multi-application mapping of CMPs. Specifically, the proposed mapping problem is formulated, its NP-completeness is proven, and an efficient heuristic-based algorithm for solving the problem is presented. Simulation results show that the proposed algorithm is able to reduce the maximum average packet latency by 10.42% and the standard deviation of packet latency by 99.65% among concurrently running applications and, at the same time, incur little degradation in the overall performance.

This paper demonstrates that a partially solar powered EV can significantly save battery energy during cruising using innovative fast photovoltaic array (PV) reconfiguration. Use of all the vehicle sur- face areas, such as the hood, rooftop, door panels, quarter pan- els, etc., makes it possible to install more PV modules, but it also results in severe performance degradation due to inherent partial shading. This paper introduces fast online PV array reconfigura- tion and customization of the PV array installation according to the driving pattern and overcomes the partial shading phenomenon. We implement a high-speed, high-voltage PV reconfiguration switch network with IGBTs (insulated-gate bipolar transistors) and a controller. We derive the optimal reconfiguration period based on the solar irradiance/driving profiles using adaptive learning method, where the on/off delay of IGBT, CAN (control area network) delay, computation overhead, and energy overhead are taken into account. Experimental results show 25% more power generation from the PV array. This paper also introduces two important design-time optimization problems to achieve trade-off between performance and overhead. We derive the optimal PV reconfiguration granularity and partial PV array mounting by the car owner's driving pattern, which results in more than 20% PV cell cost reduction.

Due to limits on the availability of the energy source in many mobile user platforms (ranging from handheld devices to portable electronics to deeply embedded devices) and concerns about how much heat can effectively be removed from chips, minimizing the power consumption has become a primary driver for system-on-chip designers. Because of their superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the delay vs. temperature characteristics of FinFET-based circuits are fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET-based circuits without any appreciable performance penalty. Experimental results demonstrate 40% energy saving (with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.

Maintaining safe chip and device skin temperatures in small form-factor mobile devices (such as smartphones and tablets) while continuing to add new functionalities and provide higher performance has emerged as a key challenge. This paper presents Therminator, an early stage, fast, full-device thermal analyzer, which generates accurate steady-state temperature maps of the entire smartphone starting from the Application Processor and other key device components, extending to the skin of the device itself. The thermal analysis is sensitive to detailed device specifications (including its material composition and 3-D layout) as well as different use cases (each case specifying the set of active device components and their activity levels). Therminator considers all major components within the device, builds a corresponding compact thermal model for each component and the whole device, and produces their steady-state temperature maps. Temperature results obtained by using Therminator have been validated against a commercial computational fluid dynamics-based tool, i.e., Autodesk Simulation CFD, and thermocouple measurements on a Qualcomm Mobile Developer Platform. A case study on a Samsung Galaxy S4 using Therminator is provided to relate the device performance to the skin temperature and investigate the thermal path design.

While power gating is a promising technique to reduce the static power consumption of network-on-chip (NoC), its effectiveness is often hindered by the requirement of maintaining network connec-tivity and the limited knowledge of traffic behaviors. In this paper, we present Smart Butterfly, a core-state-aware NoC power-gating scheme based on flattened butterfly that utilizes the active/sleep state information of processing cores to improve power-gating effectiveness. Smart Butterfly exploits the rich connectivity of the flattened butterfly topology to allow more on-chip routers to be power-gated when their attached cores are asleep. We present two heuristic algorithms to determine the set of routers to be turned on to maintain connectivity and allow tradeoff between power consumption and average packet latency. Simulation results show an average of 42.85% and 60.48% power reduction of Smart Butterfly over prior art on 4x4 and 8x8 networks, respectively.

A compilation of work related to a priori estimation of interconnect lengths in VLSI circuits is provided, with an emphasis on procedural wire length estimation methods that do not require knowledge of the circuit layout and instead rely on structural analysis of the circuit net list and stochastic modeling of the underlying placement and routing tools. Reviewed work includes references listed below.

In this article, we investigate the impact of process variations on the speedup and maximum frequency of the extended ISA processor. First, without considering process variations, a custom functional unit (CFU) is designed based on nominal timing parameters, then the timing variations of critical paths of the extensible processor, including the baseline processor and the CFU, are investigated by considering both systematic and random variations. Next, the maximum frequency of the extensible processor and the speed enhancement factor of the extended ISA for different benchmarks are investigated. Results show that timing variation could reduce the speedup of the extensible processor. However, this reduction is highly dependent on the baseline processor and the CFU structures. Additionally, the impact of process variations in the worst-case design approach is studied. Results show that the speedup of the extensible processor is reduced more than in the case when custom instructions (CIs) are selected without considering process variations. To study the impact of each variation type, speedup variations due to random and systematic variations are investigated separately. The study reveals that random variation has a similar effect on the CFU and the baseline processor, while the impact of systematic variation on the baseline processor is greater than the CFU.

Improving circuit realization of known quantum algorithms by CAD techniques has benefits for quantum experimentalists. In this article, the problem of synthesizing a given function on a set of ancillea is addressed. The proposed approach benefits from extensive sharing of cofactors among cubes that appear on function outputs. Accordingly, it can be considered a multilevel logic optimization technique for reversible circuits. In particular, the suggested approach can efficiently implement any n -input, m -output lookup table (LUT) by a reversible circuit. This problem has interesting applications in the Shor's number-factoring algorithm and in quantum walk on sparse graphs. Simulation results reveal that the proposed cofactor-sharing synthesis algorithm has a significant impact on reducing the size of modular exponentiation circuits for Shor's quantum factoring algorithm, oracle circuits in quantum walk on sparse graphs, and the well-known MCNC benchmarks.

Smartphones consume a significant amount of power. Indeed, they can hardly provide a full day of use between charging operations even with a 2000 mAh battery. While power minimization and dynamic power management techniques have been heavily explored to improve the power efficiency of modules (processors, memory, display, GPS, etc.) inside a smartphone platform, there is one critical factor that is often overlooked: the power conversion efficiency of the power delivery network (PDN). This paper focuses on dc-dc converters, which play a pivotal role in the PDN of the smartphone platform. Starting from detailed models of the dc–dc converter designs, two optimization methods are presented: 1) static switch sizing to maximize the efficiency of a dc–dc converter under statistical loading profiles and 2) dynamic switch modulation to achieve the high efficiency enhancement under dynamically varying load conditions. To verify the efficacy of the optimization methods in actual smartphone platforms, this paper also presents a characterization procedure for the PDN. The procedure is as follows: 1) group the modules in the smartphone platform together and use profiling to estimate their average and peak power consumption levels and 2) build an equivalent dc–dc converter model for the power delivery path from the battery source to each group of modules and use linear regression to estimate the conversion efficiency of the corresponding equivalent converter. Experimental results demonstrate that the static switch sizing can achieve 6% power conversion efficiency enhancement, which translates to 19% reduction in power loss general usage of the smartphone. The dynamic switch modulation accomplishes similar improvement at the same condition, while also achieving high efficiency enhancement in various load conditions.

Partial shading is a serious obstacle to the effective utilization of photovoltaic (PV) systems since it can result in a significant degradation in the PV system output power. A PV system is organized as a series connection of PV modules, each module comprising a number of series-parallel connected PV cells. Backup PV cell employment and PV module reconfiguration techniques have been proposed to improve the performance of the PV system under the partial shading effects. However, these approaches are not very effective since they are costly in terms of their PV cell count and/or cell connectivity requirements. In contrast, this paper presents a cost-effective, reconfigurable PV module architecture with integrated switches in each PV cell. This paper also presents a dynamic programming algorithm to adaptively produce near-optimal reconfigurations of each PV module so as to maximize the PV system output power under any partial shading pattern. We implement a working prototype of reconfigurable PV module with 16 PV cells and confirm 45.2% output power level improvement. Using accurate PV cell models extracted from prototype measurement, we have demonstrated up to a factor of 2.36X output power improvement of a large-scale PV system comprised of three PV modules with 60 PV cells per module.

The oversampling requirement in a delta-sigma modulator (DSM) is considered one of the limiting factors toward its employment in current high-frequency applications, such as wireless software defined radio (SDR) systems. This paper advances that the critical requirement for DSMs is high-frequency processing and not a high-oversampling ratio. A single-bit semiparallel processing structure to accomplish the high-frequency processing is proposed in this paper. Using the suggested low-oversampling digital DSM architecture, high-speed, high-complexity computations, which are normally required for wireless applications, are executed simultaneously. This facilitates the design of embedded SDR multistandard transmitters using commercially available digital processors. The most favorable application of the proposed single-bit DSM is to build an radio frequency transmitter that includes a one-bit quantifier with two-level switching power amplifier for both high linearity and high efficiency. Performance analysis is carried out by using MATLAB simulations, which shows a reduction of the oversampling ratio by a factor of 16 (for a baseline oversampling ratio of 256) with the same signal-to-noise ratio (SNR). The proposed DSM is also implemented on a field-programmable gate array (FPGA) board and its performance is validated by using a code division multiple access signal. The bandwidth of the output signal is increased four times without increasing the processing frequency. Simultaneously, quality of the output signal remains the same but FPGA resource usage is increased by a factor of three.

In spite of extensive research it is still quite expensive to store electrical energy without converting it to a different form of energy. As of today, no single type of electrical energy storage (EES) element can fulfill all the desirable features of an ideal storage device, e.g., high-efficiency, high-power/energy capacity, low-cost, and long-cycle life. A hybrid EES system (HEES) consists of two or more heterogeneous EES elements, realizing the advantages of each EES element while hiding their weaknesses. HEES systems exhibit superior performance compared with homogeneous EES systems when appropriate charge allocation and replacement policies are developed and used. In addition, charge migration is mandatory because the optimal EES banks for charge allocation and replacement are in general different, and each EES bank has limited storage capacity. This paper formally describes the notion of charge migration efficiency and its optimization. We first define the charge migration architecture and the corresponding charge migration optimization problem. We provide a systematic solution for the single-source, single-destination charge migration problem considering the efficiency variation of the converters, the rate capacity and internal power loss of the storage element, the terminal voltage variation of the storage elements as a function of their state of charge, and so on. We also introduce the optimal solutions for both the time-constrained and -unconstrained versions of the charge migration problem formulations. Experimental results demonstrate significant charge migration efficiency improvement of up to 83.4%.

This work focuses on the load balancing problem for online service applications (which are response time-sensitive) considering a distributed cloud system comprised of geographically dispersed, heterogeneous datacenters. An offline solution based on force-directed scheduling is presented, which can determine the application placement for long periods of time. The solution is then extended to do online application placement and migration for geographically distributed datacenters based on predictions about the application lifetimes, workload intensities, dynamic energy prices, and renewable energy generation capacities at different datacenters in the cloud system. The simulation results demonstrate 27% to 40% improvement using the proposed algorithms with respect to the method that does not consider the geographical load balancing.

Improving the energy efficiency of cloud computing systems has become an important issue because the electric energy bill for 24/7 operation of these systems can be quite large. The focus of this paper is on the virtual machine (VM) consolidation in a cloud computing system as a way of lowering daily energy consumption of the system. In contrast to the existing works that assume resource demands of VMs are known and given as scalar variables, this paper treats these demands as random variables with known means and standard deviations. These random variables may be correlated with one another, and there are several kinds of resources which can be performance bottlenecks. Therefore, both the correlation and multiple resource type should be considered. The VM consolidation problem is then formulated as a multi-capacity stochastic bin packing problem. This problem is NP-hard, so we propose a heuristic method to solve the problem efficiently. The simulation results show that, in spite of its simplicity and scalability, the proposed method produces high quality solutions.

Emerging mobile systems integrate a lot of functionality into a small form factor with a small energy source in the form of rechargeable battery. This situation necessitates accurate estimation of the remaining energy in the battery such that user applications can be judicious on how they consume this scarce and precious resource. This paper thus focuses on estimating the remaining battery energy in Android OS-based mobile systems. This paper proposes to instrument the Android kernel in order to collect and report accurate subsystem activity values based on real-time profiling of the running applications. The activity information along with offline-constructed, regression-based power macro models for major subsystems in the smartphone yield the power dissipation estimate for the whole system. Next, while accounting for the rate-capacity effect in batteries, the total power dissipation data is translated into the battery's energy depletion rate, and subsequently, used to compute the battery's remaining lifetime based on its current state of charge information. Finally, this paper describes a novel application design framework, which considers the batterys state-of-charge (SOC), batterys energy depletion rate, and service quality of the target application. The benefits of the design framework are illustrated by examining an archetypical case, involving the design space exploration and optimization of a GPS-based application in an Android OS.

Hybrid electrical energy storage (HEES) systems are comprised of multiple banks of heterogeneous electrical energy storage (EES) elements with distinct properties. This paper defines and solves the problem of scheduling multiple charge migration tasks in HEES systems with the objective of minimizing the total energy drawn from the source banks. The solution approach consists of two steps: (i) Finding the best charging current profile and voltage level setting for the Charge Transfer Interconnect (CTI) bus for each charge migration task, and (ii) Merging and scheduling the charge migration tasks. Experimental results demonstrate improvements of up to 32.2% in the charge migration efficiency compared to baseline setups in an example HEES system.

This paper is the first to present a comprehensive analysis of the profitability of the hybrid electrical energy storage (HEES) systems while further providing a HEES design and control optimization framework to maximize the total return on investment (ROI). The solution consists of two steps: (i) Derivation of an optimal HEES management policy to maximize the daily energy cost saving and (ii) Optimal design of the HEES system to maximize the amortized annual profit under budget and system volume constraints. We consider a HEES system comprised of lead-acid and Li-ion batteries for a case study. The optimal HEES system achieves an annual ROI of up to 60% higher than a lead-acid battery-only system (Li-ion battery-only) system.

This work focuses on the load balancing and scheduling problem for batch jobs considering a cloud system comprised of geographically dispersed, heterogeneous datacenters. Each batch job is modeled using a directed acyclic graph of heterogeneous tasks. Load balancing and scheduling of batch jobs with loose deadlines results in operational cost reduction in the cloud system due to availability of renewable energy sources in datacenters' site and time of use dependent energy pricing in utility companies. A solution for load balancing and scheduling problem based on the force-directed scheduling approach is presented that considers the online application workload and limited resource and peak power capacity in each datacenter. The simulation results demonstrate significant operational cost decrease (up to 40%) using the proposed algorithm with respect to a greedy solution.

This paper presents LEQA, a fast latency estimation tool for evaluating the performance of a quantum algorithm mapped to a quantum fabric. The actual quantum algorithm latency can be computed by performing detailed scheduling, placement and routing of the quantum instructions and qubits in a quantum operation dependency graph on a quantum circuit fabric. This is, however, a very expensive proposition that requires large amounts of processing time. Instead, LEQA, which is based on computing the neighborhood population counts of qubits, can produce estimates of the circuit latency with good accuracy (i.e., an average of less than 3% error) with up to two orders of magnitude speedup for mid-size benchmarks. This speedup is expected to increase superlinearly as a function of circuit size (operation count).

Optimization of the interaction distance between qubits to map a quantum circuit into one-dimensional quantum architectures is addressed. The problem is formulated as the Minimum Linear Arrangement (MinLA) problem. To achieve this, an interaction graph is constructed for a given circuit, and multiple instances of the MinLA problem for selected subcircuits of the initial circuit are formulated and solved. In addition, a lookahead technique is applied to improve the cost of the proposed solution which examines different subcircuit candidates. Experiments on quantum circuits for quantum Fourier transform and reversible benchmarks show the effectiveness of the approach.

In this paper, we propose a scheme for reducing the latency of packets transmitted via on-chip interconnect network in MultiProcessor Systems on Chips (MPSoCs). In this scheme, the network architecture separates the packets transmitted to near destinations from those transmitted to distant ones by using two network layers. These two layers are realized by dividing the channel width among the cores. The optimum ratio for the channel width division is a function of relative significances of the two types of communications. Simulation results indicate that for non-uniform traffic constituting of more than 30 percent local traffic, the proposed network, on average provides 64% and 70% improvement over the conventional one in terms of average network latency and Energy-Delay product (EDP), respectively. Also, for uniform and NED traffic patterns, by adjusting the number of hops between local nodes to include approximately 55 percent of total communications in local ones, the proposed architecture provides the latency reduction of 50%.

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Improving circuit realization of known quantum algorithms by CAD techniques has benefits for quantum experimentalists. In this paper, we address the problem of synthesizing a given k-input, m-output lookup table (LUT) by a reversible circuit. This problem has interesting applications in the famous Shor's number-factoring algorithm and in quantum walk on sparse graphs. For LUT synthesis, our approach targets the number of control lines in multiple-control Toffoli gates to reduce synthesis cost. To achieve this, we propose a multi-level optimization technique for reversible circuits to benefit from shared cofactors. To reuse output qubits and/or zero-initialized ancillae, we un-compute intermediate cofactors. Our experiments reveal that the proposed LUT synthesis has a significant impact on reducing the size of modular exponentiation circuits for Shor's quantum factoring algorithm, oracle circuits in quantum walk on sparse graphs, and the well-known MCNC benchmarks.

Photovoltaic (PV) systems are often subject to partial shading that significantly degrades the output power of the whole systems. Reconfiguration methods have been proposed to adaptively change the PV panel configuration according to the current partial shading pattern. The reconfigurable PV panel architecture integrates every PV cell with three programmable switches to facilitate the PV panel reconfiguration. The additional switches, however, increase the capital cost of the PV system. In this paper, we group a number of PV cells into a PV macro-cell, and the PV panel reconfiguration only changes the connections between adjacent PV macro-cells. The size and internal structure (i.e., the series-parallel connection of PV cells) of all PV macro-cells are the same and will not be changed after PV system installation in the field. Determining the optimal size of the PV macro-cell is the result of a trade-off between the decreased PV system capital cost and enhanced PV system performance. A larger PV macro-cell reduces the cost overhead whereas a smaller PV macro-cell achieves better performance. In this paper, we set out to calculate the optimal size of the PV macro-cells such that the maximum system performance can be achieved subject to an overall system cost limitation. This “design” problem is solved using an efficient search algorithm. In addition, we provide for in-field reconfigurability of the PV panel by enabling formation of series-connected groups of parallel-connected macro-cells. We ensure maximum output power for the PV system in response to any incurring partial shading pattern. This “architecture optimization” problem is solved using dynamic programming.

Integrating residential photovoltaic (PV) power generation and electrical energy storage (EES) systems into the Smart Grid is an effective way of utilizing renewable power and reducing the consumption of fossil fuels. This has become a particularly interesting problem with the introduction of dynamic electricity energy pricing models since electricity consumers can use their PV-based energy generation and EES systems for peak shaving on their power demand profile from the grid, and thereby, minimize their electricity bill. Due to the characteristics of a realistic electricity price function and the energy storage capacity limitation, the control algorithm for a residential EES system should accurately account for various energy loss components during operation. Hybrid electrical energy storage (HEES) systems are proposed to exploit the strengths of each type of EES element and hide its weaknesses so as to achieve a combination of performance metrics that is superior to those of any of its individual EES components. This paper introduces the problem of how best to utilize a HEES system for a residential Smart Grid user equipped with PV power generation facilities. The optimal control algorithm for the HEES system is developed, which aims at minimization of the total electricity cost over a billing period under a general electricity energy price function. The proposed algorithm is based on dynamic programming and has polynomial time complexity. Experimental results demonstrate that the proposed HEES system and optimal control algorithm achieves 73.9% average profit enhancement over baseline homogeneous EES systems.

Cycle life of a battery largely varies according to the battery operating conditions, especially the battery temperature. In particular, batteries age much faster at high temperature. Extensive experiments have shown that the battery temperature varies dramatically during continuous charge or discharge process. This paper introduces a forced convection cooling technique for the batteries that power a portable system. Since the cooling fan is also powered by the same battery, it is critical to develop a highly effective, low power-consuming solution. In addition, there is a fundamental tradeoff between the service time of a battery equipped with fans and the cycle life of the same battery. In particular, as the fan speed is increased, the power dissipated by the fan goes up and hence the full charge capacity of the battery is lost at a faster rate, but at the same time, the battery temperature remains lower and hence the battery longevity increases. This is the first work that formulates the adaptive thermal management problem for batteries (ATMB) in portable systems and provides a systematic solution for it. A hierarchical algorithm combining reinforcement learning at the lower level and dynamic programming at the upper level is proposed to derive the ATMB policy.

The finite and rather small battery energy capacity in today's mobile devices has limited the functionality that can be integrated into these platforms or the performance and quality of applications that can be delivered to the users. In the last few years, there is a trend toward offloading certain computation-intensive and latency-tolerant local applications and service requests to a mobile cloud computing (MCC) system so as to save the precious battery life while providing the services requested by the users. Each mobile application can be thought of as a sequence of tasks that are executed locally or remotely. In this paper, the problem of optimal task dispatch, transmission, and execution onto the MCC system is considered. To achieve a good balance between the application execution time and power consumption, dynamic voltage and frequency scaling (DVFS) is applied to the local processor in the mobile device, while the transmitter can choose among multiple modulation schemes and bit rates. The rate capacity effect of a battery and power conversion losses in the mobile device are also accounted for so as to have a more realistic model of the remaining battery life. The mobile device is modeled as a semi-Markov decision process (SMDP) and the optimization problem to set the DVFS level and the transmission rate is effectively solved by linear programming combined with a one-dimensional heuristic search. Experimental results show that the proposed algorithm consistently outperforms some baseline algorithms.

Soft-edge flip-flop based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by allowing opportunistic time borrowing. The application of this technique to near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections and substrate temperature changes. This paper thus addresses the issue of variability-aware design of the energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes. Precisely, this goal is achieved by deriving the optimal delay line configuration in the soft-edge flip-flops in the near-threshold and the super-threshold operations regimes. The key is to ensure that the same transistor sizes result in effective operation of the delay lines (and hence appropriate settings of the transparency window size) in both operation regimes under the process induced variations. Experimental results demonstrate the efficacy of the proposed solution.

FinFET has been proposed as an alternative for bulk CMOS in current and future technology nodes due to more effective channel control, reduced random dopant fluctuation, high ON/OFF current ratio, lower energy consumption, etc. Key characteristics of FinFET operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper first introduces an analytical transregional FinFET model with high accuracy in both sub- and near-threshold regimes. Next, the paper extends the well-known and widely-adopted logical effort delay calculation and optimization method to FinFET circuits operating in multiple voltage (sub/near/super-threshold) regimes. More specifically, a joint optimization of gate sizing and adaptive independent gate control is presented and solved in order to minimize the delay of FinFET circuits operating in multiple voltage regimes. Experimental results on a 32nm Predictive Technology Model for FinFET demonstrate the effectiveness of the proposed logical effort-based delay optimization framework.

The thermal management is a crucial design problem for mobile devices because it greatly affects not only the device reliability, but also the leakage energy consumption. Conventional dynamic thermal management (DTM) techniques work well for the computer systems. However, due to the limitation of the physical space in mobile devices, the thermal coupling effect between the major heat generation components, such as the application processor (AP) and the battery, plays an important role in determining the temperature inside the mobile device package. Due to this effect, the thermal behavior of one part is no longer independent of the other, but is affected by the temperature of other parts. This is the first work that quantitatively characterizes the thermal coupling between the battery and AP and presents a predictive DTM for mobile devices considering this effect. Simulation results show that the proposed DTM method significantly reduces the thermal violations for the target mobile devices.

Operating circuits in the ultra-low voltage regime results in significantly lower power consumption but can also degrade the circuit performance. In addition, it leads to higher sensitivity to various sources of variability in VLSI circuits. This paper extends the current source modeling (CSM) technique, which has successfully been applied to VLSI circuits to achieve very high accuracy in timing analysis, to the near-threshold voltage regime. In particular, it shows how to combine non-linear analytical models and low-dimensionality CSM lookup tables to simultaneously achieve modeling accuracy, space and time efficiency, when performing CSM-based timing analysis of VLSI circuits operating in near-threshold regime and subject to process variability effects.

One of the biggest stumbling blocks for the successful continuation of the Moore's law is the substrate temperature of VLSI circuits. Thermoelectric cooling is one of the promising cooling methods to combat high die temperatures. This method provides key benefits such as compactness, high reliability, and exceptionally high heat-pumping capability. On the other hand, even with the recent advances in the fabrication techniques, thermoelectric coolers (TECs) are suffering from a poor coefficient of performance (COP), which denotes the ratio of heat removed per second to the power needed to drive the TEC, is rather low. In this paper, different techniques to improve the performance of a TEC, when it is embedded inside a processor package, are investigated. In particular, first the COP of TECs is reformulated to consider the leakage power, which is exponentially dependent on the die temperature. Next it is demonstrated that the TEC driving current that yields the maximum decrease in the die temperature is quite different from the one that runs the TEC in its highest COP state. Based on these observations, a platform-dependent, leakage-aware cooling policy in which the TEC driving current is set based on the target specs (high-performance vs. low-power) and actual conditions of the chip (emergency vs. preventive thermal management) is proposed. Experimental results show that, with this policy, one can reduce the temperature of chip hotspots while achieving a high COP.

Energy harvesting is a promising technique to overcome the limitation imposed by the finite energy capacity of batteries in conventional battery-powered embedded systems. In particular, the question of how one can achieve full energy autonomy (i.e., perpetual, battery-free operation) of a real-time embedded system with an energy harvesting capability (RTES-EH) by applying a global control strategy is investigated. The energy harvesting module is comprised of a Photovoltaic (PV) panel for harvesting energy and a supercapacitor for storing any excess energy. The global controller performs optimal operating point tracking for the PV panel, state-of-charge management for the supercapacitor, and energy-harvesting-aware real-time task scheduling with dynamic voltage and frequency scaling (DVFS) in the embedded load device. The controller, which accounts for dynamic V-I characteristics of the PV panel, terminal voltage variation and self-leakage of the supercapacitor, and power losses in voltage converters, employs a cascaded feedback control structure with an inner control loop determining the V-I operating point of the PV panel and an outer supervisory control loop performing real-time task scheduling and setting the voltage and frequency level in the embedded load device (to keep the state-of-charge of the supercapacitor in a desirable range). Experimental results show that the proposed global controller lowers the task drop rate in a RTES-EH by up to 60% compared with baseline controller within the same service time.

Battery life of high-end smartphones and tablet PCs is becoming more and more important due to the gap between the rapid increase in power requirements of the electronic components and the slow increase in energy storage capacity of Li-ion batteries. Energy harvesting, on the other hand, is a promising technique that can prolong the battery life without compromising the users' experience with the devices and potentially without the necessity to have access to a wall AC outlet. Such energy harvesting products are available on the market today, but most of them are equipped with only a large battery pack, which exhibits poor capacity utilization during solar energy harvesting. In this paper, we propose and demonstrate that using a supercapacitor instead of a large capacity battery can be beneficial in terms of improving the charging efficiency, and thereby, significantly reducing the charging time. However, this is not a trivial task and gives rise to many problems associated with charging the supercapacitor via the USB charging port. We analyze the USB charging standard and commercial USB charger designs in smartphones to formulate an energy efficiency optimization problem and propose a dynamic programming-based online algorithm to solve the aforesaid problem. Experimental results show up to 34.5% of charging efficiency improvement compared with commercial solar charger designs.

State-of-the-art electrical energy storage (EES) systems are mainly homogeneous, i.e., they consist of a single type of EES elements. None of the existing EES elements is capable of simultaneously fulfilling all the desired features of an ideal EES system, e.g., high charge/discharge efficiency, high energy density, low cost per unit capacity, long cycle life. A novel technology, i.e., a hybrid EES system that employs heterogeneous EES elements organized in a hierarchy of storage banks and linked by appropriate charge transfer interconnects, has shown great promise in overcoming the aforesaid limitations of conventional EES systems. However, the widespread adoption/deployment of hybrid EES systems is hampered by lack of a hybrid EES system simulator. This paper thus presents SIMES, a powerful and scalable simulator for hybrid EES systems, which provides fast and accurate system simulations, while accounting for key characteristics of various EES elements, power converters, charge transfer interconnect schemes, etc. Experimental results on two different applications (one targeting load shifting for households, the other related to battery rate capacity effect minimization in portable electronic devices) demonstrate the value and usefulness of SIMES for designing energy-aware facilities and products.

Due to prohibitive cost of data center setup and maintenance, many small-scale businesses rely on hosting centers to provide the cloud infrastructure to run their workloads. Hosting centers host services of the clients on their behalf and guarantee quality of service as defined by service level agreements (SLAs.) To reduce energy consumption and to maximize profit it is critical to optimally allocate resources to meet client SLAs. Optimal allocation is a nontrivial task due to 1) resource heterogeneity where energy consumption of a client task varies depending on the allocated resources 2) lack of energy proportionality where energy cost for a task varies based on server utilization. In this paper, we introduce a generalized Network Flow-based Resource Allocation framework, called NFRA, for energy minimization and profit maximization. NFRA provides a unified framework to model profit maximization under a wide range of SLAs. We will demonstrate the simplicity of this unified framework by deriving optimal resource allocations for three different SLAs. We derive workload demands and server energy consumption data from SPECWeb2009 benchmark results to demonstrate the efficiency of NFRA framework.

With the CMOS transistors being scaled to 28 nm and lower, negative bias temperature instability (NBTI) has become a major concern due to its impact on pMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of CMOS flip-flops. First, it is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing codependent setup and hold time contours of the flip-flops. Third, a multicorner optimization technique, which relies on mathematical programming to find the best transistor sizes, is presented to minimize the energy-delay product of the flip-flops under the NBTI effect. Finally, the proposed optimization technique is applied to true single-phase clock flip-flops to demonstrate its effectiveness.

Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. Nevertheless, existing DVFS transition overhead models suffer from significant inaccuracies; for example, by incorrectly accounting for the effect of DC-DC converters, frequency synthesizers, voltage, and frequency change policies on energy losses incurred during mode transitions. Incorrect and/or inaccurate DVFS transition overhead models prevent one from determining the precise break-even time and thus forfeit some of the energy saving that is ideally achievable. This paper introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the DVFS transition overhead including the underclocking-related losses in a DVFS-enabled microprocessor, additional inductor IR losses, and power losses due to discontinuous-mode DC-DC conversion. We report the transition overheads for a desktop, a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high-level DVFS schedulers.

Organic light emitting diode (OLED) display is a self-illuminating device that is supposed to be more power efficient than liquid crystal display (LCD). However, OLED display panels consume as much power as LCD panels due to total internal reflection. As the power consumption of the OLED panel depends on the pixel colors, most of the earlier power saving methods alter the pixel colors. In practice, such OLED power saving techniques can hardly accommodate photo viewers and movie players. This paper introduces the first OLED power saving technique that dynamically changes the supply voltage of the panel. Reduced supply voltage results in both power saving and decreased pixel luminance, but model-based color correction restores the decreased luminance with minimum color distortion. This technique is similar to dynamic backlight scaling of LCDs but is based on the unique characteristics of the OLED drivers. We provide an online color compensation algorithm using the luminance histogram. Luminance quantization in the histogram also achieves resource minimization. We develop a prototype and demonstrate the proposed OLED dynamic voltage scaling (DVS). Experimental result shows that the proposed OLED DVS saves up to 74.7% of the display power for the still images and up to 35.9% for movie clips.

A hybrid electrical energy storage (HEES) system consists of multiple banks of heterogeneous electrical energy storage (EES) elements placed between a power source and some load devices and providing charge storage and retrieval functions. For an HEES system to perform its desired functions of 1) reducing electricity costs by storing electricity obtained from the power grid at off-peak times when its price is lower, for use at peak times instead of electricity that must be bought then at higher prices, and 2) alleviating problems, such as excessive power fluctuation and undependable power supply, which are associated with the use of large amounts of renewable energy on the grid, appropriate charge management policies must be developed in order to efficiently store and retrieve electrical energy while attaining performance metrics that are close to the respective best values across the constituent EES banks in the HEES system. This paper is the first to formally describe the global charge allocation problem in HEES systems, namely, distributing a specified level of incoming power to a subset of destination EES banks so that maximum charge allocation efficiency is achieved. The problem is formulated as a mixed integer nonlinear program with the objective function set to the global charge allocation efficiency and the constraints capturing key requirements and features of the system such as the energy conservation law, power conversion losses in the chargers, the rate capacity, and self-discharge effects in the EES elements. A rigorous algorithm is provided to obtain near-optimal charge allocation efficiency under a daily charge allocation schedule. A photovoltaic array is used as an example of the power source for the charge allocation process and a heuristic is provided to predict the solar radiation level with a high accuracy. Simulation results using this photovoltaic cell array and a representative HEES system demonstrate up to 25% gain in the charge allocation efficiency by employing the proposed algorithm.

Carbon nanotube field effect transistors (CNFETs) show great promise as extensions to silicon CMOS. However, imperfections, which are mainly related to carbon nanotubes (CNTs) growth process, result in metallic and nonuniform CNTs leading to significant functional yield reduction. This paper presents a comprehensive technique for statistical functional yield estimation and enhancement of CNFET-based VLSI circuits. Based on experimental data extracted from aligned CNTs, we propose a compact statistical model to estimate the failure probability of a CNFET. Using the proposed failure model, we show that enhancing the CNT synthesis process alone cannot achieve acceptable functional yield for upcoming CNFET-based VLSI circuits. We propose a technique which is based on replacing each transistor by series-parallel transistor structures to reduce the failure probability of CNFETs in the presence of metallic and nonuniform CNTs. The technique is adapted to use single directional independence, which is inherent in aligned CNTs, to enhance the functional yield as validated by theoretical analysis and simulation results. Tradeoffs between failure probability reduction and design overheads such as area and current drive are explored. As demonstrated by extensive simulation results, the proposed technique achieves 80% functional yield in CNFET technology at the cost of 7.5X area and 34% current drive overheads if the CNT density and the fraction of semiconducting CNTs are improved to 200 CNTs per μm and 99.99%, respectively.

By utilizing Virtual Machines (VM) and doing server consolidation in a datacenter, a cloud provider can reduce the total energy consumption for servicing his clients with little performance degradation. In particular, the cloud provider can take advantage of dissimilar workloads and by assigning these workloads to the same server, can utilize fewer active servers to service his clients. Placing multiple copies of a VM on different servers and distributing the incoming requests among these VM copies can reduce the resource requirement for each VM copy and help the cloud provider utilize the servers more efficiently. In this paper, the problem of energy-efficient VM placement in a cloud computing system is solved. Precisely, we present an approach that first creates multiple copies of VMs and then uses dynamic programming and local search to place these copies on the physical servers. Simulation results show that the proposed algorithm reduces the total energy consumption by up to 20% with respect to previous work.

The focus of this paper is on energy-aware resource management in a cloud computing system. Much of the existing work assumes that the resource requirements for various applications are known and given as scalar values. However, it is very difficult to know the exact resource requirements, and thus, it is more appropriate to treat resource requirements for applications as random variables with known characteristics. For a desired quality of service, the required total resource amount can then be estimated as a function of the means and standard deviations of these random variables. Inspired by the modern portfolio theory, this paper presents algorithms that minimize the total amount of estimated resource in the system. A source of difficulty is that some of the aforesaid random variables may be correlated with each other. The proposed algorithms effectively deal with correlated applications. Experimental results show that, in spite of its simplicity and scalability, the proposed solution outperforms the well-known heuristics i.e., first fit decreasing (FFD) and best fit decreasing (BFD) by an average of 10% while having a low execution time.

Hybrid electrical energy storage (HEES) systems are composed of multiple banks of heterogeneous electrical energy storage (EES) elements with distinctive properties. Charge replacement in a HEES system (i.e., dynamic assignment of load demands to EES banks) is one of the key operations in the system. This paper formally describes the global charge replacement (GCR) optimization problem and provides an algorithm to find the near-optimal GCR control policy. The optimization problem is formulated as a mixed-integer nonlinear programming problem, where the objective function is the charge replacement efficiency. The constraints account for the energy conservation law, efficiency of the charger/converter, the rate capacity effect, and self-discharge rates plus internal resistances of the EES element arrays. The near-optimal solution to this problem is obtained while considering the state of charges (SoCs) of the EES element arrays, characteristics of the load devices, and estimates of energy contributions by the EES element arrays. Experimental results demonstrate significant improvements in the charge replacement efficiency in an example HEES system comprised of banks of battery and supercapacitor elements with a high-power pulsed military radio transceiver as the load device.

Cloud computing systems (or hosting datacenters) have attracted a lot of attention in recent years. Utility computing, reliable data storage, and infrastructure-independent computing are example applications of such systems. Electrical energy cost of a cloud computing system is a strong function of the consolidation and migration techniques used to assign incoming clients to existing servers. Moreover, each client typically has a service level agreement (SLA), which specifies constraints on performance and/or quality of service that it receives from the system. These constraints result in a basic trade-off between the total energy cost and client satisfaction in the system. In this paper, a resource allocation problem is considered that aims to minimize the total energy cost of cloud computing system while meeting the specified client-level SLAs in a probabilistic sense. The cloud computing system pays penalty for the percentage of a client's requests that do not meet a specified upper bound on their service time. An efficient heuristic algorithm based on convex optimization and dynamic programming is presented to solve the aforesaid resource allocation problem. Simulation results demonstrate the effectiveness of the proposed algorithm compared to previous work.

A hybrid electrical energy storage (HEES) system that consists of multiple, heterogeneous electrical energy storage (EES) elements is a promising solution to achieve a cost-effective EES system because no storage element has ideal characteristics. The state-of-the-art HEES systems are based on a shared-bus charge transfer interconnect (CTI) architecture. Consequently, they are quite limited in scalability which is a function of the number of EES banks. This paper is the first introduction of a HEES system based on a networked CTI architecture, which is highly scalable and is capable of accommodating multiple, concurrent charge transfers. The paper starts by presenting a router architecture for the networked CTI and an effective on-line routing algorithm for multiple charge transfers. In the proposed algorithm, negotiated congestion (NC) routing for multiple charge transfers is performed and any lack of routing resources is addressed by merging two or more charge transfers while maximizing the overall energy efficiency by setting the optimal voltage level for the shared CTI. Examples of the proposed networked CTI are presented and the efficacy of the routing algorithm is demonstrated on a mesh-grid networked CTI.

Partial shading is a serious obstacle to effective utilization of photovoltaic (PV) systems since it can result in significant output power degradation for the system. A PV system is organized as a series connection of PV modules, each module comprising of a number of series-parallel connected cells. This paper presents modified PV cell structures with integrated switches, imbalanced cell connection topologies for PV modules, and a dynamic programming algorithm to produce near-optimal reconfigurations of each PV module with the goal of maximizing the system output power level under any partial shading patterns. Through simulations, we have demonstrated up to a factor of 2.3X improvement in the output power level of a PV system comprised of 3 PV modules with 60 PV cells per module.

Quantum computers are exponentially faster than their classical counterparts in terms of solving some specific, but important problems. The biggest challenge in realizing a quantum computing system is the environmental noise. One way to decrease the effect of noise (and hence, reduce the overhead of building fault tolerant quantum circuits) is to reduce the latency of the quantum circuit that runs on a quantum circuit. In this paper, a novel algorithm is presented for scheduling, placement, and routing of a quantum algorithm, which is to be realized on a target quantum circuit fabric technology. This algorithm, and the accompanying software tool, advances state-of-the-art in quantum CAD methodologies and methods while considering key characteristics and constraints of the ion-trap quantum circuit fabric. Experimental results show that the presented tool improves results of the previous tool by about 41%.

In this paper, we present an architecture-level approach to mitigate the impact of process variations on extended instruction set architectures (ISAs). The proposed architecture adds one extra cycle to execute custom instructions (CIs) that violate the maximum allowed propagation delay due to the process variations. Using this method, the parametric yield of manufactured chips will greatly improve. The cost is an increase in the cycle latency of some of the CIs, and hence, a slight performance degradation for the extensible processor architectures. To minimize the performance penalty of the proposed approach, we introduce a new merit function for selecting the CIs during the selection phase of the ISA extension design flow. To evaluate the efficacy of the new selection method, we compare the extended ISAs obtained by this method with those selected based on the worst-case delay. Simulation results reveal that a speedup improvement of about 18% may be obtained by the proposed selection method. Also, by using the proposed merit function, the proposed architecture can improve the speedup about 20.7%.

Hybrid electrical energy storage (HEES) systems consist of multiple banks of heterogeneous electrical energy storage (EES) elements that are connected to each other through the Charge Transfer Interconnect. A HEES system is capable of providing an electrical energy storage means with very high performance by taking advantage of the strengths (while hiding the weaknesses) of individual EES elements used in the system. Charge migration is an operation by which electrical energy is transferred from a group of source EES elements to a group of destination EES elements. It is a necessary process to improve the HEES system's storage efficiency and its responsiveness to load demand changes. This paper is the first to formally describe a more general charge migration problem, involving multiple sources and multiple destinations. The multiple-source, multiple-destination charge migration optimization problem is formulated as a nonlinear programming (NLP) problem where the goal is to deliver a fixed amount of energy to the destination banks while maximizing the overall charge migration efficiency and not depleting the available energy resource of the source banks by more than a given percentage. The constraints for the optimization problem are the energy conservation relation and charging current constraints to ensure that charge migration will meet a given deadline. The formulation correctly accounts for the efficiency of chargers, the rate capacity effect of batteries, self-discharge currents and internal resistances of EES elements, as well as the terminal voltage variation of EES elements as a function of their state of charges (SoC's). An efficient algorithm to find a near-optimal migration control policy by effectively solving the above NLP optimization problem as a series of quasi-convex programming problems is presented. Experimental results show significant gain in migration efficiency up to 35%.

This paper is the first to present an efficient charge management algorithm focusing on extending the cycle life of battery elements in hybrid electrical energy storage (HEES) systems while simultaneously improving the overall cycle efficiency. In particular, it proposes to apply a crossover filter to the power source and load profiles. The goal of this filtering technique is to allow the battery banks to stably (i.e., with low variation) receive energy from the power source and/or provide energy to the load device, while leaving the spiky (i.e., with high variation) power supply or demand to be dealt with by the supercapacitor banks. To maximize the HEES system cycle efficiency, a mathematical problem is formulated and solved to determine the optimal charging/discharging current profiles and charge transfer interconnect voltage, taking into account the power loss of the EES elements and power converters. To minimize the state of health (SoH) degradation of the battery array in the HEES system, we make use of two facts: the SoH of battery is better maintained if (i) the SoC swing is smaller, and (ii) the same SoC swing occurs at lower average SoC. Now then using the supercapacitor bank to deal with the high-frequency component of the power supply or demand, we can reduce the SoC swing for the battery array and lower the SoC of the array. A secondary helpful effect is that, for fixed and given amount of energy delivered to the load device, an improvement in the overall charge cycle efficiency of the HEES system translates into a further reduction in both the average SoC and the SoC swing of the battery array. The proposed charge management algorithm for a Li-ion battery - supercapacitor bank HEES system is simulated and compared to a homogeneous EES system comprised of Li-ion batteries only. Experimental results show significant performance enhancements for the HEES system, an increase of up to 21.9% and 4.82x in terms of the cycle efficiency and cycle life, respectively.

Photovoltaic energy harvesting systems (PV systems) are subject to PV cell faults, which decrease the efficiency of PV systems and even shorten the PV system lifespan. Manual PV cell fault detection and elimination are expensive and nearly impossible for remote PV systems, e.g., PV systems on satellites. Therefore, online fault detection techniques and fault tolerance solutions are needed that can detect and tolerate PV cell faults without manual intervention. In this work, we present an online fault detection and tolerance technique for remote PV systems, which is capable of dynamically locating faulty PV cells and tolerating PV cell faults. More precisely, we present a modified PV panel structure and an efficient algorithm for our online fault detection and tolerance. Our fault detection and tolerance technique reduces output power degradation due to PV cell faults in a PV system by up to 81.31%.

A modern smartphone or tablet-PC is typically equipped a high-resolution and large-size display, which is a primary power consumer. In spite of the relatively high power efficiency of organic light emitting diode (OLED) displays, the integrated display sub-system exhibits low energy efficiency due to power losses in the battery and the boost voltage conversion. In this paper, we formulize the system energy efficiency in terms of the battery internal losses as well the converter efficiency considering the OLED power supply condition. We also analyze the effect of recently introduced dynamic (driver) supply voltage scaling technique for OLED displays on the overall system efficiency based on the system-level power profiling result. We introduce the optimal battery setup for different sizes and resolutions of the OLED display for modern smartphones and tablet-PCs.

Power dissipation and die temperature have become key performance limiters in today's high-performance Chip Multiprocessors (CMPs.) Dynamic power management solutions have been proposed to manage resources in a CMP based on the measured power dissipation, performance, and die temperature of processing cores. In this paper, we develop a robust framework for power and thermal management of heterogeneous CMPs subject to variability and uncertainty in system parameters. More precisely, we first model and formulate the problem of maximizing the task throughput of a heterogeneous CMP (a.k.a., asymmetric multi-core architecture) subject to a total power budget and a per-core temperature limit. Next we develop a solution framework, called Variation-aware Power/Thermal Manager (VPTM), which is a hierarchical dynamic power and thermal management solution targeting heterogeneous CMP architectures. VPTM utilizes dynamic voltage and frequency scaling (DVFS) and core consolidation techniques to control the core power consumptions, which implicitly regulate the core temperatures. An algorithm is proposed for core consolidation and application assignment, and a convex program is formulated and solved to produce optimal DVFS settings. Finally, a feedback controller is employed to compensate for variations in key system parameters at runtime. Experimental results show highly promising performance improvements for VPTM compared to the state-of-the-art techniques.

Hot carrier injection (HCI) effect is one of the major reliability concerns in VLSI circuits. This paper presents a scalable reliability simulation flow, including a logic cell characterization method and an efficient full chip simulation method, to analyze the HCI-induced transistor aging with a fast run time and high accuracy. The transistor-level HCI effect is modeled based on the Reaction-Diffusion (R-D) framework. The gate-level HCI impact characterization method combines HSpice simulation and piecewise linear curve fitting. The proposed characterization method reveals that the HCI effect on some transistors is much more significant than the others according to the logic cell structure. Additionally, during the circuit simulation, pertinent transitions are identified and all cells in the circuit are classified into two groups: critical and non-critical. The proposed method reduces the simulation time while maintaining high accuracy by applying fine granularity simulation time steps to the critical cells and coarse granularity ones to the non-critical cells in the circuit.

Dynamic power management (DPM) in battery-powered mobile systems attempts to achieve higher energy efficiency by selectively setting idle components to a sleep state. However, re-activating these components at a later time consumes a large amount of energy, which means that it will create a significant power draw from the battery supply in the system. This is known as the energy overhead of the “wakeup” operation. We start from the observation that, due to the rate capacity effect in Li-ion batteries which are commonly used to power mobile systems, the actual energy overhead is in fact larger than previously thought. Next we present a model-free reinforcement learning (RL) approach for an adaptive DPM framework in systems with bursty workloads, using a hybrid power supply comprised of Li-ion batteries and supercapacitors. Simulation results show that our technique enhances power efficiency by up to 9% compared to a battery-only power supply. Our RL-based DPM approach also achieves a much lower energy-delay product compared to a previously reported expert-based learning approach.

The focus of this paper is on dynamic power management in virtualized multi-core server systems. The paper starts by analyzing the effect of virtualization and CPU consolidation on power dissipation and performance (latency) of such systems, and concludes by presenting two new CPU consolidation algorithms for multi-core servers. The paper also reports an extensive set of experimental results founded on a realistic multi-core server system setup and well-developed benchmarks, i.e., SPEC2K and SPECWeb2009 and obtained through hardware measurements.

Modern smartphones consume significant power and can hardly provide a full day's use between charging operations even with a 2000 mAh battery. This is in spite of many power management techniques being employed in the smartphones. This paper starts from the observation that modern smartphones waste a significant amount of the battery's stored energy during power conversion from the 3.7V output of a Li-Ion battery cell to different voltage levels needed to power various modules in a smartphone (processors, memory, display, GPS, etc.) Indeed the power conversion efficiency from the battery source to point of use in the smart phone has on average of only 60-75% efficiency. The approach taken to reduce this energy waste in smartphones is to (i) profile the power consumption of each module under different operating scenarios, (ii) build an equivalent DC-DC converter model for each smartphone module and estimate its power conversion efficiency, and (iii) change the parameters of the actual converters in the smartphone to improve the equivalent power conversion efficiencies for all modules. Experimental results demonstrate that we can achieve 6% to 15% power conversion efficiency enhancement, which translates to up to 30% reduction in the power losses incurred during power conversion in smartphones.

Photovoltaic (PV) power generation systems are one of the most promising renewable power sources to reduce carbon footprint. Grid-connected PV power systems do not generally have a battery to store the excess charge. However, due to severe imbalance between the peak PV power generation and peak load demand, battery-less Grid-connected PV systems are much less effective for the purpose of power generation and demand mismatch mitigation. Grid-connected PV systems equipped with a battery indeed require elaborate management. This is the first paper that introduces a systematic battery management optimization that accommodates arbitrary electricity billing policies. We formulate an optimization framework to determine the battery charging current from the Grid and PV array taking into account the limited battery capacity, power converter efficiency, battery's internal resistance and rate capacity effect, and maximum power tracking of the PV array. Experimental results show that the proposed algorithm effectively reduces the electricity bill by as much as 28% when compared with previous state-of-the-art battery management policies.

Photovoltaic (PV) energy harvesting system is a promising energy source for battery replenishment in hybrid electric vehicles (HEVs.) The PV cell array is installed on different parts of a vehicle body such as the engine hood, door panels, and the roof panel. Non-uniformity of the solar irradiance and temperature on the PV cell array is, however, a serious obstacle to efficient utilization of the PV system in HEVs because such variation, if not managed properly, can result in a significant degradation in the overall output power level of the PV system. This paper presents a dynamic PV array reconfiguration technique with structural support and a dynamic programming-based algorithm with polynomial time complexity to produce the near-optimal reconfiguration of the PV array on the HEV. The goal of this technique is to maximize the PV system output power under any solar irradiance and temperature distribution on the PV array. We demonstrate up to 6X improvement in the output power of a PV system against a conventional fixed configuration PV system.

We propose an accurate model to describe the I–V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor (MOSFET) in the linear and saturation regions for fast analytical calculation of the current. The model is based on the BSIM3v3 model. Instead of using constant threshold voltage and early voltage, as is assumed in the BSIM3v3 model, we define these voltages as functions of the gate-source voltage. The accuracy of the model is verified by comparison with HSPICE for the 90-, 65-, 45-, and 32-nm CMOS technologies. The model shows better accuracy than the n th-power and BSIM3v3 models. Then, we use the proposed I–V model to calculate the read static noise margin (SNM) of nano-scale conventional 6T static random-access memory (SRAM) cells with high accuracy. We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed. The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-, 65-, 45-, and 32-nm technologies. Verification in the presence of process variations and negative bias temperature instability (NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.

Pervasive use of cloud computing and the resulting rise in the number of datacenters and hosting centers (that provide platform or software services to clients who do not have the means to set up and operate their own computing facilities) have brought forth many concerns, including the electrical energy cost, peak power dissipation, cooling, and carbon emission. With power consumption becoming an increasingly important issue for the operation and maintenance of the hosting centers, corporate and business owners are becoming increasingly concerned. Furthermore, provisioning resources in a cost-optimal manner so as to meet different performance criteria, such as throughput or response time, has become a critical challenge. The goal of this paper is to provide an introduction to resource provisioning and power or thermal management problems in datacenters, and to review strategies that maximize the datacenter energy efficiency subject to peak or total power consumption and thermal constraints, while meeting stipulated service level agreements in terms of task throughput and/or response time.

A tri-modal multi-threshold CMOS (MTCMOS) switch design is presented. Similar to the conventional MTCMOS switches, the tri-modal switch comes in two flavors: header and footer. The tri-modal switch provides three different power modes for the underlying circuit: active, drowsy, and sleep. The ability of data retention in the drowsy mode makes the proposed tri-modal switch an excellent candidate for implementing data-retentive power gating designs. We will see that three different low-power design schemes, namely data-retentive power gating, multi-drowsy mode structures, and on-chip dynamic voltage scaling, are implemented using the proposed tri-modal switch. We show that our proposal introduces superior low-power solutions across various circuit operating modes using a single circuitry.

With increasing demand for computing and memory, distributed computing systems have attracted a lot of attention. Resource allocation is one of the most important challenges in the distributed systems specially when the clients have Service Level Agreements (SLAs) and the total profit in the system depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem for multi-tier applications in the cloud computing is considered. An upper bound on the total profit is provided and an algorithm based on force-directed search is proposed to solve the problem. The processing, memory requirement, and communication resources are considered as three dimensions in which optimization is performed. Simulation results demonstrate the effectiveness of the proposed heuristic algorithm.

With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a trade-off between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed and vice versa. Meanwhile, timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. This power minimization can be done after the sign-off which is more accurate and realistic than if it is done before the sign-off. The available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment. In this paper, we introduce our post sign-off leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We set up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by CG. We show that by doing this optimization we can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off. All experiments are done on the real industrial designs.

Unlike liquid crystal display (LCD) panels that require high-intensity backlight, organic LED (OLED) display panels naturally consume low power and provide high image quality thanks to their self-illuminating characteristic. In spite of this fact, the OLED display panel is still the dominant power consumer in battery-operated devices. As a result, there have been many attempts to reduce the OLED power consumption. Since power consumption of any pixel of the OLED display depends on the color that it displays, previous power saving methods change the pixel color subject to a tolerance level on the color distortion specified by the users. In practice, the OLED power saving techniques cannot be used on common user applications such as photo viewers and movie players.

To cope with the variations and uncertainties that emanate from hardware and application characteristics, dynamic power management (DPM) frameworks must be able to learn about the system inputs and environment and adjust the power management policy on the fly. In this paper we present an online adaptive DPM technique based on model-free reinforcement learning (RL), which is commonly used to control stochastic dynamical systems. In particular, we employ temporal difference learning for semi-Markov decision process (SMDP) for the model-free RL. In addition a novel workload predictor based on an online Bayes classifier is presented to provide effective estimates of the workload states for the RL algorithm. In this DPM framework, power and latency tradeoffs can be precisely controlled based on a user-defined parameter. Experiments show that amount of average power saving (without any increase in the latency) is up to 16.7% compared to a reference expert-based approach. Alternatively, the per-request latency reduction without any power consumption increase is up to 28.6% compared to the expert-based approach.

With the increasing levels of variability in the characteristics of VLSI circuits and continued uncertainty in the operating conditions of processors, achieving predictable power efficiency and high performance in the electronic systems has become a daunting, yet vital, task. This paper tackles the problem of system-level dynamic power management (DPM) in the state-of-the-art chip multiprocessor (CMP) architectures that are manufactured in nanoscale CMOS technologies with large process variations or are operated under widely varying environmental conditions over their lifetime. We adopt a Markovian Decision Process based approach to CMP power management problem. The proposed technique models the underlying variability and uncertainty of parameters in system level as a partially observable MDP, and finds the optimal policy that stochastically minimizes energy per request. Experimental results demonstrate the high efficacy of the proposed power management framework.

In this paper, we propose a technique for custom instruction (CI) extension considering process variations. It bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In the proposed method, instead of using the conventional static timing analysis (STA), statistical static timing analysis (SSTA) which in turn results in a probabilistic approach to identifying and selecting different parts of the CI extension is utilized. More precisely, we use the delay Probability Density Function (PDF) of the CIs in identification and selection phases of the CI extension. In the identification phase, the delay of each CI is modeled by PDF whereas the performance yield is added as a constraint. Additionally, in the selection phase, the merit function of the conventional approaches is modified to increase the performance gain of the selected CIs at the price of slightly sacrificing the design yield. Also, to make the approach computationally more efficient, we propose a method for reducing the modeling time of the PDF of the CIs by reducing the number of candidate CIs before extracting the PDF.

Modern batteries (e.g., Li-ion batteries) provide high discharge efficiency, but the rate capacity effect in these batteries drastically decreases the discharge efficiency as the load current increases. Electric double layer capacitors, or simply supercapacitors, have extremely low internal resistance, and a battery-supercapacitor hybrid may mitigate the rate capacity effect for high pulsed discharging current. However, a hybrid architecture comprising a simple parallel connection does not perform well when the supercapacitor capacity is small, which is a typical situation because of the low energy density and high cost of supercapacitors. This paper presents a new battery-supercapacitor hybrid system that employs a constant-current charger. The constant-current charger isolates the battery from supercapacitor to improve the end-to-end efficiency for energy from the battery to the load while accounting for the rate capacity effect of Li-ion batteries and the conversion efficiencies of the converters.

Compared with the conventional homogeneous electrical energy storage (EES) systems, hybrid electrical energy storage (HEES) systems provide high output power and energy density as well as high power conversion efficiency and low self-discharge at a low capital cost. Cycle efficiency of a HEES system (which is defined as the ratio of energy which is delivered by the HEES system to the load device to energy which is supplied by the power source to the HEES system) is one of the most important factors in determining the overall operational cost of the system. Therefore, EES banks within the HEES system should be prudently designed in order to maximize the overall cycle efficiency. However, the cycle efficiency is not only dependent on the EES element type, but also the dynamic conditions such as charge and discharge rates and energy efficiency of peripheral power circuitries. Also, due to the practical limitations of the power conversion circuitry, the specified capacity of the EES bank cannot be fully utilized, which in turn results in over-provisioning and thus additional capital expenditure for a HEES system with a specified level of service. This is the first paper that presents an EES bank reconfiguration architecture aiming at cycle efficiency and capacity utilization enhancement. We first provide a formal definition of balanced configurations and provide a general reconfigurable architecture for a HEES system, analyze key properties of the balanced reconfiguration, and propose a dynamic reconfiguration algorithm for optimal, online adaptation of the HEES system configuration to the characteristics of the power sources and the load devices as well as internal states of the EES banks. Experimental results demonstrate an overall cycle efficiency improvement of by up to 108% for a DC power demand profile, and pulse duty cycle improvement of by up to 127% for high-current pulsed power profile. We also present analysis results for capacity utilization improvement for a reconfigurable EES bank.

Digital information management is the key enabler for the unparalleled rise in productivity and efficiency gains experienced by the world economies. Computing and information processing systems are important elements of the world's digital infrastructure by providing ever-present and ever-increasing general purpose and data-driven processing and storage capabilities for both wired and mobile users. As such, they are also significant drivers of economic growth and social change. However, continued expansion of computing and information processing systems is now hindered by their unsustainable and rising power needs, with associated electrical energy costs and peak power draw requirements. Moreover governments, people, and corporations are becoming increasingly concerned about the environmental impact of these systems i.e., their carbon footprint. Separately from all this, with the increasing levels of variability in the characteristics of nanoscale CMOS devices and on-chip interconnects and continued uncertainty in the operating conditions of VLSI circuits, achieving power efficiency and high performance in computing and information processing systems under process, voltage, and temperature variations as well as interconnect wear-out and device aging has become a daunting, yet vital, task.

In this paper, we present and solve the problem of power-delay optimal soft linear pipeline design. The key idea is to use soft-edge flip-flops to allow time borrowing among consecutive stages of the pipeline in order to provide the timing-critical stages with more time and trade this timing slack for power saving. We formulate the problem of optimally designing the soft-edge flip-flops and setting the clock frequency and supply voltage so as to minimize the power-delay product of a linear pipeline under different scenarios using both deterministic and statistical static delay models. In our first problem formulation, timing violations are avoided by respecting deterministic worst case path delay bounds. Next, the same problem is formulated for a scenario where stage delays are assumed to be random variables, and we minimize the power-delay product while keeping the probability of timing violations bounded. The soft-edge flip flops are equipped with dynamic error detection (and correction) circuitry to detect and fix the errors that might arise from over-clocking. Although the system is capable of recovering from error, there is a tradeoff between performance and power saving, which is exploited to further minimize the power-delay product of the pipeline in our third formulation. Experimental results demonstrate the efficacy of our proposed algorithms for solving each of the aforesaid problems.

No abstract available.

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.

A current source model (CSM) for CMOS logic cells is presented, which can be used for accurate noise and delay analysis in CMOS VLSI circuits. CS modeling is broadly considered as the method of choice for modern static timing and noise analysis tools. Unfortunately, the existing CSMs are only applicable to combinational logic cells. In addition to multistage logic nature of the sequential cells, the main difficulty in developing a CSM for these cells is the presence of feedback loops. This paper begins by presenting a highly accurate CSM for combinational logic cells, followed by models for common sequential cells, including latches and master slave flip-flops. The proposed model addresses these problems by characterizing the cell with suitable nonlinear CSs and capacitive components. Given the input and clock voltage waveforms of arbitrary shapes, our new model can accurately compute the output voltage waveform of the sequential cell. Experimental results demonstrate close-to-SPICE waveforms with three orders of magnitude speedup.

An adaptive method to perform dynamic voltage and frequency scheduling (DVFS) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFS system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The technique, which can be realized with very simple hardware, is completely transparent to the application. The results of applying the method to some real application workloads demonstrate considerable power savings and fewer frequency updates compared to DVFS systems based on fixed update intervals.

In deep sub-micron technology, accurate modeling of output waveforms of library cells under different input slew and load capacitance values is crucial for precise timing and noise analysis of VLSI circuits. Construction of a compact and efficient model of such waveforms becomes even more challenging when manufacturing process and environmental variations are considered. This paper introduces a rigorous and robust foundation to mathematically model output waveforms under sources of variability and to compress the library data. The proposed approach is suitable for today's current source model (CSM) based ASIC libraries. It employs an orthonormal transformation to represent the output waveforms as a linear combination of some appropriately-derived basis waveforms. More significantly Robust Principle Component Analysis (RPCA) is used to stratify the library waveforms into a small number of groups for which different sets of principle components are calculated. This stratification results in a very high compression ratio for the variational CSM library while meeting a maximum error tolerance. Interpolation and further compression is obtained by representing the coefficients as signomial functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature. We propose a procedure to calculate the coefficients and power of the signomial functions. Experimental results demonstrate the effectiveness of the proposed variational CSM modeling framework and the stratification-based compression approach.

With the increasing demand for energy-efficient power delivery network (PDN) in today's electronic systems, configuring an optimal PDN that supports power management techniques, e.g., dynamic voltage scaling (DVS), has become a daunting, yet vital task. This paper describes how to model and configure such a PDN so as to minimize the total energy dissipation in DVS-enabled systems, while satisfying total PDN cost and/or power conversion efficiency constraints. The problem of configuring an energy-efficient PDN under various constraints is subsequently formulated by using a controllable Markovian decision process (MDP) model and solved optimally as a policy optimization problem. The key rationale for utilizing MDP for solving the PDN configuration problem is to manage stochastic behavior of the power mode transition times of DVS-enabled systems. Simulation results demonstrate that the proposed technique ensures energy savings, while satisfying design goals in terms of total PDN cost and its power efficiency.

The current energy and environmental cost trends of datacenters are unsustainable. It is critically important to develop datacenter-wide power and thermal management (PTM) solutions that improve the energy efficiency of the datacenters. This paper describes one such approach where a PTM engine decides on the number and placement of ON servers while simultaneously adjusting the supplied cold air temperature. The goal is to minimize the total power consumption (for both servers and air conditioning units) while meeting an upper bound on the maximum temperature seen in any server chassis in the data center. To achieve this goal, it is important to be able to predict the incoming workload in terms of requests per second (which is done by using a short-term workload forecasting technique) and to have efficient runtime policies for bringing new servers online when the workload is high or shutting them off when the workload is low. Datacenter-wide power saving is thus achieved by a combination of chassis consolidation and efficient cooling. Experimental results demonstrate the effectiveness of the proposed dynamic resource provisioning method.

This paper presents the analysis and optimization of a flip-flop while considering the effect of energetic particle hits on its setup and hold times. First it is shown that the particle hit tightens the setup and hold timing constraints imposed on the flip-flop. Next it is shown how to size transistors of a clocked master-slave CMOS flip-flop to make it more robust against single-event timing upsets. Experimental results to assess the effectiveness of transistor sizing step are provided and discussed.

This paper addresses the problem of minimizing the total energy consumption of a (chip) multiprocessor system while maintaining a required throughput. The minimum energy solution subject to a throughput constraint is achieved by selectively turning cores ON or OFF, assigning a given set of tasks to different cores, and simultaneously selecting the optimum operating supply voltage and clock frequency level for each processor core in the system. This NP-hard problem is solved by a three-level hierarchical framework comprised of a control theory-based dynamic power manager (DPM) and a task assignment unit. Experimental results demonstrate 17% energy saving of the proposed solution approach.

It is important to maintain high efficiency when charging electrical energy storage elements so as to achieve holistic optimization from an energy generation source (e.g., a solar cell array) to an energy storage element (e.g., a supercapacitor bank). Previous maximum power point tracking (MPPT) methods do not consider the fact that efficiency of the charger varies depending on the power output level of the energy generation source and the state of charge of the storage element. This paper is the first paper to optimize the efficiency of a supercapacitor charging process by utilizing the MPPT technique and simultaneously considering the variable charger efficiency. More precisely, previous MPPT methods only maximize the power output of the energy generation source, but they do not guarantee the maximum energy is stored in the energy storage element. Note that the load device takes its energy from the storage element so it is important to maximize energy transfer from the source into the storage element. We present a rigorous framework to determine the optimal capacitance of a supercapacitor and optimal configuration of a solar cell array so as to maximize the efficiency of energy transfer from the solar cells into a bank of supercapacitors. Experimental results show the efficacy of the proposed technique and design optimization framework.

Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.

Electrical energy is a high quality form of energy that can be easily converted to other forms of energy with high efficiency and, even more importantly, it can be used to control lower grades of energy quality with ease. However, building a cost-effective electrical energy storage (EES) system is a challenging task despite steady advances in the design and manufacturing of EES elements including various battery and supercapacitor technologies. As of today, no single type of EES element fulfills high energy density, high power delivery capacity, low cost per unit of storage, long cycle life, low leakage, and so on at the same time.

This paper presents a supervised learning based power management framework for a multi-processor system, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the occupancy state of a global service queue) and then uses this predicted state to look up the optimal power management action (e.g., voltage-frequency setting) from a precomputed policy table. The motivation for utilizing supervised learning in the form of a Bayesian classifier is to reduce the overhead of the PM which has to repetitively determine and assign voltage-frequency settings for each processor core in the system. Experimental results demonstrate that the proposed supervised learning based power management technique ensures system-wide energy savings under rapidly and widely varying workloads.

Given the criticality of energy awareness in wireless networks, it has become essential to devise an improved definition of the network lifetime at the system design stage. The new definition must capture the life profile of the network while accounting for its functionality and specific design parameters. This paper presents the notion of network durability, which captures the spatiotemporal life/death patterns of devices in a wireless network by examining the time evolution of spatial patterns according to which devices are progressively forced to exit the network having exhausted their energy resource. Using network durability, we show how networks can satisfy different levels of monitoring criticality, even when they exhibit the same conventionally defined lifetime. Finally, as an example application, we consider a heterogeneous location-aware modulation scheme where the proposed durability model is effectively employed to characterize the network lifetime.

This paper describes a waveform compression technique suitable for the efficient utilization, storage and interchange of the emerging current source model (CSM) based cell libraries. The technique is based on pre-processing of a collection of voltage/current waveforms for the cells in the library and then, constructing an orthogonal time-voltage/time-current waveform basis using singular-value decomposition. Compression is achieved by representing all waveforms as linear combination coefficients of adaptive subset of the basis waveforms. Experimental results indicate that adaptive waveform representation results in higher compression ratios than the waveform representation as a function of fixed set of basis functions. Interpolation and further compression are obtained by representing the coefficients as simple functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature. The methods introduced in this paper are tested and validated on several industrial strength libraries, with spectacular compression results.

Digital information management is the key enabler for unprecedented rise in productivity and efficiency gains experienced by the world economies during the 21st century. Information processing systems have thus become essential to the functioning of business, service, academic, and governmental institutions. As institutions increase their offerings of digital information services, the demand for computation and storage capability also increases. Examples include online banking, e-filing of taxes, music and video downloads, online shipment tracking, real-time inventory/supply-chain management, electronic medical recording, insurance database management, surveillance and disaster recovery. It is estimated that, in some industries, the number of records that must be retained is growing at a CAGR of 50 percent or greater. This exponential increase in the digital intensity of human existence is driven by many factors, including ease of use and availability of a rich set of information technology (IT) devices and services. Indeed, it would be difficult to imagine how significant societal transformations that better our world could occur without the productivity and innovation enabled by the IT. Unfortunately, the energy cost and carbon footprint of the IT devices and services has become exorbitant. Moreover, current technological and digital service utilization trends result in a doubling of the energy cost of the IT infrastructure and its carbon footprint in less than five years. In an energy-constrained world, this consumption trend is unsustainable and comes at increasingly unacceptable societal and environmental costs. This presentation will first explain what is meant by green computing and how greenness of information processing may be quantified. Next, energy-efficient computing paradigms which utilize chip multi-processing, multiple-voltage domains, dynamic voltage/frequency scaling, and power/clock gating techniques will be reviewed. Finally, techniques for improving performance per Watt of large-scale information processing and storage systems (e.g., a data center), including hierarchical dynamic power management, task placement and scheduling, energy balancing, resource virtualization, and application optimizations that dynamically configure hardware for higher efficiency will be discussed.

In this paper we present deterministic clock gating schemes for various micro architectural blocks of a modern out-of-order superscalar processor. We propose to make use of (1) idle stages of the pipelined function units (FUs) and (2) wrong-path instruction execution during branch mis-prediction, in order to clock gate various stages of FUs. The baseline Pipelined Functional unit Clock Gating (PFCG), presented for evaluation purpose only, disables the clock on idle stages and thus results in 13.93% chip-wide energy saving. Wrong-path instruction Clock Gating (WPCG) detects wrong-path instructions in the event of branch mis-prediction and prevents them from being issued to the FUs, and subsequently, disables the clock of these FUs along with reducing the stress on register file and cache. Simulations demonstrate that more than 92% of all wrong-path instructions can be detected and stopped from being executed. The WPCG architecture results in 16.26% chip-wide energy savings which is 2.33% more than that of the baseline PFCG scheme.

This paper focuses on power minimization in a data center accounting for both the information technology equipment and the air conditioning power usage. In particular we address the server consolidation (on/off state assignment) concurrently with the task assignment. We formulate the resulting optimization problem as an Integer Linear Programming problem and present a heuristic algorithm that solves it in polynomial time. Experimental results show an average of 13% power saving for different data center utilization rates compared to a baseline task assignment technique, which does not perform server consolidation.

This paper addresses the problem of low-power fanout optimization for near-continuous-size inverter libraries. It is demonstrated that because of neglecting short-circuit current, previous techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This paper describes how the problem of low-power fanout optimization can be reduced to inverter-chain optimization problem and formulates the minimization of the total power consumption of an inverter chain as a geometric program. Moreover, it describes an efficient method to minimize the total power consumption of a fanout tree by using multiple-channel-length (multi-LGate) and multiple-threshold-voltage (multi-Vt) techniques. Experimental results show that the proposed technique can reduce the power consumption of the fanout trees by an average of 11.17% over SIS fanout-optimization program.

This paper introduces techniques for power-efficient design of power-delivery network (PDN) in multiple voltage-island system-on-chip (SoC) designs. The first technique is targeted to SoC designs with static-voltage assignment, while the second technique is pertinent to SoC designs with dynamic-voltage scaling (DVS) capability. Conventionally, a single-level configuration of dc–dc converters, where exactly one converter resides between the power source and each load, is used to deliver currents at appropriate voltage levels to different loads on the chip. In the presence of DVS capability, each dc–dc converter in this network should be able to adjust its output voltage. In the first part of this paper, it is shown that, in a SoC design with static-voltage assignment, a multilevel tree topology of suitably chosen dc–dc converters between the power source and loads can result in higher power efficiency in the PDN. The problem is formulated as a combinatorial problem and is efficiently solved by dynamic programming. In the second part of this paper, a new technique is presented to design the PDN for a SoC design to support DVS. In this technique, the PDN is composed of two layers. In the first layer, dc–dc converters with fixed output voltages are used to generate all voltage levels that are needed by different loads in the SoC design. In the second layer of the PDN, a power-switch network is used to dynamically connect the power-supply terminals of each load to the appropriate dc–dc converter output in the first layer. Experimental results demonstrate the efficacy of both techniques.

This paper presents energy-efficient packet interface architecture and a power management technique for gigabit Ethernet controllers, where low-latency and high-bandwidth are required to meet the pressing demands of very high frame-rate data. More specifically, a predictive-flow-queue (PFQ)-based packet interface architecture is presented, which adjusts the operating frequency of different functional blocks at a fine granularity so as to minimize the total system energy dissipation while attaining performance goals. A key feature of the proposed architecture is the implementation of a runtime workload prediction method for the network traffic along with a continuous frequency adjustment mechanism, which enables one to eliminate the latency and energy penalties associated with discrete power mode transitions. Furthermore, a stochastic modeling framework based on Markovian decision processes and queuing models is employed, which make it possible to adopt a precise mathematical programming formulation for the energy optimization under performance constraints. Experimental results with a designed 65-nm Gb Ethernet controller show that the proposed interface architecture and continuous frequency scaling result in system-wide energy savings while meeting performance specifications.

This paper tackles the problem of dynamic power management (DPM) in nanoscale CMOS design technologies that are typically affected by increasing levels of process and temperature variations and fluctuations due to the randomness in the behavior of silicon structure. This uncertainty undermines the accuracy and effectiveness of traditional DPM approaches. This paper presents a stochastic framework to improve the accuracy of decision making during dynamic power management, while considering manufacturing process and/or environment induced uncertainties. More precisely, variability and uncertainty at the system level are captured by a partially observable semi-Markov decision process with interval-based definition of states while the policy optimization problem is formulated as a mathematical program based on this model. Experimental results with a RISC processor in 65-nm technology demonstrate the effectiveness of the technique and show that the proposed uncertainty-aware power management technique ensures system-wide energy savings under statistical circuit parameter variations.

In this paper, a low-power structure called bypass zero, feed A directly (BZ-FAD) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications to the multiplier which multipliesAbyBinclude the removal of the shifting theBregister, direct feeding ofAto the adder, bypassing the adder whenever possible, using a ring counter instead of a binary counter and removal of the partial product shift. The architecture makes use of a low-power ring counter proposed in this work. Simulation results for 32-bit radix-2 multipliers show that the BZ-FAD architecture lowers the total switching activity up to 76% and power consumption up to 30% when compared to the conventional architecture. The proposed multiplier can be used for low-power applications where the speed is not a primary design parameter.

In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.

With the increasing levels of variability in the behavior of manufactured nano-scale devices and dramatic changes in the power density on a chip, timely identification of hot spots on a chip has become a challenging task. This paper addresses the questions of how and when to identify and issue a hot spot alert. There are important questions since temperature reports by thermal sensors may be erroneous, noisy, or arrive too late to enable effective application of thermal management mechanisms to avoid chip failure. This paper thus presents a stochastic technique for identifying and reporting local hot spots under probabilistic conditions induced by uncertainty in the chip junction temperature and the system power state. More specifically, it introduces a stochastic framework for estimating the chip temperature and the power state of the system based on a combination of Kalman Filtering (KF) and Markovian Decision Process (MDP) model. Experimental results demonstrate the effectiveness of the framework and show that the proposed technique alerts about thermal threats accurately and in a timely fashion in spite of noisy or sometimes erroneous readings by the temperature sensor.

Achieving high performance under a peak temperature limit is a first-order concern for VLSI designers. This paper presents a new abstract model of a thermally-managed system, where a stochastic process model is employed to capture the system performance and thermal behavior. We formulate the problem of dynamic thermal management (DTM) as the problem of minimizing the energy cost of the system for a given level of performance under a peak temperature constraint by using a controllable Markovian decision process (MDP) model. The key rationale for utilizing MDP for solving the DTM problem is to manage the stochastic behavior of the temperature states of the system under online re-configuration of its micro-architecture and/or dynamic voltage-frequency scaling. Experimental results demonstrate the effectiveness of the modeling framework and the proposed DTM technique.

This paper presents a current source model (CSM) of a CMOS logic cell, which captures simultaneous switching of multiple inputs while accounting for the effect of internal node voltages of the logic cell. Characterization procedures for various components of the proposed CSM are described and application of the model to output waveform computation is discussed. Experimental results to assess the accuracy and efficiency of the proposed multiple input switching CSM in the context of noise and timing analyses in VLSI circuits are reported.

With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization under process, voltage, and temperature (PVT) variations as well as current, voltage, and thermal (CVT) stress has become a daunting, yet vital, task. In this paper, we present a stochastic dynamic power management (DPM) framework to improve the accuracy of decision making under probabilistic conditions induced by PVT variations and/or stress. More precisely, we propose a resilient power management technique that guarantees to select an optimal policy under sources of uncertainty. A key characteristic of the proposed technique is that the effects of uncertainties due to variability and stress are captured by stochastic processes which control a self- improving power manager. Simulation results with a 65 nm processor design show that, compared to the worst-case PVT conditions, the proposed DPM technique ensures energy efficiency, while reducing the uncertain behaviors of the system.

Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizing which minimizes the total sleep transistor width for a coarse-grain multi-threshold CMOS circuit assuming a given standard cell and sleep transistor placement. First, the circuit is decomposed into a set of modules, each containing the set of logic cells that are closest to a sleep transistor cell. Next given an upper bound on the overall circuit speed degradation, the global timing slack is distributed among different clusters using a delay-budgeting. The slack distribution result is then used to size the sleep transistors such that the total sleep transistor width is minimized while accounting for the parasitic resistances of the virtual ground net. Results show that the proposed sizing algorithm produces sleep transistor sizes that are 40% smaller than those produced by previous approaches.

With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, different types of flip-flops exhibit different levels of susceptibility to NBTI-induced change in their setup/hold time values. Finally, an NBTI-aware transistor sizing technique can minimize the NBTI effect on timing characteristics of the flip-flops.

Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for employing SSTA is the characterization of the setup and hold times of the latches and flip-flops in the cell library. This paper presents a methodology to exploit the statistical codependence of the setup and hold times. The approach comprises of three steps. In the first step, probability mass function (pmf) of codependent setup and hold time (CSHT) contours are approximated with piecewise linear curves by considering the probability density functions of sources of variability. In the second step, pmf of the required setup and hold times for each flip-flop in the design are computed. Finally, these pmf values are used to compute the probability of individual flip-flops in the design passing the timing constraints and to report the overall pass probability of the flip-flops in the design as a histogram. We applied the proposed method to true single phase clocking flip-flops to generate the piecewise linear curves for CSHT. The characterized flip-flops were instantiated in an example design, on which timing verification was successfully performed.

This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three different steps. At the beginning of an off-chip data bus transaction, i) connect all bus lines that are expected to fall to a common node, ii) connect, one at a time and for a fixed period of time, each of bus lines that are expected to rise to the same common node to enable charge recycling, and finally, iii) resume regular data bus transaction by enabling the tri-state buffers to complete the remaining charging (discharging) of the rising (falling) bus lines. Experimental results in Hspice show that the proposed technique achieves 17.4% average energy savings in a 32 bit-wide data bus implemented in a 0.13¼m technology with a 1.8V supply voltage.

In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running. The technique dynamically adjusts the supply voltage level and clock frequency of the design by exploiting slacks that are present in various stages of the pipeline. The key enabler is the utilization of soft-edge flip-flops to allow time borrowing between consecutive stages of the pipeline in order to provide the timing-critical stages with more time to complete their computations resulting in lower error probability. This raises the effective throughput of the pipeline for a fixed energy consumption level, or alternatively, lowers the energy consumption for the same effective throughput. We formulate the problem of optimally selecting the transparency window sizes of the soft-edge flip-flops and the frequency level of the pipeline circuit at different voltage levels so as to optimize the energy cost of the achieved throughput. Experimental results show the efficacy of the problem formulation and solution technique.

This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conventional analysis of this effect in sequential circuit elements (SCEs) tends to underestimate the threat posed by such events. More precisely, there exists a timing window close to the triggering edge of the clock during which a SCE is more vulnerable to the particle hit. This phenomenon has been ignored by previous work, resulting in false negatives. Next the paper explains how to size transistors of a familiar SCE i.e., a clocked CMOS latch, to make it more robust to such events. Experimental results to validate the characterization and transistor sizing steps are provided and discussed.

A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Boolean difference calculus and can be applied to the problem of calculating the error probability at the primary outputs of a multi-level Boolean circuit with a time complexity which is linear in the number of gates in the circuit. This is done by starting from the primary inputs and moving toward the primary outputs by using a post-order traversal. Experimental results demonstrate the accuracy and efficiency of the proposed approach compared to the other known methods for error calculation in VLSI circuits.

This paper presents a novel technique to minimize the total power consumption of a synchronous linear pipeline circuit by exploiting extra slacks available in some stages of the pipeline. The key idea is to utilize soft-edge flip-flops to enable time borrowing between stages of a linear pipeline in order to provide the timing-critical stages with more time to complete their computations. Time borrowing, in conjunction with keeping the clock frequency unchanged, gives rise to a positive timing slack in each pipeline stage. The slack is subsequently utilized to minimize the circuit power consumption by reducing the supply voltage level. We formulate and solve the problem of optimally selecting the transparency window of the soft-edge flip-flops and choosing the minimum supply voltage level for the pipeline circuit as a quadratic program, thereby minimizing the power consumption of the linear pipeline circuit under a clock frequency constraint. Experimental results prove the efficacy of the problem formulation and solution technique.

With power efficiency and lifetime awareness becoming critical design concerns in wireless sensor networks (WSN), it has become essential to exploit the physical layer characteristics at the system deployment stage. This paper focuses on how certain physical layer attributes can affect both the lifetime and the end-to-end delay in a hierarchical WSN. We present a heterogeneous modulation scheme and report its impact on the spatial distribution of energy dissipation and the resulting network lifetime. Moreover, we study how this heterogeneous modulation scheme affects the end-to-end delay due to inherent trade-offs in power efficiency and bandwidth efficiency of the different modulation schemes.

A compact canonical form and a computational procedure for solving the Boolean matching problem under permutation and complementation of variables are presented. The proposed approach, which utilizes generalized signatures and variable symmetries, can handle combinational functions with no limitation on the number of input variables. Experimental results demonstrate the generality and effectiveness of the proposed canonical form and the associated Boolean matching algorithm.

The design of a suitable power gating (e.g., multithreshold or super cutoff CMOS) structure is an important and challenging task in sub-90-nm very large scale integration (VLSI) circuits where leakage currents are significant. In designs where the mode transitions are frequent, a significant amount of energy is consumed to turn on or off the power gating structure. It is thus desirable to develop a power gating solution that minimizes the energy consumed during mode transitions. This paper presents such a solution by recycling charge between the virtual power and ground rails immediately after entering the sleep mode and just before wakeup. The proposed method can save up to 43% of the dynamic energy wasted during mode transition while maintaining the wakeup time of the original circuit. It also reduces the peak negative voltage value and the settling time of the ground bounce.

In this article, a wavelet-based dynamic power management policy (WBDPM) is proposed. In this approach, the workload source (service requester) is modeled by a nonstationary time series which, in turn, represented by a nondecimated Haar wavelet as its basis. The proposed approach is robust and has the ability to minimize energy dissipation under different performance constraints. To assess the accuracy of the model, the algorithm was implemented for data extracted from the hard disks of computers. Prediction results of this approach for the case of a nonstationary service requester exhibit accuracies of more than 95%.

editorial Free Access Share on Editorial Editor: Massoud Pedram View Profile Authors Info & Claims ACM Transactions on Design Automation of Electronic SystemsVolume 13Issue 4September 2008 Article No.: 55pp 1–3https://doi.org/10.1145/1391962.1391963Published:03 October 2008Publication History 0citation323DownloadsMetricsTotal Citations0Total Downloads323Last 12 Months17Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-Vtand dual-Toxassignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.

In this paper, we present a dynamic thermal management (DTM) algorithm based on: 1) accurate estimation of the workload of frames in a group of pictures (GOP) in an MPEG-2 video stream and 2) slack borrowing across the GOP frames in order to achieve a thermally safe state of operation in microprocessors during the video decoding process. The proposed DTM algorithm employs dynamic voltage and frequency scaling (DVFS) while considering the frame-rate-dependent GOP deadline, variance of the frame decoding times within the GOP, and a maximum chip temperature constraint. If it becomes necessary to sacrifice video quality or violate the GOP deadline due to a low temperature bound, then the (intra-frame) spatial quality degradation and the (inter-frame) temporal quality degradation will be applied to the GOP. Experimental results demonstrate the competence and efficiency of the proposed online DTM algorithm.

An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage values. Therefore the actual shape of the voltage signal waveforms at the input and output of the cell should be considered in order to precisely calculate the short circuit energy dissipation. Previous approaches such as the approximation of the crosstalk induced noisy waveforms with saturated ramps can lead to short circuit energy estimation errors as high as an order of magnitude for a minimum sized inverter. To resolve this shortcoming, a current-based logic cell model is utilized, which constructs the output voltage waveform for a given noisy input waveform. The input and output voltage waveforms are then used to calculate the short circuit current, and hence, short circuit energy dissipation. A characterization process is executed for each logic cell in the standard cell library to model the relevant electrical parameters e.g., the parasitic capacitances and nonlinear current sources. Additionally, our model is capable of calculating the short circuit energy dissipation caused by glitches in VLSI circuits, which in some cases can be a key contributor to the total circuit energy dissipation. Experimental results show an average error of about 1% and a maximum error of 3% compared to SPICE for different types of logic cells under noisy input waveforms including glitches while the runtime speedup is up to a factor of 16,000.

This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient gigabit Ethernet controller. Key characteristics of such a controller are low-latency and high-bandwidth required to meet the pressing demands of extremely high frame and control data, which in turn cause difficulties in managing power dissipation. We propose a flow-through-queue (FTQ) based power management method, which allows some of the tasks involved in processing the frame data to be offloaded. This in turn enables utilization of multiple clock rates and multiple voltages for different cores inside the Ethernet controller. A modeling approach based on semi-Markov decision process (SMDP) and queuing models is employed, which allow one to apply mathematical programming formulations for energy optimization under performance constraints. The proposed gigabit Ethernet controller is designed with a 130nm CMOS technology that includes both high and low threshold voltages. Experimental results show that the proposed power optimization method can achieve system-wide energy savings under tighter performance constraints.

High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where only one converter resides between the source and each load, is used to deliver currents with appropriate voltage levels to different loads in the circuit. In this paper we show that using a tree topology of suitably chosen voltage regulators between the power source and loads yields higher power efficiency in the power delivery network. We formulize the problem of selecting the best set of regulators in a tree topology as a dynamic program and efficiently solve it. Experimental results demonstrate the efficacy of proposed problem formulation and solution.

This paper tackles the problem of dynamic power management (DPM) in nanoscale CMOS design technologies that are typically affected by increasing levels of process, voltage, and temperature (PVT) variations and fluctuations. This uncertainty significantly undermines the accuracy and effectiveness of traditional DPM approaches. More specifically, a stochastic framework was propose to improve the accuracy of decision making in power management, while considering the manufacturing process and/or design induced uncertainties. A key characteristic of the framework is that uncertainties are effectively captured by a partially observable semi-Markov decision process. As a result, the proposed framework brings the underlying probabilistic PVT effects to the forefront of power management policy determination. Experimental results with a RISC processor demonstrate the effectiveness of the technique and show that the proposed variability-aware power management technique ensures robust system-wide energy savings under probabilistic variations

NoC is an efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip. NoCs have tackled the SoCs disadvantages and are scalable. In this paper, we compare two popular NoC topologies, i.e., mesh and torus, in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms and two common traffic models, uniform and hotspot. To the best of our knowledge, this is the first effort in comparing mesh and torus topologies under different routing algorithms and traffic models with respect to their performance and power consumption.

The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce sub threshold leakage currents during the standby mode of CMOS VLSI Circuits. The performance of MTCMOS circuits strongly depends on the size of the sleep transistors and the parasitics on the virtual ground network. Given a placed net list of a row-based MTCMOS design and the number of sleep transistor cells on each standard cell row, this paper introduces an optimal algorithm for linearly placing the allocated sleep transistors on each standard cell row so as to minimize the performance degradation of the MTCMOS circuit, which is in part due to unwanted voltage drops on its virtual ground network. Experimental results show that, compared to existing methods of placing the sleep transistors on cell rows, the proposed technique results in up to 11% reduction in the critical path delay of the circuit.

An effective thermal management scheme, called active bank switching, for temperature control in the register file of a microprocessor is presented. The idea is to divide the physical register file into two equal-sized banks, and to alternate between the two banks when allocating new registers to the instruction operands. Experimental results show that this periodic active bank switching scheme achieves 3.4°C of steady-state temperature reduction, with a mere 0.75% average performance penalty.

A downside of using Multi-Threshold CMOS (MTCMOS) technique for leakage reduction is the energy consumption during transitions between sleep and active modes. Previously, a charge recycling (CR) MTCMOS architecture was proposed to reduce the large amount of energy consumption that occurs during the mode transitions in powergated circuits. Considering the RC parasitics of the virtual ground and VDD lines, proper sizing and placement of charge-recycling transistors is key to achieving the maximum power saving. In this paper, we show that the sizing and placement problems of charge-recycling transistors in CR-MTCMOS can be formulated as a linear programming problem, and hence, can be efficiently solved using standard mathematical programming packages. The proposed sizing and placement techniques allow us to employ the CR-MTCMOS solution in large row-based standard cell layouts while achieving nearly the full potential of this power-gating architecture, i.e., we achieve 44% saving in switching energy due to the mode transition in CR-MTCMOS compared to standard MTCMOS.

Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabler for the design of any DVS technique. In this paper we show how to design an efficient power delivery network for a complex system-on-a-chip (SoC) so as to enable dynamic power management through assignment of appropriate voltage level (and the corresponding clock frequency) to each function block in the SoC. We show that the proposed technique reduces the power loss of the power delivery network by an average of 34% while reducing its cost by an average of 8%.

This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors to reduce the leakage power consumption in the idle mode is used. We simultaneously calculate the repeater sizes, repeater distances, and the size of the sleep transistors to minimize the power dissipation. The effect of crosstalk coupling capacitance on propagation delay and (switching and short circuit) power dissipation is considered. Experimental results show that depending on the activity factor of the circuit, the proposed technique can significantly reduce the power consumption of the global bus interconnects.

This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementary bit-lines in each column of the RegFile. Because the read and write ports for the RegFile are separately implemented, it is possible to avoid pre-charging the bit-line pair for consecutive writes. More precisely, when writing same values to some cells in the same column of the RegFile, it is possible to eliminate energy consumption due to precharging of the bit-line pair. At the same time, when writing opposite values to some cells in the same column of the RegFile, it is possible to reduce energy consumed in charging the bit-line pair thanks to charge-sharing. Motivated by these observations, we modify the bit-line structure of the write ports in the RegFile such that i) we remove per-cycle bitline pre-charging and ii) we employ conditional data dependent charge-sharing. Experimental results on a set of SPEC2000INT / MediaBench benchmarks show an average of 61.5% energy savings with 5.1% area overhead and 16.2% increase in write access delay.

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. In this paper, two new approaches for doing variational gate TA for Gaussian and non-Gaussian sources of variation in parameterized sigmaTA are presented. To start, a variational RC-pi load is approximated by using a canonical first-order model. Next, an accurate variational gate TA (VGTA) technique, which accounts for variational RC-pi loads, variational input transitions, and a variation-aware gate library, is introduced. The proposed method relies on static effective-capacitance-calculation method and its variational form. Experimental results demonstrate that VGTA exhibits an average error of 4% for gate delay and output transition time with respect to the Monte Carlo simulation with 104samples. Next, a more efficient VGTA [called Fast VGTA (F-VGTA)] based on a single-iteration variational effective capacitance calculation is presented. Experimental results show that F-VGTA achieves an average error of 7% for gate delay and output transition time with respect to the Monte Carlo simulation with 104samples but with runtimes that are about two times faster than VGTA.

In this paper, we present a synthesis technique targeted toward coarse-grained antifuse-based field- programmable gate arrays (FPGAs). A macrologic cell, in this class of FPGAs, has multiple inputs and multiple outputs. A library of small logic cells can be generated from this macrocell and used to map the target netlist. First, we calculate the minimum number of macrologic cells required to map a given circuit by using either a dynamic programming or a linear programming technique. Given this minimum number of macrologic cells, we introduce an interconnect-aware clustering algorithm that assigns logic cells to individual macrocells so as to minimize the routing costs. Alternatively, a timing slack-driven clustering algorithm is presented where timing criticalities of nodes in a network are calculated and used to determine the final packing into the macrocells so as to minimize the number of the macrocells on the critical paths. When compared to results from a commercial tool, our two synthesis techniques reduce the number of macrologic cells by 12% and the maximum depth by 35%, respectively.

introduction Introduction to special issue on demonstrable software systems and hardware platforms Authors: Sung Kyu Lim Atlanta, Georgia Atlanta, GeorgiaView Profile , Massoud Pedram Los Angeles, California Los Angeles, CaliforniaView Profile Authors Info & Claims ACM Transactions on Design Automation of Electronic SystemsVolume 12Issue 3August 2007 Article No.: 20pp 1–3https://doi.org/10.1145/1255456.1255457Published:22 May 2008Publication History 1citation283DownloadsMetricsTotal Citations1Total Downloads283Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in wrong values being latched in the circuit registers. We propose a design methodology for limiting the maximum value of the supply/ground currents to a user-specified threshold level while minimizing the wake up (sleep to active mode transition) time. In addition to controlling the sudden discharge of the accumulated charge in the intermediate nodes of the circuit through the sleep transistors during the wake up transition, we can eliminate short circuit current and spurious switching activity during this time. This is, in turn, achieved by reducing the amount of charge that must be removed from the intermediate nodes of the circuit and by turning on different parts of the circuit in a way that causes a uniform distribution of current over the wake up time. Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a 1-2 orders of magnitude improvement in the product of the maximum ground current and the wake up time

As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. This paper introduces a new framework for performing statistical gate timing analysis for non-Gaussian sources of variation in block-based sigmaTA. First, an approach is described to approximate a variational RC-pi load by using a canonical first-order model. Next, an accurate variation-aware gate timing analysis based on statistical input transition, statistical gate timing library, and statistical RC-pi load is presented. Finally, to achieve the aforementioned objective, a statistical effective capacitance calculation method is presented. Experimental results show an average error of 6% for gate delay and output transition time with respect to the Monte Carlo simulation with 104samples while the runtime is nearly two orders of magnitude shorter

In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.

This paper introduces a new current-based cell timing analyzer, called CGTA, which has a higher performance than existing logic cell timing analysis tools. CGTA relies on a compact lookup table storing the output current gain (sensitivity) of every logic cell as a function of its input voltage and output load. The current gain values are subsequently used by the timing calculator to produce the output current value as a function of the applied input voltage. This current and the output load then uniquely determine the output voltage value. Therefore, CGTA is capable of efficiently and accurately computing the output voltage waveform of a logic cell, which has been subjected to an arbitrary noisy input voltage waveform. Experimental results are presented to assess the quality of CGTA compared to other existing approaches

This paper addresses the problem of minimizing energy consumption of a computer system performing periodic hard real-time tasks with precedence constraints. In the proposed approach, dynamic power management and voltage scaling techniques are combined to reduce the energy consumption of the CPU and devices. The optimization problem is first formulated as an integer programming problem. Next, a three-phase solution framework, which integrates power management scheduling and task voltage assignment, is proposed. Experimental results show that the proposed approach outperforms existing methods by an average of 18% in terms of the system-wide energy savings.

A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can accurately compute the output waveform for input waveforms of arbitrary shapes subjected to noise. The cell parasitic capacitances are pre-characterized by lookup tables to improve the accuracy. To capture the effect of process parameter variations on the cell behavior, the output voltage waveform of logic cells is modeled by a stochastic Markovian process in which the voltage value probability distribution at each time instance is computed from that of the previous time instance. Next the probability distribution of a%Vdd crossing time, i.e., the hitting time of the output voltage stochastic process is computed. Experimental results demonstrate the high accuracy of our cell delay model compared to Monte-Carlo-based SPICE simulations.

This paper presents a temporally-aware backlight scaling (TABS) technique for video streams. The goal is to maximize energy saving in the display system by means of dynamic backlight dimming subject to a user-specified tolerance on the video distortion. The video distortion itself comprises of (i) an intra-frame (spatial) distortion component due to frame-sensitive backlight scaling and transmittance function tuning and (ii) an inter-frame (temporal) distortion component due to large-step backlight dimming across multiple frames and modulated by the physiological characteristics of the human visual system. The proposed backlight scaling technique is capable of efficiently computing the flickering effect online and subsequently using a measure of the temporal distortion to appropriately adjust the slack on the intra-frame spatial distortion. The proposed technique has been implemented on the Apollo Testbed II hardware platform. Actual current measurements on this platform demonstrate the superiority of TABS compared to previous backlight dimming techniques.

Designing an energy efficient power gating structure is an important and challenging task in Multi-Threshold CMOS (MTCMOS) circuit design. In order to achieve a very low power design, the large amount of energy consumed during mode transition in MTCMOS circuits should be avoided. In this paper, we propose an appropriate charge recycling technique to reduce energy consumption during the mode transition of MTCMOS circuits. The proposed method can save up to 46% of the mode transition energy while, in most cases, maintaining, or even improving, the wake up time of the original circuit. It also reduces the peak negative voltage value and the settling time of the ground bounce.

This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a framework for performing timing analysis of RLC networks with step inputs, under both Gaussian and non-Gaussian sources of variation, is presented. In this framework, resistance, inductance, and capacitance of the RLC line are modeled in a canonical first order form and used to produce the corresponding propagation delay and slew (time) in the canonical first-order form. To accomplish this step, mean, variance, and skewness of delay and slew distributions are obtained in an efficient, yet accurate, manner. The proposed framework can be extended to consider higher order terms of the various sources of variation. Experimental results show average errors of less than 2% for the mean, variance and skewness of interconnect delay and slew while achieving orders of magnitude speedup with respect to a Monte Carlo simulation with 104samples

Quantum information processing technology is in its pioneering stage and no proficient method for synthesizing quantum circuits has been introduced so far. This paper introduces an effective analysis and synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can generate a quantum circuit using the most basic quantum operators, i.e., the rotation and controlled-rotation primitives. The paper introduces the notion of quantum factored forms and presents a canonical and concise representation of quantum logic circuits in the form of quantum decision diagrams (QDD's), which are amenable to efficient manipulation and optimization including recursive unitary functional bi-decomposition. This paper concludes by presenting the QDD-based algorithm for automatic synthesis of quantum circuits

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in very deep submicron regime. As a result, reducing the subthreshold and gate-tunneling leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-Vtand dual-Toxassignment to reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different types of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. Simulation results with a 65 nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 Kb SRAM by more than 50%

While transistors per square millimeter and on-chip clock keep scaling smoothly according to Moore’s Law, Vdd does not, nor does Vth. This leads to a dramatic increase in chip power density, and to a significant shift in the balance between dynamic and leakage power. In spite of the recent effort made by EDA vendors in delivering novel solutions that help mitigating the effects on power consumption of technology scaling, the question of whether EDA industry is taking the low-power matter seriously still remains. This session will provide an answer to this intriguing question, by first offering a short review of the state of-the-art in design technologies for dynamic and leakage power minimisation. The session will then continue with a public “trial”, in which OEMs, IDMs, IP and fabless semiconductor vendors will play the role of the public prosecutor, against defendant EDA industry. The court’s ruling will tell us about the future targets the EDA vendors will pursue in low-power design technologies.

A cell delay model based on rate-of-current-change is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More precisely, a pre-characterized table of time derivatives of the output current as a function of input voltage and output load values is constructed. The data in this table, in combination with the Taylor series expansion of the output current, is utilized to progressively compute the output current waveform, which is then integrated to produce the output voltage waveform. Experimental results show the effectiveness and efficiency of this delay model

This paper presents a timeout-driven DPM technique which relies on the theory of Markovian processes. The objective is to determine the energy-optimal timeout values for a system with multiple power saving states while satisfying a set of user defined performance constraints. More precisely, a controllable Markovian process is exploited to model the power management behavior of a system under the control of a timeout policy. Starting with this model, a perturbation analysis technique is applied to develop an offline gradient-based approach to determine the optimal timeout values. Online implementation of this technique for a system with dynamically-varying system parameters is also described. Experimental results demonstrate the effectiveness of the proposed approach. Introduction Dynamic power management (DPM), which refers to selective shut-off or slow-down of components that are idle or underutilized, has proven to be a particularly effective technique for reducing power dissipation in such systems. In the literature, various DPM techniques have been proposed, from heuristic methods presented in early works [ 1][ 2] to stochastic optimization approaches [ 3][ 4]. Among the heuristic DPM methods, the timeout policy is the most widely used approach in industry and has been implemented in many operating systems. Examples include the power management scheme incorporated into the Windows system, the low-power saving mode of the IEEE 802.11a-g protocol for wireless LAN card, and the enhanced adaptive battery life extender (EABLE) for the Hitachi disk drive. Most of these industrial DPM techniques provide mechanisms to adjust the timeout values at the user level.

Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a significant impact on both device (front-end of the line) and interconnect (back-end of the line) performance. Statistical static timing analysis techniques are being developed to tackle this important problem. Existing timing analysis tools divide the analysis into interconnect (wire) timing analysis and gate timing analysis. In this paper, we focus on statistical static timing analysis of coupled interconnects where crosstalk noise analysis is unavoidable. We propose a new framework for handling the effect of Gaussian and Non-Gaussian process variations on coupled interconnects. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as the line width, metal thickness, and dielectric thickness in the presence of crosstalk noise. To achieve this goal, we express the electrical parameters of the coupled interconnects in a first order (linear) form as function of changes in physical parameters and subsequently use these forms to perform accurate timing and noise analysis to produce the propagation delay and slew in the first-order forms. This work can be easily extended to consider the effect of higher order terms of the sources of variation. Experimental results show that the proposed method is capable of accurately predicting delay variation in a coupled interconnect line.

This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic replication caused by timing constraint during the low-power driven clustering. This technique reduces size of duplicated logic substantially, resulting in benefits in area, delay, and power dissipation. First, we build power-delay curves at nodes with the aid of the prediction algorithm. Next, we choose the best cluster starting from primary outputs moving backward in the circuit based on these curves. Experimental results show 16% and 20% reduction in dynamic and leakage power dissipation with 18% area reduction compared to the results of clustering without the replication prediction.

Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. Statistical approaches have been suggested as the most effective substitute for corner-based approaches to deal with the variability of present process technology nodes. This paper introduces a statistical analysis of the crosstalk-aware delay of coupled interconnects considering process variations. The few existing works that have studied this problem suffer not only from shortcomings in their statistical models, but also from inaccurate crosstalk circuit models. We utilize an accurate distributed RC-p model of the interconnections to be able to model process variations close to reality. The considerable effect of correlation among the parameters of neighboring wire segments is also indicated. Statistical properties of the crosstalk-aware output delay are characterized and presented as closed-formed expressions. Monte Carlo Spice-based experimental results demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay when crosstalk is present.

An efficient adaptive method to perform dynamic voltage and frequency management (DVFM) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFM system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The method, which is based on introducing the concept of an effective deadline, utilizes the correlation between consecutive values of the workload. In practice because the frequency and voltage update rates are dynamically set based on variable update interval lengths, voltage fluctuations on the power network are also minimized. The technique, which may be implemented by simple hardware and is completely transparent from the application, leads to power savings of up to 60% for highly correlated workloads compared to DVFM systems based on fixed update intervals.

This paper proposes a stochastic dynamic thermal management (DTM) technique in high-performance VLSI system with especial attention to the uncertainty in temperature observation. More specifically, we propose a stochastic thermal management framework to improve the accuracy of decision making in DTM, which performs dynamic voltage and frequency scaling to minimize total power dissipation and on-chip temperature. A key characteristic of the framework is that thermal states are controlled by stochastic processes, i.e., partially observable semi-Markov decision processes. Collaborative optimization is considered with mathematical programming formulations to reduce operating temperature by using multi-objective design optimization methods. Experimental results with 32-bit embedded RISC processor demonstrate the effectiveness of the technique and show that the proposed algorithm ensures thermal safety under performance constraints.

This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This shows to achieve a low-power fanout tree, an accurate power consumption model should be used as the objective function. Moreover, we propose an efficient method to minimize the total power consumption of a fanout tree by using MTCMOS and Multi-Vt techniques. Experimental results show that depending on the activity factor of the circuit, the proposed technique can reduce the power consumption of the fanout tree 18% to 45%.

In this paper, we propose an effective dynamic thermal management (DTM) scheme for MPEG-2 decoding by allowing some degree of spatiotemporal quality degradation. Given a target MPEG-2 decoding time, we dynamically select either an intra-frame spatial degradation or an inter-frame temporal degradation strategy in order to make sure that the microprocessor chip will continue to stay in a thermally safe state of operation, albeit with certain amount of image/video quality loss. For our experiments, we use the MPEG-2 decoder program of MediaBench and modify/combine Wattch and HotSpot for the power and thermal simulations and measurements, respectively. Our experimental results show that we achieve thermally safe state with spatial quality degradation of 0.12 Root Mean Square Error (RMSE) and with frame drop rate of 12.5% on average.

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

This paper advances the state of the art by presenting a well-founded mathematical framework for modeling and manipulating Markov processes. The key idea is based on the fact that a Markov process can be decomposed into a collection of directed cycles with positive weights, which are proportional to the probability of the cycle traversals in a random walk. Two applications of this new formalism in the computer-aided design area are studied. In the first application, the authors present a new state assignment technique to reduce dynamic power consumption in finite state machines. The technique comprises of first decomposing the state machine into a set of cycles and then performing a state assignment by using Gray codes. The proposed encoding algorithm reduces power consumption by an average of 15%. The second application is sequence compaction for improving the efficiency of dynamic power simulators. The proposed method is based on the cycle decomposition of the Markov process representing the given input sequence and then selecting a subset of these cycles to construct the compacted sequence

This paper addresses the problem of maximizing the capacity utilization of the battery power source in a portable electronic system under latency and loss rate constraints. First, a detailed stochastic model of a power-managed battery-powered electronic system is presented. The model, which is based on the theories of continuous-time Markovian decision processes (CTMDP) and stochastic networks, captures two important characteristics of today's rechargeable battery cells; i.e., the current rate-capacity characteristic and the relaxation induced capacity recovery. Next, the battery-aware dynamic power management (DPM) problem is formulated as a policy optimization problem and is solved by using a linear programming approach. Experimental results show that the proposed method outperforms existing methods by more than 20% in terms of battery service lifetime.

No abstract available.

Static timing analysis is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model-order reduction techniques for wire delay calculation is prohibitively expensive. In this paper, we present sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis. The key idea is to partition the circuit into low and high complexity circuits, whereby low complexity circuits are handled with efficient algorithms such as total capacitance algorithm for gate delay and the Elmore metric for wire delay and high complexity circuits are handled with sign-off algorithms. Experimental results on microprocessor designs show accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times

Liquid crystal displays (LCDs) have appeared in applications ranging from medical equipment to automobiles, gas pumps, laptops, and handheld portable computers. These display components present a cascaded energy attenuator to the battery of the handheld device which is responsible for about half of the energy drain at maximum display intensity. As such, the display components become the main focus of every effort for maximization of embedded system's battery lifetime. This paper proposes an approach for pixel transformation of the displayed image to increase the potential energy saving of the backlight scaling method. The proposed approach takes advantage of human visual system (HVS) characteristics and tries to minimize distortion between the perceived brightness values of the individual pixels in the original image and those of the backlight-scaled image. This is in contrast to previous backlight scaling approaches which simply match the luminance values of the individual pixels in the original and backlight-scaled images. Furthermore, this paper proposes a temporally-aware backlight scaling technique for video streams. The goal is to maximize energy saving in the display system by means of dynamic backlight dimming subject to a video distortion tolerance. The video distortion comprises of: 1) an intra-frame (spatial) distortion component due to frame-sensitive backlight scaling and transmittance function tuning and 2) an inter-frame (temporal) distortion component due to large-step backlight dimming across frames modulated by the psychophysical characteristics of the human visual system. The proposed backlight scaling technique is capable of efficiently computing the flickering effect online and subsequently using a measure of the temporal distortion to appropriately adjust the slack on the intra-frame spatial distortion, thereby, achieving a good balance between the two sources of distortion while maximizing the backlight dimming-driven energy saving in the display system and meeting an overall video quality figure of merit. The proposed dynamic backlight scaling approach is amenable to highly efficient hardware realization and has been implemented on the Apollo Testbed II. Actual current measurements demonstrate the effectiveness of proposed technique compared to the previous backlight dimming techniques, which have ignored the temporal distortion effect

Predicting the residual energy of the battery source that powers a portable electronic device is imperative in designing and applying an effective dynamic power management policy for the device. This paper starts up by showing that a 30% error in predicting the battery capacity of a lithium-ion battery can result in up to 20% performance degradation for a dynamic voltage and frequency scaling algorithm. Next, this paper presents a closed form analytical expression for predicting the remaining capacity of a lithium-ion battery. The proposed high-level model, which relies on online current and voltage measurements, correctly accounts for the temperature and cycle aging effects. The accuracy of the high-level model is validated by comparing it with DUALFOIL simulation results, demonstrating a maximum of 5% error between simulated and predicted data.

In this paper, we present a new performance-driven multilevel partitioning algorithm, which calculates the timing gain of a move in the move-based partitioning strategies based on the aggregation of preferred signal directions. In addition, we propose a new timing-aware multilevel clustering algorithm that uses the connection strength of an edge as the primary objective, and the maximum depth or the maximum hop-count of any path containing the edge as a tiebreaker for the clustering step. These ideas are integrated into a general multilevel partitioning framework, which consists of three phases: uncoarsening, initial partitioning, and coarsening and refinement phases. The benchmarks show that, on average, we can reduce delay by 14.6%, while increasing the cutsize by 1.2% when compared to hMetis[1].

In this paper, we present area and performance-driven clustering techniques for coarse-grained, antifuse-based FPGAs. A macro logic cell in this class of FPGAs has multiple inputs and multiple outputs. Starting with this macro cell, a library of small logic cells can be generated and a target network was mapped with the library. For the minimum-area clustering, our algorithm minimizes the number of required macro logic cells to cover a network. Two linear equations were set up and we found the optimal mapping solution by using the equations. For the performance-driven clustering, the number of macro logic cells on the critical path is minimized by using the extension of Lawler's algorithm. The results show that the area-driven clustering algorithm reduced the number of macro logic cells by 12.29% and the performance-driven clustering reduced the maximum depth by 44.75% compared to a commercial tool.

The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in wrong values being latched in the circuit registers. We propose a design methodology for limiting the maximum value of the supply/ground currents to a user-specified threshold level while minimizing the wake up (sleep to active mode transition) time. In addition to controlling the sudden discharge of the accumulated charge in the intermediate nodes of the circuit through the sleep transistors during the wake up transition, we can eliminate short circuit current and spurious switching activity during this time. This is in turn achieved by reducing the amount of charge that must be removed from the intermediate nodes of the circuit and by turning on different parts of the circuit in a way that causes a uniform distribution of current over the wake up time. Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a one to two orders of magnitude improvement in the product of the maximum ground current and the wake up time.

An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for computing the proposed canonical form is provided. The efficiency of the algorithm allows it to be applicable to large complex Boolean functions with no limitation on the number of input variables as apposed to previous approaches, which are not capable of handling functions with more than seven inputs. Generalized signatures are used to define and compute the canonical form while symmetry of variables is used to minimize the computational complexity of the algorithm. Experimental results demonstrate the efficiency and applicability of the proposed canonical form.

This paper proposes an approach for pixel transformation of the displayed image to increase the potential energy saving of the backlight scaling method. The proposed approach takes advantage of human visual system characteristics and tries to minimize distortion between the perceived brightness values of the individual pixels in the original image and those of the backlight-scaled image. This is in contrast to previous backlight scaling approaches which simply match the luminance values of the individual pixels in the original and backlight-scaled images. Moreover, the proposed dynamic backlight scaling approach, which is based on tone mapping, is amenable to highly efficient hardware realization because it does not need information about the histogram of the displayed image. Experimental results show that the dynamic tone mapping for backlight scaling method results in about 35% power saving with an effective distortion rate of 5% and 55% power saving for a 20% distortion rate.

In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display. This is achieved by finding a pixel transformation function, which maps the original image histogram to a new histogram with lower dynamic range. Next the contrast of the transformed image is enhanced so as to compensate for brightness loss that would arise from backlight dimming. The proposed approach relies on an accurate definition of the image distortion which takes into account both the pixel value differences and a model of the human visual system and is amenable to highly efficient hardware realization. Experimental results show that the histogram equalization for backlight scaling method results in about 45% power saving with an effective distortion rate of 5% and 65% power saving for a 20% distortion rate. This is significantly higher power savings compared to previously reported backlight dimming approaches.

A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Conventional STA tools represent a waveform by its arrival time and slope. However, this is not an accurate way of modeling the waveform for the purpose of noise analysis. The key contribution of our work is the development of a method that allows efficient propagation of equivalent waveforms throughout the circuit. Experimental results demonstrate higher accuracy of the proposed sensitivity-based gate delay propagation technique, SGDP, compared to the best of existing approaches. SGDP is compatible with the current level of gate characterization in conventional ASIC cell libraries, and as a result, it can be easily incorporated into commercial STA tools to improve their accuracy.

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to statistical variations in the gate and wire delays. Statistical timing analysis techniques are being developed to tackle this important problem. In this paper, we propose a new framework for handling variation-aware interconnect timing analysis in which the sources of variation may have symmetric or skewed distributions. To achieve this goal, we express the resistance and capacitance of a line in canonical first order forms and then use these to compute the circuit moments. The variational moments are subsequently used to compute the interconnect delay and slew at each node of an RC tree. For this step, we combine known closed-form delay metrics such as Elmore and AWE-based algorithms to take advantage of the efficiency of the first category and the accuracy of the second. Experimental results show an average error of 2% for interconnect delay and slew with respect to SPICE-based Monte Carlo simulations.

We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the crosstalk effects in VLSI circuits. As example of these observations, we report that the combination of one crosstalk event at some site and another crosstalk event at a different site in the transitive fan-out of the first site may cause a slowdown or speedup of the circuit by an amount that can significantly exceed the sum of crosstalk effects caused by each site in isolation. As another example, we report that the common assumption that zero skew between the input transitions of aggressor and victim lines causes the worst case crosstalk effect is not always valid, and therefore, optimization or test based on such an assumption may be invalid. We also demonstrate the non-monotone behavior of the crosstalk effect with respect to the skew between the input transition of aggressor and victim lines. This work provides a first step toward the development of a new framework for timing analysis and test development in the presence of crosstalk events.

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to gate and wire variability. Therefore, statistical timing analysis is inevitable. Most timing tools divide the analysis into two parts: 1) interconnect (wire) timing analysis and 2) gate timing analysis. Variational interconnect delay calculation for block-based /spl sigma/TA has been recently studied. However, variational gate delay calculation has remained unexplored. In this paper, we propose a new framework to handle the variation-aware gate timing analysis in block-based /spl sigma/TA. First, we present an approach to approximate variational RC-/spl pi/ load by using a canonical first-order model. Next, an efficient variation-aware effective capacitance calculation based on statistical input transition, statistical gate timing library, and statistical RC-/spl pi/ load is presented. In this step, we use a single-iteration C/sub eff/ calculation which is efficient and reasonably accurate. Finally we calculate the statistical gate delay and output slew based on the aforementioned model. Experimental results show an average error of 7% for gate delay and output slew with respect to the HSPICE Monte Carlo simulation while the runtime is about 145 times faster.

This paper addresses the problem of maximizing the service lifetime of a distributed battery-powered sensor network in the context of the network interdiction problem under user-specified initial energy and probability of detection constraints. We consider a version of this problem where the probability distribution of selecting paths by the intruder is known to the interdictor. A two-step solution technique is proposed in whereby first the safeguarding constraints are satisfied and then the scheduling problem is solved. Experimental results demonstrate the effectiveness of the proposed two-step approach.

We consider the problem of energy efficient random deployment of sensor network. Our goal is to find the sensor node density, or alternatively, the energy resource density at every point inside a given deployment region, which results in allocating the minimum total number of deployed sensors, or alternatively, the minimum total energy source subject to constraints on the quality of monitoring (QoM) and network lifetime. The QoM is defined as the average of spatial distortion in reconstructed signal at the base station and can be bounded for a random deployment of sensor nodes when sensors are points of a Poisson process in the deployment region. To solve the optimization problem, we first determine a node density which satisfies the QoM constraint. Next we present a continuous space model for random deployment with the associated routing scheme that can be used to provide the minimum total required energy consumption. Finally, we present a spatial distribution of the sensor nodes (or the energy resources) that can achieve this minimum total energy. Simulation result shows that the minimum total energy obtained is close to the actual energy required in a randomly deployed dense network.

This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, power, and input capacitance, the fanout tree is converted to a set of inverter chains and for each chain the optimal sizes and threshold voltages are determined. Experimental results show that using this technique, the power dissipation of fanout tree is reduced by an average of 33% for a state-of-the-art CMOS technology.

We investigate and develop energy-efficient strategies for deployment of wireless sensor networks (WSN) for the purpose of monitoring some phenomenon of interest in a coverage region. We first describe a two-level WSN structure where the sensors in the lower level monitor their surrounding environment and the micro-servers in the top level provide connectivity between the sensors and a base station. We then formulate and solve the problem of assigning positions and initial energy levels to the micro-servers and concurrently partitioning the sensors into clusters assigned to individual micro-servers so as maximize the monitoring lifetime of the two-level WSN subject to a total energy budget. This problem, called MDEA, is solved for both collinear deployment and planar deployment situations. Our experimental results show that the design and deployment of such a two-level WSN increase the network lifetime by a factor of two or more compared to a flat WSN with the same total initial energy and quality of monitoring

This paper presented a hierarchical power management architecture which aims to facilitate power-awareness in an Energy-Managed Computer (EMC) system with multiple components. The proposed architecture divides PM function into two layers: system-level and component-level. The system-level hierarchical PM was formulated as a concurrent service request flow regulation and application scheduling problem. Experimental results showed that a 25% reduction in the total system energy can be achieved compared to the optimal component-level DPM policy.

Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot and, thus, adjust its voltage and frequency in order to save energy, while meeting soft timing constraints. This is, in turn, achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15% /spl sim/ 60% CPU energy saving was achieved at the cost of 5%-20% performance penalty.

Rapid technology scaling along with the continuous increase in the operation frequency cause the crosstalk noise to become a major source of performance degradation in high-speed integrated circuits. This paper presents an efficient metric to estimate the capacitive crosstalk in nanometer high-speed very large scale integration circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulsewidth, and the time-domain waveform of the crosstalk noise. Experimental results show that the maximum error of our noise predictions is less than 13%, while the average error is only 5.82%.

This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. This technique decomposes the workload for decoding a frame into on-chip and off-chip workloads. The execution time required for the on-chip workload is CPU frequency-dependent, whereas the off-chip workload execution time does not change, regardless of the CPU frequency, resulting in the maximum energy savings by setting the minimum frequency during off-chip workload execution time, without causing any delay penalty. This workload decomposition is performed using a performance-monitoring unit (PMU) in the XScale-processor, which provides various statistics such as cache hit/miss and CPU stall, due to data dependency at run time. The on-chip workload for an incoming frame is predicted using a frame-based history so that the processor voltage and frequency can be scaled to provide the exact amount of computing power needed to decode the frame. To guarantee a quality of service (QoS) constraint, a prediction error compensation method, called inter-frame compensation, is proposed in which the on-chip workload prediction error is diffused into subsequent frames such that run time frame rates change smoothly. The proposed DVFS algorithm has been implemented on an XScale-based Testbed. Detailed current measurements on this platform demonstrate significant CPU energy savings ranging from 50% to 80% depending on the video clip.

This paper presents a concurrent brightness and contrast scaling (CBCS) technique for a cold cathode fluorescent lamp (CCFL) backlit TFT-LCD display. The proposed technique aims at conserving power by reducing the backlight illumination while retaining the image fidelity through preservation of the image contrast. First, we explain how CCFL works and show how to model the non-linearity between its backlight illumination and power consumption. Next, we propose the contrast distortion metric to quantify the image quality loss after backlight scaling. Finally, we formulate and optimally solve the CBCS optimization problem with the objective of minimizing the fidelity and power metrics. Experimental results show that an average of 3.7X power saving can be achieved with only 10% of contrast distortion.

This paper presents an intra-process dynamic voltage and frequency scaling (DVFS) technique targeted toward non real-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically-constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot, and thus, adjust its voltage and frequency in order to save energy while meeting soft timing constraints. This is in turn achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15/spl sim/60% CPU energy saving was achieved at the cost of 5-20% performance penalty.

This paper presents a dynamic energy management policy for a wireless video streaming system, consisting of battery-powered client and server. The paper starts from the observation that the video quality in wireless streaming is a function of three factors: encoding aptitude of the server, decoding aptitude of the client, and the wireless channel. Based on this observation, the energy consumption of a wireless video streaming system is modeled and analyzed. Using the proposed model, the optimal energy assignment to each video frame is done such that the maximum system lifetime is achieved while satisfying a given minimum video quality requirement. Experimental results show that the proposed policy increases the system lifetime by 20%.