A new FFT architecture for real-time implementation of large FFTs is presented. The architecture supports both, high throughput and variable-length processing capabilities. The implementation is configurable at run-time, in order to compute power-of-two length ranging from 16 to 2n. It supports efficient integration of data scaling techniques. A radix-23DIT FFT algorithm is derived, which minimizes the number of multipliers and supports simple reordering.

This paper presents a forwarding-based approach to increase the code compaction and consequently the processing performance of VLIW media-processors that implement monolithic or partitioned register file (RF) organizations with reduced number of read/write ports. This approach exploits the forwarding mechanism implemented in common pipelined VLIW architectures to reduce the number of RF accesses, which is one of the main limiting factors of the code compaction process. This RF access reduction enables a higher instruction scheduling efficiency and eventually decreases the power consumption, without requiring extra hardware. A forwarding-sensitive code generation algorithm based on an enhanced list scheduling algorithm is described in detail. In addition, three case studies are presented, where the proposed scheduling algorithm leads to performance improvements of up to 8.4% when running common image and video codec tasks on a generic VLIW architecture. This is attractively close to the maximum performance improvement (11.4%) that can be achieved when investing in hardware by using a RF with twice the number of ports.

This paper presents a dedicated parallel hardware architecture for fast connected component labeling. Both, label generation and merging of equivalent labels are accelerated. Label generation is performed for four pixels in parallel. A special linked list based approach for fast label merging is proposed. This results in a compact implementation and shorter processing times compared to published implementations. For prototyping and evaluation purposes, the hardware architecture was integrated into an FPGA-based modular coprocessor architecture. A binary D1 test image is labeled in 1.74 ms on a Virtex-II Pro FPGA running at 140 MHz. Moreover, the architecture can be easily integrated into embedded image processing systems.

This paper describes a case study in a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The goal of the presented methodology is to speed up and improve the verification flow of a multiprocessor system that will finally be implemented as an ASIC. The case study consists of a 64-bit compatible AMBA AHB system bus which connects up to 14 32-Bit RISC processors to a host interface. A typical parallel computing application has been implemented for the parameterized multiprocessor system. The employed FPGA emulation environment increases by up to 200 the simulation frequency of the global system on a workstation (2.2 GHz AMD Dual Opteron with 8 GB RAM). Moreover a standalone emulation can be performed at the maximum achievable frequency (65 MHz).

Video encoding IP for home entertainment equipment and mobile devices is based on the same compression standards. However, performance and power efficient implementations for both application fields usually lead to independent hardware architectures and require separate implementation and maintenance. We introduce a new approach for a multi-standard texture encoder for MPEG and VC-1 compression standards. The data path based architecture has been designed for scalability of performance and chip size without the requirement of manual hardware modifications. Using the maximum supported number of eight data paths running at 108 MHz, the texture encoder is able to process Dl video sequences.

This paper presents a new H.264 motion estimation algorithm and architecture for video encoding. The algorithm resolves the sequential data dependencies of H.264 motion estimation by a new method, called "staggered approach". It adapts existing motion search methods (3DRS, hierarchical full search), maximizing parallel execution and allowing efficient pipelined execution while maintaining the high compression rate of H.264. Its regular and reduced-computation processing scheme makes the algorithm particularly suitable for high-performance hardware implementations, as required for realtime encoding of HDTV. The proposed motion estimator architecture demonstrates the suitability of the algorithm for cost-efficient consumer HDTV encoder chips

A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processor cores and various interfaces onto a single chip, all tied to a 64-bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 /spl mu/m 6LM standard-cell technology, occupies about 82 mm/sup 2/, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.

A new generation of on-board SAR processors for compact airborne systems is presented, which is currently under development at the Laboratorium fu/spl uml/r Informationstechnologie (LfI), Universita/spl uml/t Hannover. The processor uses the /spl omega/k-algorithm (also known as the wavenumber domain algorithm) and features region of interest support and source coding of the SAR images for further reduction of the output data rate. This is important for data transmission via radio data links. The hardware architecture of the SAR processor is based on the HiBRID-SoC, a new signal processor with three fully programmable cores. This SoC allows the mapping of the whole SAR processing chain to a single chip. This reduces the number of hardware components, which is important for the realization of compact and power efficient hardware design.

The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 /spl mu/m 6LM standard- cell technology, occupies about 82 mm/sup 2/, operates at 145 MHz, and consumes 3.5 Watts.

This paper describes the work in progress of the European IST-2001-34410 CAMELLIA project, which focuses on a platform-based development of a smart imaging core to be embedded in smart cameras. Therefore the work within the CAMELLIA project comprises the specification and implementation of smart imaging applications including the development of required new algorithms and hardware. Based on an existing video encoding architecture for MPEG-4 Simple Profile, the aim is to design a smart imaging core, which is suitable for automotive and mobile communication applications. Thereby the encoding architecture is to be extended with processing units for low- and mid-level smart imaging functions. To indicate the applicability of this platform-based development, a first approach for a motion estimation based background detection using a hardware motion estimation unit is illustrated in this paper. Furthermore, first results employing the background detection to detect moving objects in video sequences using a functional simulator of a video encoding architecture are presented.

This paper presents a Multi-DSP system for real- time SAR-processing using the HiPAR-DSP 16. We developed this full programmable processor at the Laboratorium f ¨ ur Informationstechnologie. With 16 parallel data paths and a two- dimensional memory it is optimized for image processing algo- rithms like FFT-transforms. SAR image synthesis methods, like the investigated ωk-algorithm, use the computational intensive FFT-transform. To overcome the large processing power of future realtime SAR image synthesis applications, several DSPs have to work in parallel. The presentedcompact SAR system can be easily adapted to match the demands of different SAR algorithms by scaling the number of processing nodes. Equiped with 6 HiPAR-DSP 16 a 233x175x15 mm 3 boardprovid es a realtime capability of processing SAR applications with a PRF of 1200 Hz. A rangeline length of 4096 8 bit complex samples and 4096 rangelines is assumed. The small volume and it's power consumption of less than 35 W enables it for on-boardusage in compact air- or spaceborne systems.

The presented HiPAR-DSP is a highly parallel DSP core for system on a chip video- and image processing applications. The architecture is based on an array of up to 16 parallel data paths steered by a single RISC controller in SIMD style. Each data path consists of three VLIW controlled arithmetical units: a 16 bit MAC and 32 bit ALU and shift & round units. A divided memory concept serves local caches for each data path as well as a special shared matrix memory which enables concurrent access from all data paths in every clock cycle. External connection can be provided via a modular DMA controller which enables an easy interfacing to other on chip modules. The HiPAR-DSP core has been manufactured in the most powerful version with 16 data paths in second Quarter 2001 and delivers with a maximum clock frequency of 100 MHz 4.8 GOPS peak and about 3 GOPS sustained performance. In addition to the core architecture the paper will also present the software development system for the HiPAR-DSP including C/C++ compiler, assembler, simulator and a PCI board with onboard video I/O interfaces.

A methodology for performance estimation of streaming media applications on different implementation platforms is presented. The methodology derives a complexity profile for an application as a platform-independent metric, and enables performance estimation on different platforms by correlating the complexity profile with platform-specific data. By example of an MPEG-4 advanced simple profile (ASP) video decoder, performance estimation results are presented for different platforms, including general-purpose processors and specialized architectures. As one particular benefit, the approach can be employed to assist in design decisions in the specification phase of new architectures.

At the University of Hannover a fully programmable DSP, the HiPAR-DSP 16, was developed. This HiPAR-DSP 16 contains 16 parallel datapaths and a 2-dimensional memory adapted to image processing algorithms. For real time SAR processing high computational power is required. Therefore a multi DSP board with 6 HiPAR-DSP 16 is developed. The high performance of up to 28 GOPS enables a SAR processing in real time. The calculation time for the wk-algorithm running on this board was estimated. For blocks of 4096 lines with 4096 8 bit complex samples real time processing is possible to a pulse repetition frequency (PRF) of 1200 Hz. Due to a low power consumption and the small size of 160/spl times/230 mm/sup 2/ of this board the use in on-board systems is predestinated.

The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video.

A programmable processor architecture for MPEG-4 video is proposed, that can serve as a co-processor module in MPEG-4 decoder systems. it consists of a 64-bit dual-issue VLIW macroblock engine, a separate RISC core for bitstream parsing and system processing, and an autonomous I/O processor. A separate DSP is used for MPEG audio support. The architecture is fully programmable and supports parallelism on data-, instruction- and thread-level to cope with the high flexibility and processing demands of the MPEG-4 standard. The first implementation will support realtime decoding of MPEG-4 advanced simple profile or of MPEG-4 ACE-profile (CCIR601, single-object). Future designs will add support for object-based MPEG-4 functionalities. The paper focuses on the architecture, instruction set, and performance of the macroblock engine, which operates as an autonomous co-processor and carries most of the workload in MPEG-4 video processing.. It has a RISC-based architecture with support for parallel processing of instructions and data. Special instructions are implemented with specific support for video processing.

With new tools for advanced coding efficiency, such as global motion compensation and quarter-pel motion compensation, the newly defined visual MPEG-4 Advanced Simple (AS) Profile targets in particular the increasingly important field of streaming video applications in the promising 1–2 MBit/s range. Based on an analysis of MPEG-4 AS profile bitstream statistics, the implementation on a programmable multimedia processor platform is described, achieving real-time decoding performance for ITU-R 601 resolution video.

The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-lime. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or software support for different video-formats. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 /spl mu/ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm/sup 2/ overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (CCIR).

The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 /spl mu/ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm/sup 2/ overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (CCIR).

M-PIRE is a programmable MPEG-4 multimedia codec VLSI for mobile and stationary applications. It integrates a RISC core, two separate DSPs, a 64-bit dual-issue VLIW macroblock engine, and an autonomous I/O processor on a single chip to cope with the high flexibility and processing demands of the MPEG-4 standard. The first M-PIRE implementation will consume 90 mm/sup 2/ in 0.25 /spl mu/ CMOS technology. It will support real-time video and audio processing of MPEG-4 simple profile or ITU H.26x standards; future designs of M-PIRE will add support for higher MPEG-4 profiles. This paper focuses on the architecture, instruction set, and performance of M-PIRE's macroblock engine, which carries most of the workload in MPEG-4 video processing.

A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

This paper proposes a new array architecture for MPEG-4 image compositing and 3D rendering. The emerging MPEG-4 standard for multimedia applications allows VRML-like script-based compositing of audio-visual scenes from multiple audio and visual objects. MPEG-4 supports both natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video and audio-decoder and a floating-point geometry-processor. It performs computation and bandwidth intensive low-level tasks for image compositing and rasterization. The processor consists of a SIMD array of 16 identical DSPs to reach the required processing power for real-time image warping, alpha-blending, z-buffering and phong-shading. The processor has an object-oriented parallel cache architecture with 2D virtual address space (e.g. textures) that allows concurrent and conflict-free access to shared image data objects for all 16 DSPs.

The video signal processor AxPe1280V has been developed forimplementation of different video coding applications accordingto standards like ITU-T H.261/H.263, and ISO MPEG-1/2.Itconsists of a RISC processor supplemented by a coprocessor forconvolution-like low-level tasks.RISC and coprocessor have beenimplemented in a standard cell design combined with full-custommodules.The processor was fabricated in a 0.5 µm CMOS technologyand has a die size of 82 mm{2}.It provides a peak performanceof more than 1 giga arithmetic operations per second (GOPS) at66 MHz.For processing of very computation-intensive algorithmsor high data rates, several processors can be bus-connected to forma MIMD multiprocessor system.

Architecture and design of the HiPAR-DSP, a SIMD controlled signalprocessor with parallel data paths, VLIW and novel memory design.The processor architecture is derived from an analysis of thetarget algorithms and specified in VHDL on register transfer level.A team of more than 20 graduate students covered the whole designprocess, including the synthesizable VHDL description, synthesis,routing and backannotation as the development of a complete softwaredevelopment environment.The 175mm{2}, 0.5µm 3LM CMOSdesign with 1.2 million transistors operates at 80 MHz and achievesa sustained performance of more than 600 million arithmetic operations.

This paper proposes a new array architecture for MPEG-4 image compositing. The emerging MPEG4 standard for multimedia applications allows script-based compositing of audiovisual scenes from multiple audio and visual objects. MPEG-4 supports both, natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated, e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video- and audio-decoder, and performs computation and bandwidth intensive low-level tasks for image compositing. The processor consists of an SIMD array of 16 DSPs to reach the required processing power for real-time image warping, alpha-blending and 3D rendering tasks. A programmable architecture allows one to adapt the processing resources to the specific needs of different tasks and applications. The processor has an object-oriented cache architecture with 2D virtual address space (e.g. textures), that allows concurrent and conflict-free access to shared data objects for all 16 DSPs. Especially I/O intensive tasks like texture-mapping, alpha-blending, image warping, z-buffer and shading algorithms benefit from shared memory caches and the possibility to preload data before it is accessed.

An overview of very large scale integrated (VLSI) implementations of multimedia processing systems is given with particular emphasis on architectures for image and video processing. Alternative design approaches are discussed for dedicated image and video processing circuits and for programmable multimedia processors. Current design examples of dedicated and programmable architectures are reviewed, and the techniques employed to improve the performance for multimedia processing are therein identified. Future trends in multimedia processing systems are anticipated with respect to current developments in emerging image and video multimedia applications.

We propose a novel stochastic approach for the problem of multiprocessor scheduling and allocation under timing and resource constraints using an evolutionary algorithm (EA). For composite schemes of DSP algorithms a compact problem encoding has been developed with emphasis on the allocation/binding part of the problem as well as an efficient problem transformation-decoding scheme in order to avoid infeasible solutions and therefore time consuming repair mechanisms. Thus, the algorithm is able to handle even large size problems within moderate computation time. Simulation results comparing the proposed EA with optimal results provided by mixed integer linear programming (MILP) show, that the EA is suitable to achieve the same or similar results but in much less time as problem size increases.

A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of instruction level parallelism decreases in efficiency as the degree of parallelism increases. This is mainly caused by algorithm characteristics, VLSI design and compiler restrictions. We discuss selected aspects from these fields and possible solutions to upcoming bottlenecks from a practical point of view.

This paper presents a system level design methodology and its implementation in a CAD tool for the optimization of video signal processor (VSP) architectures. These VSPs, consisting of dedicated as well as programmable modules, are highly suitable for performing composite schemes of image processing algorithms under real time constraints, whereas the optimization aims at the most suitable combination of dedicated and programmable modules for the overall system. Nevertheless, in order to apply optimization techniques, it is mandatory to estimate a set of performance measures like execution time and area expense for each module in advance. Based on these performance measures estimated for a finite set of dedicated and programmable modules, the optimization can be carried out. By using mixed integer linear programming as the optimization framework, VSP architectures can be derived, being optimal in terms of chip area and throughput rate.

For the design of a highly parallel programmable video signal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP, has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.

The architecture of dedicated MPEG2 HDTV-decoders for stand-alone and hierarchical transmission has been investigated. The high demands on the video memory in terms of memory capacity and data rate are met by using synchronous DRAMs and adapting the data accesses to the properties of the memory devices. Thus compact implementations for consumer and professional decoders become possible.

The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.>

A data path array has been designed as core of a digital signal processor architecture for image processing applications. Data supply to data paths and exchange of data among data paths is performed via an on-chip shared memory with two-dimensional address space. Distribution of data onto these memory blocks enables simultaneous, conflict-free access to the shared memory by the data paths. Data that is accessed concurrently is addressed in shape of a generalized matrix i.e. a two-dimensional array with address-offsets between neighbors. Additionally, each data path has autonomous addressing capabilities to a distributed local cache memory. The combination of shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerful core of a high-performance DSP, that is completed by a RISC-style controller and a DMA-unit for data transfer. Simulation results proved, that the processor will show high performance on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4/spl times/4 array, the processor will perform a 1024 samples complex FFT within 33 /spl mu/s including data I/O. The Hough transform of a 512/spl times/512 pel image with 30% black pels is performed within 66 ms, assuming 7 bit quantization for the angle and 11 bit quantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).>

A heterogenous processor architecture for video coding applications based on hybrid coding schemes is proposed. To support high computational power and architectural flexibility, the processor consists of function oriented and programmable modules. The key components of the architecture are a RISC core which performs control tasks and module synchronisation, a programmable module for tasks like DCT, quantization and filtering and a function oriented blockmatching module for motion estimation. Applying a 0.6 micron CMOS process, a single chip video codec for CIF-30 Hz video signals can be implemented. For higher video source rates several processors can be combined to a multiprocessor system.>

The authors discuss the performance of multiprocessor architectures to be applied for video coding algorithms. SIMD, SIMD cluster, and MIMD architectures are studied by a unified performance approach under specific constraints of video coding algorithms. The proposed performance model considers communication and computation times as well as the required silicon area. MIMD architectures are compared to SIMD with regard to their performance. The optimization of architectural parameters for SIMD and MIMD architectures is discussed. It is shown how the proposed performance model can be applied to the design of VLSI-based multiprocessor systems for video coding.>

An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of two hundred and fifty-six taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines and implemented special processing of frames borders. Defect tolerance e.g. reconfiguration is implemented in order to enhance yield and reliability especially for future large area implementations.>

The hardware implementation of a DPCM coding algorithm with 2D prediction, noise shaping and fixed codeword length for the transmission of HDTV signals with 560 Mbit/s bit rate has been investigated. In order to reduce timing requirements an architecture with parallel processing elements and with modified DPCM-structure is proposed. DPCM and FIFO circuits as major components for such a codec have been designed for a VLSI-realization using 1.2|im CMOS technology.

Architectures for the realization of block matching algorithms are discussed, with emphasis on highly concurrent systolic array processors. A mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of two-dimensional and one-dimensional systolic arrays are presented. The required transistor count and the maximum frame rate for real-time processing of video telephone and TV signals using currently available CMOS technology are estimated.>

This paper presents a review of the advances in digital coding of video signals during the last four years. Displacement estimation algorithms for coding applications are compared first and the relationship between the algorithms is pointed out. The developments in predictive and transform coding are described and discussed with view to broadcast television and video-conferencing applications. One chapter summarizes the first promising results of motion adaptive frame interpolation. Some problems to be solved in the future are pointed out in the conclusions.

Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.

Differential pulse code modulation (DPCM) systems, used for encoding signals, are recursive and exhibit instability under certain conditions. In this paper, sufficient conditions for asymptotic stability of multidimensional DPCM systems are obtained both in the signal domain and the transform domain. In the case of instability, certain kinds of limit cycles, necessary conditions for their suppression are derived. The stability conditions are evaluated for one-, two-, and three-dimensional predictors.

The application of differential pulse code modulation (DPCM) for broadcast color television signals requires a design which produces no visible impairments under normal viewing conditions. This paper describes a quantizer design which is based on measured visibility thresholds of the various kinds of DPCM impairments such as granular noise, edge busyness, and slope overload. The visibility thresholds are determined by subjective tests based on comparisons of DPCM and PCM encoded pictures. Constructions of quantizers are carried out such that the number of levels is minimized without exceeding the measured visibility thresholds. Besides nonadaptive quantizers, adaptive quantizers are also constructed which are controlled by the signal changes of surrounding picture elements. These investigations show that for component coding of color video signals with two-dimensional prediction, a transmission rate of 31.7 Mbits/s is possible for natural types of test pictures without visible impairments using constant word length coding.