When a single bit is flipped as a result of a transient error in an electronic circuit, its effect can have a severe impact if the circuit is deployed in safety critical domains such as automotive, aeronautics, and industrial automation. In the design phase it is therefore essential to evaluate, and where necessary improve, the resilience of a circuit to all possible transient errors. In this paper, we present a method to analyze the transient error resiliency of a digital circuit. This method is based on an analytical model. It models a transient error as a random function and finds the vulnerable number of bits for each node. We perform a case study on a circuit implementation of a well-known adaptive filter algorithm. The results from the analytical and simulation models show that the analytical model is accurate enough to estimate the effects of transient errors on the performance of a digital circuit. Our analytical method also reduces the analysis time significantly in a design phase.

This paper is about a single event upset resilient logic design optimization technique for sub-100nm technology nodes. The proposed technique can be used for both combinational as well as sequential circuits. In order to make a logic circuit robust for a transient error, the well known gate sizing technique is used. A 65nm inverters based master slave flip flop is considered for the case study. The result shows a trade off between the robustness and the performance (power consumption and operational speed) while performing design optimization for a single event upset. Furthermore, it shows that the width of devices cannot be increased arbitrarily in order to make a flip flop resilient since it can result in timing violation. The proposed design optimization technique incorporates the timing aspects and finds the optimal widths that make a gate robust against a single event upset.

A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. In a real-time embedded system, task arrival rate, inter-task arrival time, and data size to be transferred are not uniform over time. This is due to the partial re-configuration of an embedded system to cope with dynamic workload. In this context, the traditional application specific bus architectures may fail to meet the real-time constraints. Thus, to incorporate the random behavior of on-chip communication, this work proposes an approach to synthesize an on-chip bus architecture, which is robust for a given distributions of random tasks. The randomness of communication tasks is characterized by three main parameters which are the average task arrival rate, the average inter-task arrival time, and the data size. For synthesis, an on-chip bus requirement is guided by the worst-case performance need, while the dynamic voltage scaling technique is used to save energy when the workload is low or timing slack is high. This, in turn, results in an effective utilization of communication resources under variable workload.

In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different amount of slacks to them during co-synthesis. The method finds a balance of slack allocation for both bus and memory optimization. While the previous co-synthesis approaches do not consider the slack allocation technique, the synthesized bus and memory architectures will not be optimal in terms of area and energy consumption. The experimental results carried out on real-life applications show 19% and 24% reduction in bus and memory area, respectively and 37% reduction in energy overhead due to a bridge in compared to the previous co-synthesis approach.

Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scaling indicates that the wires are getting thinner and results in an increment of wire delay and power consumption. These, in turn, result in the degradation of both device reliability and system performance. As the process technology is scaled down, the effects of process variation are becoming significant on system performance. In order to incorporate the combined effects process variations on the performance of on-chip bus architecture, this work proposes a technique to synthesize an energy conscious robust on- chip bus architecture. The proposed model simultaneously performs on- chip bus synthesis and voltage scaling under both data size and process parameters variations. The problem is relaxed to a nonlinear optimization model, which synthesizes an energy conscious optimal bus widths and the number of buses considering worst case data traffic and process variations. The experimental results show that applying voltage scaling during the synthesis of on-chip bus effectively reduces the dynamic power consumption, leakage power consumption, and mitigates the effects of process variations.

The advancement in process technology has made it possible to integrate multiple processing modules on a single chip. As a result of this, there is a sharp increase of communication traffic on the communication bus architecture. In this case, the traditional single bus based architecture may fail to meet the real-time constraints. The major concern of the scaled technology is an effect of coupling capacitance due to the trend of shrinking pitches, i.e., the distance between two wires. Its consequence is higher crosstalk noise, which degrades the signal integrity and modifies the power consumption of the wires. This motivates the synthesis of a custom on-chip bus architecture, which is efficient in terms of power and performance. Further, the memory of a complex multiprocessor system has a significant contribution to power and delay. In this paper, we present a co-synthesis of on-chip buses and memories, which finds an optimal bus architecture, memory sizes, and the number of memories. The bus synthesis problem is formulated as an optimization problem as proposed in [11], [9]. Then it is solved efficiently using an optimization tool. The memory synthesis problem is based on the graph partitioning algorithm, which partitions a data dependency task graph into a set of sub graphs with the minimum number of data dependencies called cut. The experiments carried out on the real-life multimedia applications validate the proposed technique for the co-synthesis of bus architecture and memory.

This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules of a system-on-chip (SoC). Because of the diversity of applications to be run on a single SoC, there exists a variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a random variable with a known distribution function. The resulting synthesis problem is relaxed to a convex quadratic optimization problem and solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By scaling voltage of a bus, a tradeoff between communication bus cost (bus width and the number of buses) and energy reduction is explored. The experimental results show the significant reduction in communication energy with scaling voltage. However, it offers a limitation to minimize the communication bus cost, if the voltage is scaled beyond its minimum limit. Furthermore, we also estimate the distribution of voltage under a random data size using an analytical method and the Monte Carlo simulation. The results show that the analytically estimated statistical parameters of voltage are close to the simulated results.

We propose a statistical approach for minimizing on-chip communication bus width and number of buses with reduced communication energy under timing yield constraint. The slack is exploited to maximize sharing of buses and to reduce energy by simultaneously scaling the voltage during the communication synthesis. Because of the diversity of applications to be run on a single SoC, there exists variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a normally distributed random variable. The resulting synthesis problem is relaxed to the convex quadratic optimization problem and is solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By varying the value of timing yield constraint, a trade-off between minimization of buses and energy reduction is explored. The experimental results show the significant reduction of communication energy with the increasing timing yield. However, the timing yield offers a limitation to minimize the size of bus width and number of buses, if the yield is increased beyond a certain limit.

In a reconfigurable computing system, some of the on-chip modules can be configured partially to run several applications in a single chip. Due to this feature of partial reconfiguration, the size of data to be transferred among the on-chip modules is random in nature. This paper proposes a method to synthesize an energy efficient on-chip communication bus width and number buses for a reconfigurable architecture. The randomness of data for such an architecture is modeled as a normally distributed random variable. The slack is exploited to maximize sharing of buses and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of communication bus. The resulting synthesis problem is relaxed to the quadratic optimization problem and is solved efficiently using a convex optimization tool. The experimental result shows the synthesis of bus width and number of buses with reduced communication energy for different variability of data size.

This paper presents an energy efficient on-chip communication synthesis for shared bus based architecture. An assumption for the synthesis is that a system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. The problem of communication synthesis is modeled in NLP (nonlinear programming), which finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The supply voltage is scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 44.6% by scaling its supply voltage

Due to shrinking process geometries and an increasing number of chip components in very deep sub-micron technologies, interconnects emerged as a main limiting factor for performance, die area, and power consumption. Buffer allocation, interconnect congestion, power dissipation in buffered interconnects pose tremendous difficulties on the design process. It is therefore of paramount importance to address interconnect and buffer planning at early stages in the design flow, especially from the perspective of power consumption and thermal management. The goal of this work is to indicate the remarkable opportunities in reducing power consumption in buffered interconnects during placement, and to extend a classical placement algorithm to include power-optimized interconnect and buffer planning. The authors merge a placement algorithm based on simulated annealing with A-tree construction, van Ginneken's buffer insertion algorithm, and accurate moment-based delay computation. The authors show that dramatic improvements can be achieved in terms of total interconnect structure capacitance and total area of required buffers

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

This paper presents a method of on-chip communication bus topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We define the problem of on-chip communication topology synthesis into two main problems namely scheduling and allocation binding problem. The communication behavior of each module is modeled as a set of communication lifetime intervals (CLTIs), which are evaluated and scheduled for different size of bus width to get the minimum number of overlaps, minimum size of bus width and the minimum number of bus(es) using tabu search method. These optimized CLTIs are given to the clique partitioning algorithm as an allocation-binding problem to synthesize the communication topology

This paper presents a method of on-chip commaunication topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. These optimized CLTIs are later given to the communication topology synthesis algorithm, which gives the number of buses and their interconnection. The results of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrate the utility of our techniques to synthesize a custom on-chip shared multibus based communication architecture for a complex system.