This work presents a 2-MS/s 18-bit successive-approximation-register analog-to-digital converter (ADC). Acapacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) are cascaded to avoid the linearity limitation caused by parasitic capacitors on the bridge capacitor between the CDAC and the RDAC. An optimal-combination-algorithm (OCA)-based calibration is adopted to improve the linearity of the CDAC and the matching between CDAC and the bridge capacitor, and a least significant bit (LSB)-side dynamic element matching (DEM) strategy is applied to further improve the CDAC linearity. As for the RDAC, this work makes it calibration free by combining the parallel R-unit and R-2R topology. Measurement results show that the proposed ADC can achieve 91.4-dB signal-to-noise and distortion ratio (SNDR), 12.0-parts-per-million (ppm) (3.1-LSB) integral non-linearity (INL), and 174.0-dB FOMS,SNDR(including the power consumed by the calibration logic), and the worst-case INL across 25 dies improves from 72.5ppm (19.0LSB) to 18.8ppm (4.9LSB) after the OCA-based calibration and theLSB-side DEM. To the best of the authors’ knowledge, this is the first high-precision (resolution$\geq 16$bit) data converter adopting OCA-based calibration.

This demo shows a toolbox for the optimization and automated high-level design of Analog-to-Digital Converters (ADCs). The tool integrates Artificial Neural Networks (ANNs) with behavioral simulation to optimize the high-level sizing process, mapping system-level specifications to building-block requirements. ANNs are trained to determine the optimal ADC architecture based on given specifications, as well as the ideal set of design parameters that meet these requirements. The ANN-generated designs are refined through iterative simulations to achieve the best figure of merit. The toolbox, applied to Sigma-Delta Modulators (Σ∆Ms), features a Graphical User Interface (GUI) implemented in MATLAB, which guides users through the entire process—from specifications to verification1

This demo shows how to use the You Only Look Once (YOLO) version 8 framework to identify radio-frequency (RF) signals for spectrum sensing in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, a trained YOLOv8 nano framework was embedded in an IoT device based on a Raspberry Pi 5 and connected to an ADALM-PLUTO SDR board to detect and classify the activity of RF frames around the industrial, scientific, and medical (ISM) frequency band. This framework detects wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real-time and can detect RF frames showing its potential application in SDR/CR terminals1.

This paper presents a Radio-Frequency (RF) spectrum prediction system based on a Convolutional Neural Network (CNN) architecture for image-based forecasting intended for Cognitive Radio (CR) terminals. Compared to previous approaches based on the use of time series, we propose a more efficient way for occupancy spectrum prediction based on channel availability tables (derived from spectrograms) to train a deep learning model. As a result, the neural engine is able to predict the best band available for Secondary User (SU) transmission in edge devices. As a proof of concept, a simple CR demonstrator combining a computational model for the neural engine – previously modeled and trained in Python using the Keras API – in MATLAB/SIMULINK with two Software-Defined Radio (SDR) boards has been developed. Three different table sizes were used as input for the predictor and a comparison is presented. The system performance is assessed using real over-the-air signals captured in the 2.412 GHz central frequency with 60 MHz bandwidth to validate the presented approach1.

This demo shows how to use Artificial Neural Networks (ANNs) for the optimization and automated design of analog and mixed-signal circuits. A step-by-step procedure is demonstrated to explain the key and practical aspects to consider in this approach, such as dataset preparation, ANNs modeling, training, and optimization of network hyperparameters. Two case studies at different abstraction levels are presented. The first one is the system-level sizing of Sigma-Delta Modulators (Σ∆Ms), where ANNs are combined with behavioral simulations to generate valid circuit-level design variables for a given set of specifications. The second example combines ANNs with electrical simulators to optimize the circuit-level design of operational transconductance amplifiers. The methods and tools shown in the demo can be used for the optimization of any arbitrary analog and mixed-signal integrated circuits and systems1.ISCAS Track: Analog Signal Processing.

This demo shows how to use Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum with application in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, different kinds of ANNs – including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them – are trained and tested with experimental datasets taken from measurements of the frequency spectrum. Trained ANNs are embedded in an IoT device based on a Rasperry Pi and connected with a SDR board to detect the activity of Radio-Frequency (RF) signals around the frequency band of 2.4GHz, shared by several wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real time and is able to detect in advance which portions of this frequency band will be less occupied, thus showing their potential application in SDR/CR terminals1.ISCAS Track: Analog Signal Processing.

This paper presents a high-level synthesis methodology for Sigma-Delta Modulators ($\SD$Ms) that combines behavioral modeling and simulation for performance evaluation, and Artificial Neural Networks (ANNs) to generate high-level designs variables for the required specifications. To this end, comprehensive datasets made up of design variables and performance metrics, generated from accurate behavioral simulations of different kinds of$\SD$Ms, are used to allow the ANN to learn the complex relationships between design-variables and specifications. Several representative case studies are considered, including single-loop and cascade architectures with single-bit and multi-bit quantization, as well as both Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques. The proposed solution works in two steps. First, for a given set of specifications, a trained classifier proposes one of the available$\SD$M architectures in the dataset. Second, for the proposed architecture, a Regression-type Neural Network (RNN) infers the design variables required to produce the requested specifications. A comparison with other optimization methods – such as genetic algorithms and gradient descent – is discussed, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics and CPU time.

This paper presents a new architecture for bandpass delta-sigma modulators (BP$\Delta \Sigma $Ms) featuring finite impulse response (FIR) filters in the feedback path. The effectiveness of FIR feedback in lowpass delta-sigma modulators (LP$\Delta \Sigma $Ms) has been well-established in improving loop-filter linearity and robustness to clock jitter. Building upon these findings, we explore the application of bandpass FIR filters in single-bit BP$\Delta \Sigma $Ms. By contrast to conventional BP$\Delta \Sigma $Ms, the proposed technique significantly reduces out-of-band quantization error contents in the feedback signal. This approach is applicable to both discrete-time and continuous-time implementations. Further, we show that performance does not improve by increasing the number of FIR taps beyond a certain point. However, we can enhance filtering performance by employing non-equal coefficients within the filter. To validate the efficacy of the presented approach, the paper includes electrical simulation of a 4th-order active-RC BP$\Delta \Sigma \text{M}$.

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.

Dear readers, it is a great honor and privilege for me to start my two-year term of duty as Editor-in-Chief (EiC) of IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) and I am very thankful to the IEEE Circuits and Systems Society (CASS) for giving me this opportunity. Throughout my career, I have served IEEE-CASS in several positions, including technical and organizing committees of flagship conferences, a Distinguished Lecturer, the Chair of the Spain Chapter, and more recently as a Memberat- Large of the Board of Governors. Since 2012, I have been a member of the editorial boards (EBs) of the TCAS-I and IEEE Transactions on Circuits and Systems—II: Express Briefs (TCSA-II), being the EiC of IEEE TCAS-II during the term 2020–2021.

This paper analyses the use of Artificial Neural Networks (ANNs) for the high-level synthesis and design of Sigma-Delta Modulators$(\Sigma\Delta\text{Ms})$. The presented methodology is based on training ANNs to identify optimum design patterns, so that they can learn to predict the best set of design variables for a given set of specifications. This strategy has been successfully applied in prior works to design basic analog building blocks, and it is explored in this work to automate the high-level sizing of$\Sigma\Delta\text{Ms}$. Several$\Sigma\Delta\mathrm{M}$case studies, which include both single-loop and cascade topologies as well as Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques are shown. The effect of ANN hyperparameters - such as the number of layers, neurons per layer, batch size, number of epochs, etc. - is analyzed in order to find out the best ANN architecture that finds an optimum design with less computational resources. A comparison with other optimization methods - such as genetic algorithms and gradient descent - is shown, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics, power consumption and CPU time11This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by “Junta de Andalucía” under Grant P20-00599.

This paper investigates finite impulse response (FIR) feedback in bandpass delta-sigma modulators (BP-$\Delta \Sigma \text{Ms}$). FIR feedback in lowpass delta-sigma modulators (LP-$\Delta \Sigma \text{Ms}$) improves loop filter linearity and reduces the sensitivity of the modulator to clock jitter. We show that similar benefits can be obtained in a BP-$\Delta \Sigma \mathrm{M}$if the FIR filter in the feedback path is made a bandpass one11This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by “Junta de Andalucía” under Grant P20-00599 and in part by the Center of Excellence in RF, Analog and Mixed-Signal ICs (CERAMIC), IIT Madras..

A 12-bit low-power SAR ADC with low-input capacitance is proposed. The topology exploits a structure with separate sample & hold and DAC blocks, separated block SAR, to achieve low-input capacitance. In this structure, the comparator input common-mode voltage is variable and, therefore, a rail-to-rail comparator with rail-to-rail offset cancellation is proposed to cancel the input common-mode dependent offset. The proposed comparator is modified to overcome the uneven distribution of kickback noise too. In order to achieve a 12-bit resolution, the bootstrapped switch is modified. With the aid of the proposed offset cancellation, kickback noise reduction, and switch, the ADC achieves 11.08-bit ENOB and the input capacitance is reduced to 2 pF, leading to relatively low input power consumption with no need for a reference supply voltage.

This paper gives an overview of Cognitive-Radio (CR) circuits and systems, that will enable the implementation of new technology paradigms such as software-defined electronics and Artificial Intelligence (AI) managed Internet-of-Things (IoT). A survey of the state of the art, trends and design challenges is presented from a top-down perspective - from system-level to circuit and chip implementation. As an application, special emphasis is put on analog/digital interfaces as one of the key building blocks in CR-based devices. Cutting-edge architectures - mostly based on ΣΔ Modulators (ΣΔMs) - are discussed, as well as the best candidate circuit strategies to implement CR- based digitizers in deep nanometer CMOS.

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

Radio-Frequency (RF) filters are one of the key components in the front-end of wireless transceivers that can be miniaturized in order to develop cost and power efficient reconfigurable mobile terminals as those required in next generations (5G/6G) of telecom systems. However, several factors need to be investigated in order to implement multi-standard/multi-mode devices in practice. One of the critical limitations is the deviations of basic performance metrics due to fabrication process variations and effect of parasitic circuit elements. In this context, a parametric analysis on a miniaturized capacitor-loaded broadside-coupled split-ring-resonator filter in sub-6GHz band is presented in this paper. Physical and parasitic effects like substrate thickness, capacitor equivalent series resistance and capacitance variation are analyzed against the filter performance. The effect of each of these parameters on the performance of RF filters is shown such that the solutions for these effects can be considered during mass manufacturing.

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

This paper investigates the use of the transistor threshold-voltage tuning feature available in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology in order to improve the performance of Voltage-Controlled Oscillators (VCOs) with application in Analog-to-Digital Converters (ADCs). Circuit techniques that exploit the benefits of the enhanced body-effect biasing tunnability are applied to the proposed VCO in order to improve its linearity, frequency range and robustness to technology-process variations with respect to conventional ring oscillators. The proposed circuit is applied to the design of a second-order ΣΔ ADC clocked at a configurable rate of 1-to-2 GHz. The ADC uses a multi-phase VCO-based front-end integrator as the only analog circuit, while the rest of its building blocks are digital circuits. Transistor-level simulations show that the presented techniques improve the linearity with respect to conventional VCO-based ΣΔMs, featuring 10-bit effective resolution within a 10-MHz signal bandwidth, with an estimated power consumption of 230μW.

This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.

This paper presents a state-of-the-art overview and recent advances on circuit and system level design methods and EDA tools for the automation and optimization of Delta-Sigma (ΔΣ) modulators. Main synthesis strategies and techniques are highlighted, putting emphasis on those aspects, which need to be taken into account in order to maximize the performance of ΔΣconverters, while keeping computational efficiency high. Based on the comparison of the approaches considered in this survey, the authors try to answer, where man or machine can come in1.

A 12-bit SAR ADC with an extended input range of 3.2 Vpp-d (±1.33 VREF) achieved through the use of an input sampling scaling technique, is presented. The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The ADC is implemented in a 0.13 μm CMOS process and achieves an SNDR of 69.3 dB and an SFDR of 79 dB without calibration, while consuming 0.9 mW, with a measured DNL of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.

A gated ring oscillator (GRO) based multi-stage noise-shaping ΔΣ modulator (ΔΣM) is presented in this paper. Loop-filter integrators followed by a digitally implemented GRO make the proposed architecture suitable for scaling-friendly implementations. Quantization noise of the first stage is represented in the time domain and it eases the quantization error extraction with a simple digital circuitry. The GRO offers inherent dynamic element matching, and hence no extra circuitry is needed to linearize the DACs in the feedback path. Time-domain behavioral simulations are shown to study of main GRO non-idealities considering a discrete-time MASH 3-1 topology, featuring a SNDR of 94 dB for an OSR of 16 over a 2-MHz signal bandwidth.

This paper presents a toolbox for the behavioral simulation of SAR ADCs in Simulink®. The models include the most limiting circuit effects such as sampled thermal noise, capacitor mismatch, finite settling, comparator noise and offset. A user friendly interface is also included to allow study and high-level design of SAR ADCs, which is illustrated by means of a design example. It is also shown that the proposed toolbox is several orders of magnitude faster than electrical simulators, while keeping a high accuracy.

This paper presents the design and implementation of a fourth-order band-pass continuous-time ΣΔ modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finite-impulse-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65-nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7-to-22.8 mW and a programmable 1.2/2GHz clock rate1.

This demo shows how to use multi-objective evolutionary algorithms for the optimum high-level design of ΣΔ analog-to-digital converters. The methodology illustrated in the demo is based on the combination of SIMSIDES, a SIMULINK-based time-domain behavioral simulator for ΣΔ modulators, with multi-objective optimization techniques. The proposed methodology allows designers to explore the design space in an efficient and intuitive way in order to fulfill a number of different design objectives simultaneously, by finding out the best sets of target specifications - defined as Pareto-optimal fronts. The presented approach can be extended to several kinds of optimizers implemented in MATLAB, and diverse examples are illustrated so that visitors will learn how to apply it to their own designs and projects. Although the demo is focused on ΣΔ ADCs, the tools shown in the demo can be used for the optimization of any other analog integrated circuits and systems1.

This paper presents a high-level synthesis methodology based on the use of multi-objective evolutionary algorithms for the optimization of ΣΔ modulators. Compared to conventional approaches, the proposed method allows to explore a number of different design objectives simultaneously in the design space in order to find out the best sets of target specifications - defined as Pareto-optimal fronts. This strategy leads to more efficient designs in terms of effective resolution, bandwidth and power consumption. As an application, the proposed method is applied to the high-level design of a 65-nm CMOS LC-based fourth-order band-pass continuous-time ΣΔ modulator, showing a number of experiments to validate the presented approach1.

This paper presents an overview of the state of the art on carbon-based circuits and systems made up of carbon nanotubes and graphene transistors. A tutorial description of the most important devices and their potential benefits and limitations is given, trying to identify their suitability to implement analog and digital circuits and systems. Main electrical models reported so far for the design of carbon-based field-effect devices are surveyed, and the main sizing parameters required to implement such devices in practical integrated circuits are analyzed. The solutions proposed by cutting-edge integrated circuits and devices are discussed, identifying current trends, challenges and opportunities for the circuits and systems community.

This paper presents a novel transconductor which is widely tunable and reconfigurable to a number of circuit specifications with an adaptive power consumption. Current-starving techniques are combined with programmable output stages so that the output current range and granularity can be arbitrarily set, while increasing energy efficiency with the number of active stages. These characteristics make the proposed circuit very suited to enlarge the autonomy and battery life in a number of portable multi-mode/multi-standard devices, spanning from biomedical applications and mobile phones to wireless sensor networks1.

This paper compares the performance achieved by carbon-based field-effect transistors made up of either carbon nanotubes or graphene, based on the SPICE models reported for the electrical simulation of these devices. The results achieved by these models are compared with silicon-based conventional CMOS devices, in terms of their main electrical (IDS-vs-VDSand IDS-vs-VGS) characteristics as well as their fundamental performance metrics, including the intrinsic voltage gain, Av, transconductance efficiency, gm/IDS, and transit frequency, fT. These figures of merit are obtained for diverse biasing and sizing conditions, and discussed from a circuit designer's perspective, in order to determine the benefits and drawbacks of the materials and devices under study. As an application, some carbon-based basic analog and digital circuits are designed and compared with their CMOS counterparts, in order to highlight their potential advantages in each case1.

This demo shows how to implement efficient behavioral modeling and simulation techniques for the systematic design of analog circuits and systems in MATLAB/SIMULINK. The methodology described in the demo is based on the use of C-coded SIMULINK S-functions to develop precise models of analog circuits, which allow designers to simulate complex systems with reduced simulation time, while keeping high accuracy. This simulation approach can be combined with an optimizer to automate the high-level synthesis and verification of many different analog integrated systems. As an application, two different toolboxes developed using the proposed techniques are illustrated in this demo: one is intended for the simulation of wireless receivers and the other one focuses on ΣΔ data converters. Through the multiple examples included in these toolboxes, visitors will experience the philosophy behind the presented approach and will learn how to apply it to their own designs and projects. ISCAS Track: Analog Signal Processing.

This paper discusses design considerations of LC-based bandpass continuous-time ΣΔ modulators intended for the analog-to-digital conversion of radio-frequency signals in software-defined-radio receivers. A top-down high-level synthesis methodology - based on the combination of undersampling techniques, programmable notch frequency and adequate selection of loop-filter coefficients - is presented to design efficient modulator architectures, which can be adapted to fulfill the requirements of diverse wireless communication standards, while keeping stability and robustness to circuit errors. Main architectureand circuit-level design issues are analyzed, considering diverse case studies based on Gm-LC resonators and different kinds of digital-to-analog converters. Time-domain simulations validate the presented approach1.

Classical decimation structures usually use comb filters at first stage due to the simplicity of comb filters. However, comb filters cannot satisfy high performance demands of state-of-the-art Sigma-Delta (ΣΔ) analog-digital converters (ADCs). Some possible solutions are comb based structures which are power and area efficient and posses an improved magnitude characteristic. The principal issues in the comb-based filter design are: power and area efficiency, high alias rejection and approximately flat passband characteristic, considering also high values of the decimation factors. In this paper we first review the new trends in ΣΔ ADCs and demands for the decimation block design. Next we review power and area efficient structures. The methods to improve the alias rejection of comb filters, as well as the methods for the compensation for the comb passband droop, and those strategies which simultaneously improve the alias rejection and the passband droop are reviewed in the following. Finally we review the multirate decimation structures.

This paper presents a continuous-time fourth-order band-pass ΣΔ Modulator for digitizing radio-frequency signals in software-defined-radio mobile systems. The modulator architecture is made up of two resonators and a 16-level quantizer in the feedforward path and a raised-cosine finite-impulsive-response feedback DAC. The latter is implemented with a reduced number of filter coefficients as compared to previous approaches, which allows to increase the notch frequency programmability from 0.0375/sto 0.25/s, while keeping stability and robustness to circuit-element tolerances. These features are combined with undersampling techniques to achieve an efficient and robust digitization of 0.455-to-5GHz signals with scalable 8-to-15bit effective resolution within 0.2-to-30MHz signal bandwidth, with a reconfigurable 1-to-4GHz sampling frequency1.

This paper examines and compares the state of the art in ΣΔ Modulators from an empirical but systematic perspective. Statistical data extracted from more than 300 cutting-edge integrated circuits have been exhaustively analyzed to identify trends, design challenges, as well as the most efficient solutions proposed for different application scenarios in the frontiers of the ΣΔ modulation technique. The results of this study are presented as design guidelines in order to help designers to select the optimum ΣΔ architecture and circuit implementation for a given set of specifications.

This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.

This paper analyzes the use of behavioral simulation techniques to enhance the teaching-learning process in electrical engineering courses, specifically those dealing with circuits for communication systems. The method - which can be applied to both undergraduate and master courses - allows students to better understand complex circuit- and device-level phenomena, by describing them at a higher abstraction level. As a demonstration vehicle of the presented methodology, two examples are considered in this work: an analog front-end of a direct-conversion digital radio receiver and a ΣΔ modulator. In both cases, behavioral models of the different subcircuits have been implemented in MATLAB/SIMULINK and used by the students enrolled in two different courses: an undergraduate course and a master course. The results presented in this paper reveal that students become highly motivated and satisfied with the course contents and the proposed simulation-based learning methodology.

This paper presents an educational methodology that uses the computational resources available in the nanoHUB.org online research and education platform. To this end, a number of software tools provided by nanoHUB.org have been incorporated as part of the practical lab exercises and linked to an e-learning virtual environment of a course on Electronic Materials, with emphasis on Nanoelectronic devices. The activities carried out during the course allowed students to enhance their understanding of those theoretical concepts dealing with Nanoelectronic materials and devices, thus becoming more motivated and satisfied. As an application and example, a set of experiences carried out by students is described. These experiences cover different Nanoelectronic materials and devices, going from physical and theoretical principles to device simulation. The proposed method has been applied to an undergraduate course, although it could be extended also to master students enrolled in courses dealing with materials science and engineering.

This paper describes the education activities carried out to motivate students enrolled in a laboratory course focused on the design of analog CMOS integrated circuits. Instead of using the traditional method based on doing practical exercises, a teamwork methodology was followed that consisted on a chip design project implemented by a group of students, each one playing a different role in the design team and being in charge of different tasks. A short training period at the beginning of the course was used for a preliminary assessment of students in order to assign their task and role in the design project. One of the students was selected as the project manager, while teachers acted as project reviewers. A set of control mechanisms, including internet-based video conferences and chats, was established. These tools allowed students to coordinate their activities and also were used by professors to check the work in progress during the course - apart from those review sessions taking place on-site in classroom. As a result of all these initiatives, students become more encouraged to do the practical exercises required to fulfill the course objectives and - at the same time - they developed and improved other complementary competencies, like the ability to work in a team and to defend their work by means of oral presentations.

This paper presents the design and characterization of a preamplifier used in the electronic front-end of low-pressure gaseous secondary electron detectors. The circuit - implemented in a printed circuit board as a proof of concept - has been designed to cope with the specifications of the readout electronics used in spatial resolution measurements. Experimental results show a transimpedance gain of 80dB, an overall voltage gain of 18 dB, a peak signal-to-noise ratio of 36.5 dB and a shaping time frame of 140-170ns. These features improve the performance of previous reported approaches to the problem, and allow us to minimize the overlapping probability in secondary electron detections for radioactive ion beams tracking, achieving a counting rate higher than 106 particles per second.

This paper presents a flexible 1.2-V 90-nm CMOS cascade three-stage SC ΣΔ modulator with local resonation in the last two stages, unity signal transfer function and programmable (either 3 or 5 level) quantization in all stages. The chip reconfigures its loop filter order (2nd, 4th, 6th order), the clock frequency (from 40 to 240MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental results demonstrate the flexibility of the proposed modulator, featuring a programmable noise shaping within a 100kHz-to-10MHz signal band, with adaptive power dissipation1.

This paper discusses the use of behavioral simulation techniques to improve the quality of teaching/learning circuits and systems for communications. The proposed pedagogical methodology has been applied in several electrical engineering courses, in both undergraduate and master degrees. The method allows students to better understand some complex circuit-and physical-level phenomena, by describing them at a higher abstraction level. In addition to enhance their understanding of design problems and skills, students become more motivated and satisfied. As an application, two case studies are considered in this work: a radio-frequency front-end system and an analog-to-digital converter. In both cases, behavioral models of the different building blocks have been implemented in MATLAB/SIMULINK and used by the students enrolled in two courses named: Electronic Circuits for Communications and Wireless Transceivers: Standards, Techniques and Architectures.

This paper describes the design of a switched-capacitor fourth-order single-loop Σ∆ modulator with a 5-level embedded quantizer.The loop filter consists of a cascade of resonators with distributed feedforward (CRFF) coefficients, which can be programmed to make the zeros of the noise transfer function variable.As a result, the modulator can be reconfigured either as a lowpass or as a bandpass analog-to-digital converter with a tunable notch frequency and an optimized loop-filter zero placement.The circuit -designed and implemented in a 1.2-V 90nm CMOS technology -incorporates diverse architecture-and circuit-level strategies to adapt its performance to different sets of specifications with a variable sampling frequency of 100 and 200MHz and scalable power consumption.Post-layout simulations (for frequency range of DC to 22MHz) and behavirol simulations (from 22 to 44MHz) show a correct operation of the circuit in steps of 1-to-2MHz, featuring an adaptive SNDR of 74to-86, 57-to-68 and 50-to-59dB within a signal bandwidth of 200kHz, 1MHz and 2MHz, respectively, while dissipating a scalable power consumption of 16-to-22mW 1 I.

This paper analyses the use of continuously-tuned Low Noise Amplifiers (LNAs) for the implementation of the next generation of software-defined radio receivers. Two LNA circuits are discussed. One is based on a folded cascode stage and the other one consists on a two-stage inductively degenerated common-source configuration. Both LNAs - designed and implemented in a 1-V 90-nm CMOS technology - employ MOS-varactor based tuning networks to make the operating frequency continuously programmable within the band of interest, targeting the requirements of GSM, UMTS, Bluetooth and WLAN standards, as well as any other operation mode in between. Practical design issues are presented, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. Experimental measurements demonstrate a correct operation of the circuits, showing a continuous tuning of Noise Figure (NF) and S-parameters within a 1.75-2.48 GHz band, featuring NF21>;19.6 dB and IIP3 >; -9.8 dBm in a frequency range of 1.75-2.23 GHz.

This paper presents the design of a hybrid continuous-time/discrete-time fourth-order cascade ΣΔ modulator intended for wideband low-power wireless applications. The circuit is based on a new concept of multirate operation, in which the front-end stage - implemented using continuous-time (Gm-C) integrators - operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. Simulation results show that the modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.1

This paper presents novel architectures of multirate hybrid cascade continuous-time/discrete-time ΣΔ modulators that take advantage of the potentially faster operation of the continuous-time part of the circuit, while keep a reduced sampling operation of the back-end discrete-time stages. Compared to conventional multirate ΣΔ modulators, the proposed architectures use a higher sampling rate in the front-end (continuous-time) stage of the modulator, whereas the back-end (discrete-time) stages operate at a lower rate. It is demonstrated that the intrinsic aliasing signal can be cancelled in the digital domain, with no additional analog hardware required. The resulting ΣΔ topologies are potentially faster than conventional multirate ΣΔ modulators, more power efficient than hybrid monorate architectures and more robust than cascade continuous-time implementations. The combination of these features results in a new class of ΣΔ modulators, very suited for the implementation of analog-to-digital converters in the next generation of broadband wireless telecom systems.

This paper reviews the main circuit strategies reported so far for the implementation of multi-standard low-noise amplifiers (LNAs) and presents a reconfigurable and adaptive LNA intended for beyond-3G RF hand-held devices. The circuit, designed and implemented in a 90-nm CMOS technology, combines a reduced number of inductors with PMOS-varactors and programmable load to adapt its performance to different standard specifications with optimized power consumption. As a case study, the LNA has been designed to cope with the requirements of four standards: GSM, WCDMA, Bluetooth (BT) and WLAN (IEEE 802.11b-g). Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF21>13.3 dB and IIP3>10.9 dBm over a 1.85-2.48 GHz band, with an adaptive power consumption between 17.4 mW and 21.7 mW from a 1-V supply voltage.

This paper presents novel architectures of hybrid continuous-time/discrete-time cascade SigmaDelta modulators that combine the benefits of both circuit techniques with programmable noise transfer function resonation and unity signal transfer function in all stages. Both local and inter-stage based resonation topologies are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit implementation. As an application, a multi-standard case study is presented, targeting 5-14 bit programmable effective resolution within a tunable 100 kHz-100 MHz signal bandwidth.

This paper presents the implementation and experimental characterization of a reconfigurable SigmaDelta modulator intended for multi-mode wireless receivers that is capable to perform the analog-to-digital conversion for GSM, Bluetooth, and UMTS standards. The SigmaDelta modulator reconfigures its cascade topology and building blocks in order to adapt the performance to the diverse standard specifications with optimized power consumption. The prototype has been implemented in a 130-nm CMOS technology and features dynamic ranges of 86.7/81.0/63.3dB and peak signal-to-(noise+distortion) ratios of 74.0/68.4/52.8dB at 400ksps/2Msps/8Msps, respectively. The modulator power consumption is 25.2/25.0/44.5mW, of which 11.0/10.5/ 24.8 m W are dissipated in the analog circuitry.

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit-level in order to adapt its performance to the different standard specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

This paper describes a SIMULINK block set for the behavioral simulation of RF receivers. Building blocks are modeled including their main circuit-level non idealities. These models are incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, what makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As a case study, a direct-conversion receiver intended for 4G telecom systems is modeled and simulated using the proposed toolbox.

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascadeΣΔmodulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.

This paper presents design considerations for cascade sigma-delta modulators (SAMs) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1L-2expandible SigmaDeltaM is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach

This paper presents the design of a continuous-time multibit cascade 2-2-1 DeltaSigma modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 0.13mum CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth

This paper presents the design of a continuous-time multibit cascade 2-2-1 ΣΔmodulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.