In this work, the relationship between Lyapunov exponents, used to estimate the effects of process variability, and the standard deviation obtained through the Monte Carlo method was established analytically, demonstrating that the Lyapunov exponents characterize a metric for estimating such effects. Based on this, a new metric for estimating the effects of process variability, based on Lyapunov exponents, was developed. The Sum-Power-Delay (SPD) was analytically defined, and its application was verified in the design of an inverter using 180nm technology. The SPD was applied to compare two sets of twenty cells designed in 180nm and 180nm-RH, a radiation-tolerant cell library developed at the Santa Maria Design House (SMDH), affiliated with the Federal University of Santa Maria (UFSM), demonstrating that circuits designed with Enclosed Layout-Transistor (ELT) are more robust against process variability. These results were obtained by analyzing circuits from the ISCAS85 benchmarks, as well as twenty circuits synthesized with our library. The same analysis was performed for matrix multiplication, aiming to evaluate the impact of process variability on this fundamental operation in space-grade digital systems. Finally, the 180nm-RH library was used to estimate the effects of process variability on circuits designed for space-oriented applications, including neural networks, filters, image compression, edge detection, and RISC-V microcontroller core modules. Key circuits for space applications, including image compressors, digital filters, and edge detection modules, were synthesized using a radiation-hardened standard cell library, enabling comparative evaluation of their robustness to process variability. The analysis provides valuable guidance for selecting circuits suitable for radiation-prone environments. Extension to RISC-V cores with 180 nm radiation-hardened transistors showed that Pico32 had the highest tolerance to process variability, confirming the practical effectiveness of the SPD metric in predicting and mitigating variability effects across designs.

As technology nodes advance, design rules restrictions are becoming increasingly complex due to physical limitations. This has made automatic cell layout generation a crucial and rapidly evolving area of study. A core stage of the layout design flow is the placement of transistors, which directly impacts the intracell routing and overall layout characteristics. This work presents a concise review of the different approaches that tackle the transistor placement problem to meet cell design goals.

The increasing deployment of artificial intelligence (AI) at the edge, particularly convolutional neural networks (CNNs) in resource-constrained devices, has created new challenges for ensuring system reliability and safety. Market analysts project a 21% annual growth rate in the edge AI market size over the next five years. These devices are being used in safety-critical applications such as autonomous vehicles, industrial control systems, and medical devices, where malfunctions due to radiationinduced soft errors can have severe consequences, ranging from degraded performance to life-threatening situations. Soft errors, caused by energetic particles, can corrupt data and instructions, resulting in unpredictable system behaviour. To meet safety standards in these domains, reliability engineers must proactively explore and implement efficient mitigation solutions during the initial design cycle.

The objective of this work is to unify, with mathematical rigor, the analyses to estimate the effects of process variability and the effects caused by radiation in digital circuits using a single analysis. First, we proved that to estimate the effects of process variability on delay and power, it is enough to estimate at least one of the two. Later, a relationship between the effects of radiation and the effects of variability was obtained through a common element between the two: the entropy of the circuit. We applied the presented methods to compare circuits with the operations: matrix multiplication, graph searches, encryption algorithms, and neural networks. All of the circuits are designed using a 180 nm technology. We were able to verify which circuits are more sensitive to the effects of variability and radiation simultaneously through the proposed method.

The fact that we can stream video on multiple devices in our homes, on the go using mobile devices, or even while video chatting across the globe, even with low bandwidth, is owed to video coding. Versatile Video Coding (VVC) is the latest video coding standard, which introduces a range of innovative tools. One example is adopting an alternative fractional motion estimation (FME) filter that is part of the Advanced Motion Vector Resolution (AMVR) extension. This work introduces a lowpower hardware architecture accelerator specifically designed for Fractional Motion Estimation (FME) with support for the AMVR extension of VVC.

The versatile video coding (VVC) standard introduces several innovative tools designed to enhance coding efficiency compared with its predecessors. One example is the adoption of an alternative filter for fractional motion estimation (FME) that is part of the adaptive motion vector resolution (AMVR) extension. While this allows a more precise motion representation, it also incurs more complexity for hardware implementations that aim at supporting most of VVC features. This work introduces a low-power hardware architecture accelerator specifically designed for FME with support for the AMVR extension of VVC. The proposed solution enables a systematic exploration of the design space of cross-layer approximate computing by combining approximations at both the operator and algorithm levels. This is achieved through the design of two novel architectures (2TAxA/4Tand2TAxA/2TAxA) alongside a newly proposed approximate filter applicable to both regular and alternative interpolation modes. Furthermore, we evaluate eight different approximate adder (AA) topologies to optimize power–quality tradeoffs. Experimental results demonstrate that for a complete FME multifilter interpolation unit (MIU) and maintaining an image quality threshold of$\text {SSIM} \geq 0.88$, our method achieves up to 72% power savings and 59.64% area savings.

Machine learning (ML) algorithms offer solutions across diverse domains, including resource-constrained devices. Despite advances in performance optimization and reduced-precision implementations, ML susceptibility to soft errors from radiation remains unclear. This work uses virtual platforms (VPs) to conduct a comprehensive soft error reliability assessment, at early design phases, of ML algorithms for Arm processors. The test strategy integrates confidence metrics, extensive fault injection (FI) campaigns, application profiling, and fault classifications. The main goals comprise (i) analyzing the consistency of SOFIA, a JIT-based framework, against event-driven simulators (mean mismatch ±4%, worst-case ±8%) and (ii) investigating correlations between FI results, NN-optimized kernels, and reduced-precision CNNs for IoT devices (up to 60% critical faults), aiming to promote software-based mitigation techniques (up to 98% critical faults mitigated). Results covering over 14.8 million FIs highlight SOFIA’s consistency, offering insights into balancing performance and reliability in multithreaded IoT edge platforms.

More and more components are integrated into a single chip. This advance makes difficult the task of placement and connecting these components, since more components means more connections to be performed. To address the place and route problem, there are automatic design techniques which allow to find near optimal solutions. In this work, we present NEATRouter as an alternative algorithm to optimize 2D routing of 2-pin nets. Our method focuses on complementing or replacing the MazeRouter algorithm, which is used in several state-of-the-art global routing algorithms. NEATRouter uses the Neuroevolution of Augmenting Topologies (NEAT) algorithm to generate neural networks capable of finding the shortest and most resource-efficient path for a 2-pin net. The results of our experiments suggest that this method can successfully compete with traditional approaches such as MazeRouter, generating quality routing in terms of wirelength and congestion management.

Single Event Transient (SET) faults are more notable every day at Earth applications. Even considering FinFET technology, the effects are not negligible. A circuit-level evaluation of radiation effects must consider each internal node of the cells, input vectors, particle type, and pulse width derived from the particle collision to determine the sensibility of the circuit under evaluation. Moreover, circuit characterization is time-consuming, involving many electrical simulations to reach an appropriate precision, mainly considering together with the process variability effects. This work evaluates how process variability and gate mapping impacts the radiation robustness on circuits composed by multigate devices in 7 nm FinFET technology. Firstly, the NAND2 and NOR2 gates are evaluated at nominal conditions and considering the process variability impact on the radiation sensitivity. After that, three different topologies of the same circuit are analyzed, showing that even when considering process variability, the circuit's robustness is highly dependent on its output gates and that the most sensitive part of a circuit may vary given process variability. Results also show that the$\mathbf{LET}_{th}$value may vary by order of magnitude due to the work-function fluctuation of NMOS and PMOS devices.

This work details a new way to deal with the Multiple-Cell Upsets (MCU) in SRAM memories for space applications. The method consists of spatially interleaving a memory plan with a network of memory radiation detectors. As a proof-of-concept, a prototype circuit composed of the radiation detectors was manufactured in the 350 nm CMOS Process Technology and tested considering two methodologies: electrically-induced SEU/MCU testing and SEE laser testing. Silicon measurement results confirm the correct operation of the circuit, detecting single and multiple events inserted in different positions of the evaluated detection plans. According to the ratio between the number of data and detection cells, the method proposed can provide a probability of detecting MCUs in a memory plan that can reach close to 100%.

The evolution of Science and Technology is decisive for many companies to obtain innovative products. A hypothesis is that students with research experience are more prepared to contribute in the search for innovation. The experience we have in Brazilian Universities shows that this hypothesis is true. Undergraduate students with experience in research projects, together with master and PhD students, finish the course with a bigger knowledge than the ones that don’t have the research experience. We observed that the research experience motivates students to proceed in their undergraduate courses, also increasing retention and success. A large number of these students are motivated to start a master or PhD. It will be shown how this procedure works, some experiences, and some examples of success.

Security and reliability problems in edge devices can become the Achilles’ heel for their massive use in Internet of Things (IoT) systems. While most works address security by implementing lightweight cryptographic algorithms, this paper is the first to assess the soft error reliability of lightweight cryptographic algorithms targeting IoT edge devices. This paper performs soft error analysis for ten lightweight cryptographic algorithms considering two compilers and running on top of an IoT-ready commercial processor model (i.e. Arm Cortex-M7). From the ten lightweight cryptographic algorithms, IDEA shows the best trade-off between reliability and number of instructions. Index Terms-Lightweight Cryptographic (LWC) Algorithms, Soft Error, Reliability, Internet of Things (IoT), Edge Devices.

The 2022 International Symposium on Physical Design lifetime achievement award goes to Prof. Ricardo Reis for his instrumental impact on EDA research in South America and contributions to the physical design community.

By the end of years 70s, microprocessors were designed by hand showing excellent layout compaction. It will be shown some highlights of the reverse engineering of the Z8000, which control part was designed by hand, showing several layout optimization strategies. The observation of the Z8000 layout inspired the research of methods to do the automatic generation of the layout of any transistor network, allowing to reduce the number of transistors to implement a circuit, and by consequence, the leakage power. Some of the layout automation tools developed by our group are briefly presented.

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety-critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors during the initial design cycle.

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety–critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors at the initial design cycle. This paper presents SOFIA, a framework that integrates: (i) a set of fault injection techniques that enable bespoke inspections, (ii) machine learning methods to correlate soft error results and system architecture parameters, and (iii) mitigation techniques, including: full and partial triple modular redundancy (TMR) as well as a register allocation technique (RAT), which allocates the critical code (e.g., application’s function, machine learning layer) to a pool of specific processor registers. The proposed framework and novel variations of the RAT are validated through more than 1739k fault injections considering a real Linux kernel, benchmarks from different domains and a multi-core Arm processor.

With the technology evolution, the decrease of transistors size and, thus, the increase of density of transistors per area, System-on-a-chip (SoC) development is becoming more and more complex. If design, verification, and test are considered, it is noticed how challenging it is getting for designers to plan and manage chips with dozens of billions of transistors, where optimization is a keyword to cope with the IoT world. This paper presents the use of a brand-new tool called ALTRAN to automatically generate the layout of chips using an FDSOI technology.

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

The OpenROAD project is an ambitious initiative seeking to develop an automated, open-source RTL-to-GDSII flow. To build its complex toolset, OpenROAD brings together a team of industry experts, veteran scholars, and enthusiastic students from different schools and different countries. This paper first presents our path to becoming OpenROAD contributors, highlighting the nature of the OpenROAD project, the recruitment process, and the necessary logistics. We then summarize the contributions of the Brazilian team to the OpenROAD project; these comprise the development of five tools and more than 10K lines of released code, along with authorship or co-authorship of two publications in the research literature. We also summarize our experiences from working in a large software project: (i) working environment and relationship with people from around the world; (ii) task management and short turnaround times; (iii) continuous integration and testing; etc. Finally, we highlight the challenges of "refurbishing" academic research codes for use in the design of production ICs.

Advanced technologies introduce new challenges as higher process variability impact and tight power constraints, mainly for IoT applications. Schmitt Trigger inverters are traditionally used for noise immunity enhancement due to their hysteresis characteristic, and have been recently applied to mitigate radiation effects and process variability impact. Alongside, Stacked-Inverter Gates are applied for gain increase, consequently, robustness enhancement as well. Thus, the main contribution of this paper is to investigate the relationship between transistor sizing, supply voltage, energy, and process variability robustness to get a minimal energy consumption circuit with FinFET technology, while keeping robustness and to identify the recommended circuit for different applications. Results show that adjusting the supply voltage and transistor sizing, at a high variability scenario, it is possible to decrease the energy consumption up to 32.19% while maintaining adequate robustness. It was possible to show a considerable difference concerning the Schmitt Trigger noise-immunity characteristics, in comparison to other designs, over supply voltage and variability scaling.

To achieve a substantial reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper proposes a low-cost system-level soft error mitigation technique, which allocates the critical application function to a pool of specific general-purpose processor registers. Both the critical function and the register pool are automatically selected by a developed profiling tool. The proposed technique was validated through more than 320K fault injections considering a Linux kernel, different benchmarks and two multicore ARM processors. Results show that our technique significantly reduces the code size and performance overheads while providing reliability improvement, w.r.t. the Triple Modular Redundancy (TMR) technique.

In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters "stay together" through final implementation. We propose use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 4X faster than use of hMetis for our largest testcases). Finally, we show a potential flow with fast "blob placement" of clusters to evaluate netlist and floorplan viability in early design stages; this flow can predict gate-level placement of 370K cells in 200 seconds on a single core.

The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5% and 4.2% on average, respectively.

Automotive systems are integrating artificial intelligence and complex software stacks aiming to investigate the real world, make decisions and perform actions without human input. The occurrence of soft errors in such systems can lead to wrong decisions, which might ultimately incur in life losses. This paper focuses on the assessment of the soft error susceptibility of a real automotive application (with up to 180 billion instructions) considering Linux kernel, multicore processor, and different cross-compilers. Results collected from extensive simulations show that the compiler can influence the reliability of the system.

Electronic computing systems are integrating modern multicore processors and GPUs aiming to perform complex software stacks in different life-critical systems, including health devices and emerging self-driving cars. Such systems are expected to experience at least one soft error per day in the near future [1], which may lead to life-threatening failures. This paper presents four novel non-intrusive fault injection techniques that enable full fault injection control and inspection of multicore systems behavior in the presence of faults. Proposed techniques were integrated into a fault injection framework and verified through a real automotive case study with up to 43 billions instructions. Results show that isolating critical application functions can lead to a more efficient soft error analysis with a reduction of masked faults in up to 28%.

Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability, which can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both nominal conditions and considering the impact of process variability. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.

The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. Traditionally, complex gates are adopted to reduce area, delay and power consumption. However, they can introduce challenges related to a robustness that might be avoided with more regular and basic cells. This extended abstract presents my current research works. Firstly, the different works performed in my research are described. Then, a short version methodology and the main results are presented.

The small number of logic functions in a traditional cell library limits the optimization of digital design regarding transistors, wires, and vias count. It affects traditional quality metrics, like area and total wire length. Our new library free approach enables such optimization by using tools for automatic layout synthesis of any transistor network. Using the traditional cell-based design flow to generate the initial netlist, we postprocess it considering to replace groups of cells by a single new cell of equivalent logic, which is not available in the cell library. Tests were performed over a standard benchmark, using a predictive 45nm cell library. Our approach reduces on average the number of transistors of a circuit by 21% when compared to a traditional solution. When to other logic minimization tools, it reduces transistor count by 2%, and by consequence, we obtain an average reduction of 9% on the number of wire segments, 5% in total wire length and 6% fewer pins. It also impacts the traditional performance metrics, demanding in 5% less area.

The emergence of IoT alongside with the increased process variability impact in modern technology nodes, is the main reason to control variability impact over metrics. Given the large set of IoT devices working in battery-oriented environments, energy consumption should be minimal and the operation regime reliable. Schmitt Trigger inverters are traditionally used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and process variability impact. However, Schmitt Trigger operation at the nominal voltage introduces high degradation on power consumption. Thus, the main contribution of this paper is to identify the relationship between transistor sizing, supply voltage, energy, and process variability robustness to get a minimal energy consumption circuit while keeping robustness. The results are extracted from 7-nm FinFET Schmitt Trigger layouts under different levels of process variability, supply voltages, and sizing. Also, a maximum frequency scaling under a failure threshold was performed. On average, the supply voltage decreases in layouts with a smaller number of fins, while maintaining acceptable robustness in high variability scenarios. Exploring voltage and transistor sizing made possible a reduction of about 24.84% of power consumption.

With battery-oriented applications rising in IoT, alongside the challenge of supplying electrical power, a reliable energy consumption metric must be satisfied. Although, variability has emerged as one of the critical threats to reliable metrics making the development of robustness techniques necessary. Schmitt Trigger Inverters haye been applied in designs due to its hysteresis characteristic, improving robustness. Still, Schmitt Triggers at nominal values of supply voltage may cause high degradation on power consumption. Thus, this work aims to indicate the appropriate dimensioning and supply voltage value for minimum energy consumption whOe preserving adequate robustness. It was found that the appropriate dimensioning and supply voltage can reduce up to 26.31% energy consumption.

Emerging electronic computing systems are becoming more vulnerable to the occurrence of soft errors in different system components (e.g., processors, memory, GPUs). To assess more useful information of the soft error reliability of multicore systems, this work proposes the extension of a fault injection framework, by including tools to trace and profile applications behavior under the presence of faults. Our approach is up to 10 times faster than simply parsing the application's disassembly, and it can show that, when affected by a fault, memory instructions are one of the safest in terms of crashing.

The yield optimization and radiation hardness are relevant reliability requirements as chip manufacturing advances more in-depth into the nanometer regime. One way to obtain improvements in these issues is by applying techniques to mitigate the effects of process variability and radiation-induced soft errors in the circuits. This work reports the use of three circuit-level approaches in FinFET designs as well as point out the pros and cons of adopting it.

To take advantage of the performance enhancements provided by multicore processors, new instruction set architectures (ISAs) and parallel programming libraries have been investigated across multiple industrial segments. This paper investigates the impact of parallelization libraries and distinct ISAs on the soft error reliability of two multicore ARM processor models (i.e., Cortex-A9 and Cortex-A72), running Linux Kernel and benchmarks with up to 87 billion instructions. An extensive soft error evaluation with more than 1.2 million simulation hours, considering ARMv7 and ARMv8 ISAs and the NAS Parallel Benchmark (NPB) suite is presented.

Software reliability is an essential design metric in emerging large-scale multiprocessor embedded systems. Designers should identify soft error susceptibility of multiple applications executing in parallel early in the design time to ensure reliable system operation. This work proposes a non-intrusive fault injection engine that enables to conduct bespoke soft error analysis, allowing to identify and understand the soft error propagation through the processing elements (PEs). The proposed fault injection campaign evaluates the impact of soft errors considering real benchmarks in an RTL model of a distributed-memory NoC-based multiprocessor. Experiments demonstrate that 19% of soft errors are propagated to other PEs, where 31.6% of them led to erroneous computation and 58.4% to a system crash. Thus, the fault analysis must consider not only its local effect on the processor and memory but also how the fault propagates to other system components.

This paper evaluates the benefits and drawbacks of using Schmitt Trigger (ST) inverters to minimize process, voltage and temperature variability effects on full adders. Variability mainly affects the energy outcomes on full adders, and the use of ST techniques can decrease up to 80% the energy deviation. However, it implies in a significant increase on the energy consumption. Considering the pros and cons, Mirror CMOS FA is the most beneficiated with the ST inverters, with a small impact on the average delay and a significant reduction in the energy and delay deviation.

The high integration capacity of digital circuits, which occurs due to technological scaling, presents new challenges for nanotechnology designs. The evolution of integrated circuits has made them more susceptible to faults, besides increasing the process variability, which can lead to circuits operating outside their specification ranges. This work evaluates the effects of process variability and radiation faults on complex gates. These effects are compared to alternative circuits that implement the same functions but exploring a multi-level of basic cells as NAND2, NOR2 and Inverters. The technology adopted is 7nm FinFET ASAP. Results show that although complex cells present better timing and power results, multi-level circuits are up to 28% less sensible to radiation faults and about 40% more stable under process variability.

Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2% to 30% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.

This work provides a detailed set of predictive data about FinFET and Trigate devices behavior considering process variability effects in ON and OFF currents. These evaluations help to understand the impact of variability sources identifying relevant behavior standards with respect to the use of FinFET and Trigate devices. The IOFFsuffers the higher impact of geometric variability, mainly on FinFET devices. PFET devices and the LSTP model are also more sensitive than NFET devices and high performance models. Results highlights that Trigate devices are up to 10% less sensitive to gate length variations.

Due to the advanced stage of development on EDA science, it has been increasingly difficult to implement realistic software infrastructures in academia so that new problems and solutions are tested in a meaningful and consistent way. In this paper we present Rsyn, a free and open-source C++ framework for physical synthesis research and development comprising an elegant netlist data model, analysis tools (e.g. timing analysis, congestion), optimization methods (e.g. placement, sizing, buffering) and a graphical user interface. It is designed to be very modular and incrementally extensible. New components can be easily integrated making Rsyn increasingly valuable as a framework to leverage research in physical design. Standard and third party components can be mixed together via code or script language to create a comprehensive design flow, which can be used to better assess the quality of results of the research being conducted. The netlist data model uses the new features of C++11 providing a simple but efficient way to traverse and modify the netlist. Attributes can be seamlessly added to objects and a notification system alerts components about changes in the netlist. The flexibility of the netlist inspired the name Rsyn, which comes from the word resynthesis. Rsyn is created to allow researchers to focus on what is really important to their research spending less time on the infrastructure development. Allowing the sharing and reusability of common components is also one of the main contributions of the Rsyn framework. In this paper, the key concepts of Rsyn are presented. Examples of use are drawn, the important standard components (e.g. physical layer, timing) are detailed and some case studies based on recent Electronic Design Automation (EDA) contests are analyzed. Rsyn is available at http://rsyn.design.

Electromigration (EM) effects are a high concern in power delivery networks where the current flow is unidirectional. As the integrated circuits (IC) technology nodes become smaller, the EM effects become a critical reliability failure mechanism also on signal nets. Such effect is also known as AC electromigration. This work presents a design strategy using special signal non-default routing rules (SSNDRs) to re-route the wire segments of critical nets that present a high current density and are EM-unsafe. Some EM-aware design steps are added in the traditional design flow to analyze, fix and improve the Mean Time to Failure (MTTF) of the designs.

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.

As the interconnections dominate the circuit delay in nanometer technologies, placement plays a major role to achieve timing closure since it is a main step that defines the interconnection lengths. In initial stages of the physical design flow, the placement goal is to reduce the total wirelength, however total wirelength minimization only roughly addresses timing. A timing-driven placement incorporates timing information to remove or alleviate timing violations. In this work, we present an incremental timing-driven placement flow to further optimize timing violations via single-cell movements.For late violations, we developed techniques to reduce the load capacitance on critical nets and to obtain load capacitance balancing using drive strength. For early violations, we present techniques that rely on clock skew optimization, register swap and interconnection increase. Our flow is experimentally evaluated using the ICCAD 2015 Incremental Timing-Driven Contest infrastructure. Experimental results show that our flow can significantly reduce timing violations. On average, for long maximum displacement, the quality of results is improved by 67.8% with late WNS and TNS being improved by 2.31% and 10.84%, respectively, early WNS and TNS improved by 68.92% and 76.42%, respectively and congestion metric ABU improved by 74.9% compared to the 1st place in the contest. The impact on Steiner tree wirelength is less than 2.5%.

In recent years, an increasing number of papers have focused on the cell selection problem. However, previous papers fail to consider the actual problems of performing cell selection in the after placement and CTS optimization stages of industrial designs. This paper discusses the obstacles found when applying state-of-the-art Lagrangian relaxation-based cell selection in a real industrial flow. Solutions to such obstacles are presented, filling the gap in previous literature.

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent two discrete gate sizing contests organized by International Symposium on Physical Design. Since then, there are plenty of research papers published and new algorithms are proposed based on the ISPD 2013 contest formulation. However, almost all (new and old) papers in the literature ignore the details of how power-driven gate sizing fits in industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based gate sizing into our actual physical synthesis framework, and explain the challenges and issues we observed from the point of view of VLSI design flows.

This work presents a design flow using a mixed cells design approach, mixing standard cells from a library with cells generated automatically with ASTRAN [1]. Moreover, a new technique using Artificial Neural Networks was developed to perform a comparison between two different cells, a standard cell one and ASTRAN's cell. Also, a new tool capable of performing cell replacements (between ASTRAN and standard cells) was developed willing to improve power consumption and area. So, there is a mixing of automatic cell synthesis tool and commercial synthesis tools dedicated to synthesize circuits using standard cells. Comparisons have shown that the presented approach was able to produce satisfactory results considering area and power consumption, with on average, 3.77% less power consumption and 1.25% less area.

In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuit's timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential cells are replaced, seeking to minimize clock skew. After that, a quadratic formulation is used to further reduce critical path delays. An incremental legalization tool is also presented, which supports the methods developed in this work. Our Incremental Timing-Driven Placement flow can achieve, on average, 0.3%, 26.2%, 8.7% and 23.7% of the normalized quality score improvement compared to state-of-the-art algorithms.

This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based FPGAs. Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical simulation for aging, soft error and different voltages was described to investigate the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.

As the foundries update their advanced processes with new complex design rules and cell libraries grow in size and complexity, the cost of library development become increasingly higher. In this work we present the methodology used in ASTRAN to allow automatic layout generation of cell libraries for technologies down to 45nm from its transistor level netlist description in SPICE format. It supports non-complementary logic cells, allowing generation of any kind of transistor networks, and continuous transistor sizing. We describe our new generation flow which is currently being used to generate a library with more than 500 asynchronous cells in a 65nm process.

Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects, and is used to analyze the lifetime of large benchmark circuits. Further, a method for optimizing the circuit lifetime using minor layout modifications is proposed.

Modern System on Chips (SoCs) and embedded electronic devices work at very high frequencies, which have the countermeasure of increasing the power dissipation and, consequently, the silicon die temperature. The presented radiation experiments on a 28nm FPGA-based SoC demonstrate that the temperature variation caused by a higher operating frequency affects the FPGA configuration memory cross section. An evaluation and discussion of the observed reliability dependence on power dissipation effects on practical application is also presented.

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

This paper presents a flow composed by a set of heuristic algorithms to address the discrete gate sizing and Vt assignment problem for leakage power minimization while satisfying delay, load and slew constraints. The proposed flow combines the Fanout-of-4 empirical rule, the Logical Effort concept, a Simulated Annealing (SA) as the main engine, as well as a new set of specific optimization strategies to solve this difficult problem as formulated in the 2012 ISPD Gate Sizing Contest. The main contribution of this work is to show how a sequence of Simulated Annealing runs, starting from a solution given by Logical Effort, Fanout of-4 rule, and employing a set of new techniques can be used together to solve gate sizing problems of up to a million gates. New methods are presented to solve violations during the Annealing and a dynamic cost function is presented that helps SA to achieve different conflicting tasks during the optimization. The entire flow was able to achieve the second and first ranks in the ISPD 2012 Contest. A set of different experiments is presented to support design decisions and highlight the quality of the achieved results.

This work presents methods to identify and treat circuit areas that have high overflow and interconnect demand, during global routing step. In that way, two cost pre-allocation techniques are presented: the first is applied during the pre-routing congestion estimation step of the global routing flow; the second technique will act during the iterative routing phase, where the the congestion is updated on each routing round and the congestion hot spots can be identified. Since the congestion hot spots are identified, a cost calibration step is executed using the proposed congestion look-ahead techniques. The focus of these algorithms is to speed up the convergence of the global routing solution while trying to reduce the side effects in wire length. Our experiments shows a speed up of up to 1.357x with 1.39% of maximum increase in wirelength when compared to the reference implementation for the ISPD 2008 benchmarks.

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

The power optimization of integrated circuits must be observed in all levels of abstraction of the design flow. The traditional standard cell flow don't really takes care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain an optimization at physical level, it is needed to allow the use of any possible logical function, by also using complex cells (Static CMOS complex gates SCCG) that are not available in a cell library. To have a "freedom" in the logic design step, it is needed the use of an EDA set of tools to let the automatic design of any transistor network (even with a different number of P and N transistors). This approach can reduce the amount of transistors needed to implement a circuit, reducing the power consumption, mainly the leakage power that is proportional to the number of components (transistors). This paper presents some examples and comparisons between the standard cell approach and the network of transistors approach. The flexibility of the approach can also let the designers to define layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability and DFM. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency.

Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. However, this robustness costs power. In this work, we present a mesh edge displacement algorithm that is able to reduce mesh wire length by 7.6% and overall power by 10.5% with a small mean skew improvement. We also present the first non-greedy buffer placement and sizing technique using linear programming (LP) and iterative buffer removal. We show that compared to prior methods, we can obtain 41% power reduction and an 27ps mean skew reduction on average when variation is considered compared to prior algorithms.

Despite the existence of several other alternatives for estimating delay of interconnects, the Elmore Delay Model still has been used for comparison of routing algorithms. The criterion used to establish Elmore's model as a confident metric for this purpose is the so-called Fidelity Property. In this work we investigate the Fidelity Property using nowadays interconnect parameters, in four routing scopes. For the first time the Fidelity is evaluated in actual algorithms comparison, one of the main utilities it was established for. What is found is that the original methodology used to evaluate this property hides a significant standard deviation. This standard deviation strongly impacts the capacity of Elmore's model to provide good certainty of choosing the best routing solutions among several ones. Additionally, the experiments of algorithms comparison show that different routing alternatives are appropriated for different routing scopes, with respect to metal layers, driver strengths and routing areas.

The C-element is a fundamental component in asynchronous circuits and quite used in synchronous circuits to mitigate transient faults. This work evaluates the transient-fault effects on the traditional dynamic, conventional, weak feedback, and symmetric C-element's implementations. An evaluation methodology is developed by means of fault-injection simulations at transistor level. Unlike existing methods, the methodology in this work is able to deal with the C-element function's particularities. In addition, C-element cells in different transient-fault robust versions are designed by using techniques based on sizing and transistor insertion. Results in terms of delay, power consumption, area, and fault-transient robustness show the best C-element options for the design of more robust systems.

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on user's requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated from time to time) is proposed. The aging sensor is a programmable delay sensor, allowing decision-making for several degrees of severity in the aging process. It detects abnormal delays, regardless of their origin. Hence, it can uncover ¿normal¿ aging (namely, due to NBTI) and delay faults due to physical defects activated by long circuit operation. The proposed aging sensor has been optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Moreover, the area overhead of the new architecture is significantly less than the one of other aging sensors presented in the literature. Simulation results with a 65 nm sensor design are presented, ascertaining its usefulness and its low sensitivity, in particular to process variations.

The availability of multimillion Commercial-Off-The-Shelf (COTS) Field Programmable Gate Arrays (FPGAs) is making now possible the implementation on a single device of complex systems embedding processor cores as well as huge memories and ad-hoc hardware accelerators exploiting the programmable logic (Systems on Programmable Chip, or SoPCs). When deployed in safety- or mission-critical applications, as avionic- and space-oriented ones, Singe Event Effects (SEEs) affecting COTS FPGA, which may have catastrophic effects if neglected, have to be considered and SEE mitigation techniques have to be employed. In this paper we explore the adoption of known techniques (such as lockstep, checkpointing and rollback recovery) for SEE mitigation to processors cores embedded in SoPCs, and propose their customization, specifically addressing the characteristics of programmable devices. Since the resulting design flow can easily be supported by automation tools, its adoption is particularly suitable to reduce the design and validation costs. Experimental results show the effectiveness of the proposed approach when compared to conventional TMR-based solutions.

A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.

Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to aging in such harsh environments. For safe operation, or for preventive maintenance, it is desirable that such monitoring may be performed on chip. On-line built-in aging sensors (activated from time to time) can be an adequate solution for this problem. The purpose of this paper is to present a novel methodology for electronic systems aging monitoring, and to introduce a new architecture for an aging sensor. Aging monitoring is carried out by observing the degrading timing response of the digital system. The proposed solution takes into account power supply voltage and temperature variations and allows several levels of failure prediction. Simulation results are presented, that ascertain the usefulness of the proposed methodology.

In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a maze router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.

In this paper two different design approaches for a large tuning range LP filter for DVB-T receivers are presented. The LP filter is placed at the beginning of the receiver chain, before to the RF and base band blocks, so that the design is challenging because high out-band frequencies rejection is required while maintaining low input referred noise. Closed-loop topologies have been investigated to comply with the in-band linearity requirements. A system level analysis has been developed using a proper Matlab procedure. This procedure allows optimizing the basic filter parameters - opamp bandwidth, R and C values - in order to satisfy the filter transfer function requirements. Two different design approaches will be considered. The first proposal is based on a 2nd order biquadratic cell. High quality factor is synthesized while guaranteeing the out-of-band frequencies rejection. The second implementation is based on the cascade of two biquadratic cells with more relaxed quality factor requirement. The design is realized using the 90nm CMOS technology. The simulation results for both implementations are presented. The minimum out-of-band rejection is maintained lower than -30dB, the maximum IRN in both cases is 4nV/radicHz and the IM3 is lower than -30dB for two in-band input tones.

This paper studies the 3D-via placement problem for 3D circuits. We model the problem in such a way that 3D-vias are assigned to layers between the circuit tiers. The placement problem consists of placing the 3D-vias with no overlap with other 3D-vias in the same layer. Positions inside the net bounding box are preferred and wire length minimization is used as target function. We present a heuristic based on the Tetris legalization approach for the 3D-via legalization. Our experimental results show that the algorithm could accommodate the 3D-vias in such a way that wire length overhead is close to zero in easy instances and still very low for harder instances (in most of the cases it is less than 0.1% and it is less than 5% in all cases). Compared to an existing approach, it obtains similar results with orders of magnitude advantage on run time.

This paper addresses the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. We present AMAZE, a fast maze router based algorithm that employs selected techniques to build optimized steiner trees. A biasing technique proposed for wire length improvement produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Our experimental results show that AMAZE is more effective to optimize delay to critical sinks than state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30%) while keeping the properties of a routing algorithm. We also analyzed the ability of AMAZE to handle blockages and verified experimentally that AMAZE produces tree with better delay to the critical sinks than P-Trees from 6% (5 pin nets) to 21% (9 pin nets). An important motivation for this work lies in the fact that, due to its acceptable run time and quality of results, AMAZE can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.

Heterogeneous MPSoCs present unique opportunities for emerging embedded applications, which require both high-performance and programmability. Although, software programming for these MPSoC architectures requires tedious and error-prone tasks, thereby automatic code generation tools are required. A code generation method based on fine-grain specification can provide more design space and optimization opportunities, such as exploiting fine-level parallelism and more efficient partitions. However, when partitioned, fine-grain models may require a large number of inter-processor communications, decreasing the overall system performance. This paper presents a Simulink-based multithread code generation method, which applies Message Aggregation optimization technique to reduce the number of inter-processor communications. This technique reduces the communication overheads in terms of execution time by reduction on the number of messages exchanged and in terms of memory size by the reduction on the number of channels. The paper also presents experiment results for one multimedia application, showing performance improvements and memory reduction obtained with Message Aggregation technique.

In deep-sub-micron technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis. This paper proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study yield of a dynamic-NOR using static keeper. The analytical formulations can be extended to a wide range of dynamic gates (for example pre-charge dynamic gates using dynamic keeper) because we use numerical approach for the calculation of derivatives required by error propagation. The proposed methodology presents errors less than 2% as compared to Monte Carlo simulation, while increasing computational efficiency up to 50×.

This paper presents a new transistor level design flow where it is possible to optimize the circuit with a wide number of logic functions and drive strengths. Different from the standard cell approach, our methodology is not limited to a previously characterized library of cells. The proposed design flow provides a virtual library with around 15,000 cells for logic synthesis and performs a transistor sizing optimization step to improve the timing of the circuit during layout generation. A transistor-level layout generator allows to explore these wide number of cells and drive strengths while optimizing the layout concerning connections and transistors. Circuits generated by our methodology were compared to the standard cell approach in which presented around 11 % of delay improvement and more than 30% of power savings.

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub- 100nm technologies. In this work we investigate the variability of flip flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ˜1ps is used to characterize hold time violations of flip flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to die variations of hold time violations are measured various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12–16% Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm.

This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in order to save design time. Furthermore, fault-tolerant IC design issues and results in area and performance were compared with a non-protected microprocessor version

This paper reports a case study about the automatic layout generation and transient fault injection analysis of a phase-locked loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. After layout validation, experiences were performed in the PLL in order to evaluate the sensibility against transient fault. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18/spl mu/m). Results report the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults.

This work explores an alternative model for area routing, which employs horizontally aligned terminals in each row of cells, providing channel-like routing areas. We have developed a two-layer router that decomposes the routing problem into smaller pieces and takes advantage of the low time complexity that channel routing has in order to provide fast and convergent area routing for channel-less cell-based circuits. Comparing to maze routing, our toll shows an average increase in wire-length of only 0.6%, and area increase of 7.2%, due to the insertion of spaces. But results show that it achieves 100% routing in almost linear time for our test circuits. This is the main contribution of this kind of simultaneous, variable-die approach when compared to traditional fixed-die methodologies. Convergence and short CPU times are crucial in many IC designs, mainly when time-to-market is a tighter constraint. But they can contribute also in any methodology helping to meet other design constraints by not getting stuck in non-convergent loops.

In this paper we discuss the migration of a 2D netlist with pre-placed I/Os to 3D circuits. For that, we present an algorithm to perform the partitioning of the I/O pins into various tiers targeting at I/O balancing and 3D-vias minimization. We formulate the netlist migration constrained with respect to the preservation of some original netlist properties. The I/O partitioning algorithm is based on the logic distance between I/Os. Since there is no literature on I/O partitioning for 3D circuits we compared our algorithm with two simplistic approaches that targeted balance and min-cut respectively. Experimental results show that our algorithm can reduce the number of 3D-vias compared to both algorithms, while balance is kept close to optimal. Most importantly, we showed that performing I/O partitioning separately we can reduce the number of 3D-vias even more than existing solutions in the literature for the netlist partitioning. Additionally, we studied the area impact of the 3D-vias resulted from the three algorithms targeting two different technologies for 3D circuits. We observed that especially in the bulk based technologies the 3D-via penalty is huge, favoring our algorithm

This paper present a comparison between three different high-level modeling approaches for embedded systems design, focusing on systems that require dataflow models. The proposed evaluation investigates the facilities provided by these approaches for expressing systems requirements, functional specification, and timing constraints. Properties like model readability, testability, and implementability are also considered. Moreover, the support to different Models of Computation is also evaluated. A Crane Control System is used as case study to apply the proposed comparison criteria.

Soft error rates induced by cosmic radiation become unacceptable in future very deep sub-micron technologies. Many hardening techniques at different abstraction levels have been proposed to cope with increased soft error rates. Depending on the abstraction level some techniques need to modify the design at architecture, circuit and transistor level, others required the modification of the circuit layout or to use new defined cells within the circuit. In this paper an automatic layout generator is presented to complete the system design process being able to easily generate the hardened design layout, thus reducing the system design time. This work aims at presenting a case study of a complete soft error tolerant integrated circuit by using an automatic layout generator called Parrot Punch.

This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266 MHz, while the floating point unit reaches 235 MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy (TMR) has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

This work presents a soft IP description of Rijndael, the advanced encryption standard (AES) of the National Institute of Standards and Technology (NIST). This Rijndael implementation runs its symmetric cipher algorithm using a key size of 128 bits, called the AES128 mode. The focus here is to produce a low area IP achieving good performance. To do that, we propose an architecture using mixed bit size processing, leading to a significant decrease in memory usage. The same methodology is used to implement three versions: the first one only encrypts the data, the second one decrypts and the third one performs both operation on the same device. The implementation choice was the AcexlK and Cyclone devices of Altera. The paper presents an introduction to cryptography, the AES contest that defined Rijndael as the new standard, the AES128 structure and some results, such as device occupation, clock frequency, throughput and latency.

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a high level technique to protect SRAM memories against multiple upsets based on correcting codes. The proposed technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple bit flips with reduced area and performance penalties. Multiple upsets were randomly injected in various combinations of memory cells to evaluate the robustness of the method. The experiment was emulated in a Virtex FPGA platform. Results show that 100% of the injected double faults and a large amount of multiple faults were corrected by the method.

A collaborative design system depends heavily on the chosen collaboration methodology, as well as on its technological infrastructure. This paper presents three data repository technologies and discusses their pros and cons on the role of supporting a collaborative design system.

The IP (Intellectual Property) for frame stream control is a soft IP module designed to handle data frames of variable lengths, with different transmission rates. It works in a store and forward way, using an external SDRAM memory of arbitrary capacity. There is a receiver and a transmitter interface where frames are respectively stored and forwarded. The goal of this IP module is to handle the different kinds of protocols used in modern networks. Through the standard interface a bridge can be built between a synchronous and an asynchronous channel, or a faster and a slower rate port. A simple protocol is implemented on both reception and transmission interface, making the IP reusable for different designs. It can be used, for instance, to build an IP (Internet Protocol) LAN bridge. A protocol-specific function (Ethernet, Token Ring, etc.) has to be implemented in order to deliver the IP frame to the frame stream controller IP, and another specific protocol function to receive the IP frames from the frame controller and to transmit them through the physical media.