Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.

Over the past two decades, test data compression has become a de facto technology used in large industrial designs to reduce the overall test cost. During DFT planning, it is very important to understand the impact of using different numbers of input/output channels on test coverage, test cycles, and test data volume. In this paper, an efficient method to estimate the test data volume with different input channel counts using the Embedded Deterministic Test (EDT) compression technology is proposed. The results can then be used to quickly determine the scan configuration that results in the least or near least test data volume. With this method, the total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error method.

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.

A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.

As the automotive industry enters a period of rapid evolution changing the way cars are designed and produced, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing around 120 MCUs. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. This paper presents Stellar BIST-a next generation compression scheme for in-system automotive test. The proposed solution can work with any sequential test compression. It builds on a finding that certain clusters of test vectors are capable of detecting many random-resistant faults, where a cluster consists of a parent (base) pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant tradeoffs between storage requirements and test application time, critical for in-system automotive applications. The experimental results obtained for industrial designs and different fault models illustrate feasibility of the proposed test scheme and are reported herein.

With the increase in design complexity and test data volume, compressed tests together with on-chip test decompression hardware such as Embedded Deterministic Test (EDTTM) are widely used in industry in order to reduce test cost. One of the challenges of such Design-for-Test (DFT) technology is to determine a set of optimal parameters such as the number of scan chains, scan channels, power budget, etc. such that it can reach the highest test coverage with a minimum amount of test data volume whilst satisfying various other constraints. To achieve the optimal compression configuration quickly, in this work deep learning technology based on Tensorflow is explored to estimate the test coverage and the data volume for a design when employing EDT under a given set of circuit parameters. Based on the estimated data, the optimal test architecture is also predicted, yielding a more efficient approach compared to the currently used trial-and-error methods. To demonstrate the advantages of our deep learning approach over the currently used utility, we present experimental data for eight industrial designs.

As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant.

Fault diagnosis patterns distinguish pairs of faults and are used to improve fault diagnosis resolution. Earlier, several methods to generate fault diagnosis patterns have been proposed. We demonstrate that all but one earlier proposed methods may generate invalid patterns when the circuit under test (CUT) has X sources, which is typically true for industrial designs. The earlier proposed method that can generate valid diagnosis patterns in the presence of X sources uses two copies of the CUT to generate diagnosis tests, thus requiring larger memory and run time. In addition, to use ATPGs that generate test to detect single fault, earlier methods require circuit modification for each pair of faults to be distinguished, requiring multiple loadings of the CUT, thus increasing run times. We propose a method to generate valid diagnosis patterns using a single copy of the CUT and using a standard single fault detection ATPG with minor modification. The proposed method does not require modifying the circuit to generate diagnosis patterns. Experimental results are presented to demonstrate the effectiveness of the proposed method.

Volume diagnosis has been used effectively to identify systematic defects for yield learning. Root cause deconvolution (RCD), an unsupervised machine learning technique which uses volume diagnosis data, has proven very effective for identifying root causes. As we march towards more advanced technology nodes, defects have more complicated behaviors rendering some model parameters used in RCD are not precise enough to be effective. In this paper we use a supervised machine learning technique to accurately learn these model parameters from training data. Controlled experiments using simulation data on several industrial designs show that our approach improves RCD accuracy. We also demonstrate that the approach correctly predicts 71% of the systematic defects in 21 cases validated by physical failure analysis of real silicon, which is a significantly better result compared to using the original parameters.

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

This paper proposes an efficient diagnosis-aware automatic test pattern generation (ATPG) procedure that can quickly identify equivalent-fault pairs and generate diagnosis patterns (DPs) for nonequivalent-fault pairs, where a (non)equivalent fault pair contains two stuck-at faults that are (non)equivalent. The proposed procedure contains three main methods, which together can efficiently generate highly compacted DPs by using a conventional ATPG tool. First, an all-pairs at-a-time diagnosis pattern generation (AFPAT-DPG) method, which adopts user-defined fault models (UDFMs), is employed to quickly generate DPs for most fault pairs that cannot be distinguished by a given set of, typically fault detection, test patterns (TP). For those fault pairs that cannot be distinguished by AFPAT-DPG, a multipair diagnostic ATPG method (MP-DATPG) is used. MP-DATPG is a complete method in the sense that it can generate diagnosis tests for every distinguishable pair of faults or prove that the pair of faults is indistinguishable. However, due to back-track limits in test generation procedures, diagnosis test generation for some fault pairs may be aborted after the application of the two methods. For such fault pairs, a subcircuit analysis (SCA) method is applied to identify equivalent fault pairs among the aborted fault pairs by trimming the circuit under consideration into one that is much easier to process within the back-track limits of the test generation procedures. Experimental results show that the proposed procedure is the first work that distinguishes 100% of all fault pairs in all ISCAS'89 and IWLS'05 benchmark circuits and over 99.99% for all ITC'99 benchmark circuits using a conventional ATPG tool that generates tests to detect faults.

In this paper, we propose a novel technique to detect recycled ICs via an on-chip, coarse-grained aging sensor, which can be applied to low-power circuits featuring power gating. The sensor detects the increase in the power-rail discharge time of power-gated circuits, when the circuit enters the sleep condition. Through HSPICE simulations, we prove that power network discharge time (τdV) is extremely sensitive to the age of the circuit. Indeed, after only 1 month of operation, τdVincreases by more than 3X and, after 1 year, its increase exceeds 7X. Our technique enables the detection of recycled ICs with a very high confidence and is a considerably more sensitive indicator of an aged device that alternative solutions relying on fine-grained performance degradation sensors.

This paper presents a novel test pattern generation flow to detect stuck-at and transition faults simultaneously. Both fault models are transformed into a unified fault model for a proposed 2-time-frame circuit model. This makes it possible to generate patterns for both types of faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires less test data volume and shorter test application time without degrading the fault coverage for either type of faults. Experimental results show that, compared to the conventional methods, the proposed method can reduce the total test pattern counts by up to 12.27% and 15.54% and test application times up to 12.06% and 15.58% for ISCAS'89 and ITC'99 circuits, respectively.

A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS`89, IWLS`05 and ITC`99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.

With the growing number of very complex safety-critical components used in advanced driver assistance systems and autonomous vehicles, integrated circuits in this area must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This, in turn, requires advanced test solutions that have to respond to challenges posed by automotive parts. This paper presents Stellar BIST - a deterministic two-level compression scheme for in-system automotive test. The proposed solution seamlessly integrates with any sequential test compression scheme and takes advantage of the fact that certain clusters of test vectors detect many random-resistant faults where a cluster consists of a parent pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant trade-offs between area and time, critical for in-system automotive applications. Experimental results obtained for large industrial designs with stuck-at and transition faults illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents a new staggered test pattern generation scheme. It produces deterministic stimuli in the course of a test-per-clock-based process by using dedicated capture-per-cycle observation test points. These observation points, once inserted into a design, form dedicated scan chains with the capability of capturing test responses during shift cycles when other regular scan cells are loading test patterns. This new scan infrastructure enables one to generate more compact test patterns, reduce test pattern counts, systematically detect many additional faults, and keep the resultant silicon real-estate at the acceptable level. It appears that original scan cells of a design can provide good observability for staggered test patterns. Thus, capture-per-cycle observation test points are directly inserted at selected scan cells' inputs with a minimal impact on the design. Experimental results obtained for large industrial designs illustrate feasibility of the proposed ATPG and are reported herein.

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today's very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation-and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC'99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in subthreshold current due to BTI aging. We develop a simulation framework to evaluate tradeoffs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.

in many cases, the main cause of yield loss is a specific layout pattern that is difficult to manufacture and is prone to causing an open or short defect. This situation is getting worse with advanced technology nodes due to small feature sizes and complex manufacturing processes. Volume scan diagnosis results are a rich data source for identifying such yield limiting layout patterns, but a big challenge is how to deal with an enormously large number of potential layout patterns to be considered for analysis and how to avoid over fitting. In this paper we present enhancements to the previously published root cause deconvolution technique for analyzing volume scan diagnosis data that enables it to overcome this and correctly, and automatically, determine the right layout patterns causing systematic yield loss. Also presented is an application to industrial data where a layout pattern identified by the new technique was validated by physical root cause analysis to be the dominant yield loss mechanism.

Opens are known to be one of the predominant defects in nanoscale technologies. Especially with an increasing number of complex cells in today's VLSI designs intra-gate opens are becoming a major problem. The generation of tests for these faults is hard, as the timing of the circuit needs to be considered accurately to prevent the invalidation of the generated tests through hazards. Current test generation methods, including new cell aware tests that explicitly target open defects, ignore the possibility of hazard caused test invalidation. Such tests can fail to detect a significant fraction of the targeted opens. In this work we present a waveform-accurate hazard-aware test generation approach to target intra-gate opens. Our methodology is based on a SAT-based encoding and allows the generation of tests guaranteed to be robust against hazards. Experimental results for large benchmarks mapped to the state-of-the-art NanGate 45nm cell library including complex cells show the test generation efficiency of the proposed method. Large circuits were efficiently handled - even without the use of fault simulation. Our experiments show that on average, about 10.92 % of conventional hazard-unaware tests will fail to detect the targeted opens because of test invalidation - these are reliably detected by our new test generation methodology. Importantly, our approach can also be applied to improve the effectiveness of commercial cell aware tests.

With decreasing feature sizes and increasing complexity of fabrication processes for manufacturing VLSI semiconductor devices, more systematic defects occur at the advanced technology nodes. Product yield ramp up is mostly determined by how fast systematic defects are identified and fixed. Given the long times and expense of physical failure analysis (PFA), use PFA on a large number of failing devices to find systematic defects is becoming infeasible. For this reason, volume diagnosis data mining for root cause identification based on statistical methods is used to reduce turnaround time and cost to speed up the process of systematic defect identification. The identified root cause information not only can be used to improve yield analysis but also can reduce PFA cost by focusing on failing devices with systematic defects.

This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.

With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. This is because CMOS circuits experience a large number of hazards during circuit inputs switching which are not modeled by classical tools. Hazards may activate some TSO faults considered untestable by classical ATPGs. The generation of tests that target such hazard activated opens can result in a very significant DPPM improvement - if used. In this paper, we present the first deterministic methodology for targeting hazard activated opens. It is based on a waveform-accurate SAT-based modeling and allows to accurately determine if a TSOF is detectable by hazard activation - or not. In addition, we provide a thorough investigation of the additionally achievable fault coverage using the state-of-the-art NanGate 45nm as well as NanGate 15nm cell libraries.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2×-4× compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

Scan chain diagnosis plays an important role in silicon debug and yield ramp-up since 10% to 30% of chip failures are caused by scan chain failures. Failure data collected on testers is limited by buffer sizes to capture the failing responses from scan chains, especially since scan chain failures produce a large amount of failing responses. In this paper, we propose a new pattern selection method to maximize the chain diagnosis resolution when limited failure information is collected from the tester. Experimental results on industrial designs show our method achieves higher diagnosis resolution than previous method.

An excessive switching activity during the functional capture cycles of scan-based tests can lead to overtesting of delay faults. Low-power test generation procedures that address this issue consider the switching activity of the fault-free circuit. This paper observes that an excessive switching activity in a faulty circuit can also affect the test application process. In particular, we show that a fault effect may disappear if a signal-transition is delayed because of an excessive switching activity in the faulty circuit. Thus, excessive switching activity in the faulty circuit can result in test escapes. Using functional broadside tests for benchmark circuits, we study the extent to which the switching activity of a faulty circuit may exceed the switching activity that is possible during functional operation. We also consider the effects of eliminating tests with excessive switching activity in faulty circuits.

Typically IDDQ measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using IDDQ measurements is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed IDDQ based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.

Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.

In this paper we consider detection of faults in CMOS cells that are more complex than primitive gates. We derive a single set of tests based on functional description of the cells. The tests derived, if applied, detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell, in any implementation of the cell functions. We give results on an industrial design to demonstrate the benefits of the proposed tests relative to standard stuck-at, cell exhaustive and transition fault tests in covering faults in such cells.

Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially invalidating tests generated with assumed circuit parameters. Additionally, recent investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.

Manufactured VLSI circuits using a new technology typically suffer from systematic defects that are process-dependent and at sub-nanometer feature sizes such defects may be even design-dependent. The root causes for systematic defects must be determined to ramp up yields. Volume diagnosis is becoming popular to identify root causes for systematic defects. Volume diagnosis uses logic diagnosis based on failing circuit responses to production tests of a large number of failing devices, followed by statistical analysis methods to determine the root cause(s) for yield limiters. Typically production tests use fault detection tests and hence may have limited diagnosis resolution. To improve diagnosis resolution diagnostic ATPGs can be used to generate test sets to distinguish all pairs of distinguishable faults in one or more fault models. The sizes of such tests tend to be considerably higher than fault detection test sets used as production tests. For this reason, generation of test sets that detect faults and also possess a high diagnosis resolution is important. In this work we present a method to improve the diagnosis resolution of a compact fault detection test set without increasing pattern count or decreasing fault coverage. The basic idea of the approach is to generate a SAT formula which enforces diagnosis and is solved by a MAX-SAT solver which is a SAT-based maximization tool. We believe this is the first time a method to improve diagnosis resolution of a test set of given size has been reported. Experimental results on ISCAS 89 circuits demonstrate the effectiveness of the proposed method.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Open defects such as interconnect opens are known to be one of the predominant defects in nanoscale technologies. Yet, test pattern generation for open defects is challenging because of the high number of parameters which need to be considered. Additionally, the assumed values of these parameters may vary due to process variations reducing fault coverage of a test set generated under this assumption. This paper presents a new ATPG approach for circuit Parameter independent (CPI) tests. In addition a definition of oscillation free CPI tests is given. The generated tests are robust against process variations affecting the influence of neighboring interconnects as well as trapped charge and prohibit oscillating behavior. Experimental results show the high efficiency of the new approach, generating CPI tests for circuits with over 500k nonequivalent faults and several thousand aggressors.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of the art commercial ATPG for BIST ready designs.

New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.

Diagnosis memory footprint for large designs is growing as design sizes grow such that the diagnosis throughput for given computational resources becomes a bottleneck in volume diagnosis. In this paper, we propose a scan chain diagnosis flow based on dynamic design partitioning and distributed diagnosis architecture that can improve the diagnosis throughput over one order of magnitude.

In this paper we present a methodology to accurately diagnose cell internal defects when test patterns with multiple capture cycles are used. The multi-cycle test patterns can lead to more possible excitation conditions such that the existing extraction methods become less accurate. In addition, the realistic cell internal defects may produce different faulty values at different capture cycles, or only produce faulty values on some particular capture cycles. Thus the traditional logic diagnosis techniques may not accurately find the defective cells since most of them use stuck-at fault model to identify defect locations [1]. In the proposed methodology, we enhanced an excitation condition extraction procedure by back tracing from the observation points with fault effects during fault simulation to find the most possible input conditions that cause the fault effects. Additionally, a new method is proposed to locate defective cell locations without using stuck-at fault model. Experimental results on industrial designs proved the effectiveness of the proposed methodology.

Summary form only given, as follows. Power-aware testing is facing more and more challenges in terms of test power analysis as well as test power management due to the ever-growing gap between functional power and test power for low-power LSI circuits. This special session, presented by top experts from both academia and industry, will provide firsthand information on state-of-the-art solutions as well as insightful perspectives on future R&D directions about power-aware testing. It will help researchers and practitioners alike in advancing poweraware test technologies for low-power LSI circuits, the enabler of all energy-smart electronic devices that are now indispensable in our everyday life.

A method based on dynamic design partition is presented to increase the throughput of volume diagnosis by increasing the number of failing dies diagnosed within a given time T using given constrained computational resources C. Recently we proposed a static design partitioning method to reduce the diagnosis memory footprint for large designs [1] to achieve this objective. The method in [1] is applied once for each design without using the information of test patterns and failure files, and then diagnosis is performed on an appropriate block(s) of the design partition for a failure file. Even though the memory footprint of diagnosis is reduced the diagnosis quality is impacted to unacceptable levels for some types of defects such as bridges. In this paper, we propose a new failure dependent design partitioning method to improve volume diagnosis throughput with a minimal impact on diagnosis quality. For each failure file, the proposed method first determines the small partition needed to diagnose this failure, and then performs the diagnosis on this partition instead of the complete design. Since the partition is far smaller, both the run time and the memory usage of diagnosis can be significantly reduced better than when earlier proposed static partition is used. Extensive experiments were conducted on several large industrial designs to validate the proposed method. It has been observed that the typical partition size for various defects is less than 3% of the size of the original design. Also diagnosis runs much faster (>;2X) on the partition. Combining these two factors, the throughput of volume diagnosis can be improved by an order of magnitude.

We present SATSEQ, a timing-aware ATPG system for small-delay faults in non-scan circuits. The tool identifies the longest paths suitable for functional fault propagation and generates the shortest possible sub-sequences per fault. Based on advanced model-checking techniques, SATSEQ provides detection of small-delay faults through the longest functional paths. All test sequences start at the circuit's initial state; therefore, overtesting is avoided. Moreover, potential invalidation of the fault detection is taken into account. Experimental results show high detection and better performance than scan testing in terms of test application time and overtesting-avoidance.

The conventional detection conditions for transition faults do not predict fault effects that may be created when transition faults are activated and/or propagated by pulses (or hazards). For this, detection conditions that take hazards into consideration need to be used. However, since the occurrence of pulses cannot be predicted accurately based on a gate-level circuit description, the transition fault model becomes more susceptible to pattern-dependent effects, where errors on observed outputs that are predicted by the fault model may not appear in a circuit-under-diagnosis. This paper considers the implications of these pattern-dependent effects on the resolution of fault diagnosis based on transition faults.

Recently a new method called ATE assisted compaction for achieving test response compaction has been proposed. The method relies on testers to achieve additional compaction, without compromising fault coverage, beyond what may already be achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be used with any design including legacy designs. In this work, we enhance this method so that the level of diagnostic resolution achieved without it can be maintained. Experimental results on larger ISCAS-89 show that additional test response compaction can be achieved while diagnostic resolution for single and double stuck-at faults is not adversely impacted by the procedure.

Recently statistical yield learning based on volume diagnosis has become popular. Volume diagnosis requires a large amount of diagnosis results to be produced within a reasonable time. However, it is challenging to achieve the desired throughput for modern designs with continuously increasing size. In this paper, we propose a method to partition a design under diagnosis into blocks together with a diagnosis flow at the block level. The diagnosis throughput is improved because more diagnosis jobs can be run concurrently and each job runs faster due to the reduced memory. A measure is also proposed to estimate the impact on diagnosis caused by design partitioning. Experimental results on benchmark circuits and several industrial designs show that diagnosis using circuit blocks has minimal impact on diagnosis accuracy and resolution. It is also demonstrated that the proposed measure is a good metric in predicting the impact on diagnosis.

Growing test data volume and excessive test power consumption in at-speed scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power in at-speed delay test utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results for a set of industrial circuits show that the proposed method, on average, reduces test data volume by a factor 2.7, switching activity during scan shift by a factor of 5 and peak switching activity during test response capture by a factor of 2.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that low voltage testing improves detectability of bridge fault, this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

It was recently observed that the methods to generate scan based tests with low switching activity cause about 40% less activity than functional tests. Thus such tests may cause test escapes as they may not adequately stress the circuits under test. In this work we propose a method called Max-Fill to generate high quality partially-functional broadside delay tests. The generated tests are shown to cause switching activity close to the switching activity during functional operation. The method computes a set of reachable states in which states are likely to cause high switching activity. During test generation phase, these states are used as background states to fill the unspecified bits of test cubes. Additionally, the number of test patterns produced is less than that produced by low power test methods. Experimental results for ISCAS-89 circuits are given.

Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.

Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.

Transparent-scan is a test application scheme for scan circuits. It provides unique opportunities for test compaction that do not exist with the standard test application scheme. We show that it also provides unique opportunities for reducing the power dissipation of a scan-based test set. After translating a standard scan-based test set into a transparent-scan sequence, we apply two operations for reducing the power dissipation of the sequence. The first operation attempts to remove a test vector that causes high power dissipation. The second operation attempts to replace a scan clock cycle with a functional clock cycle, or a functional clock cycle with a scan clock cycle, in order to reduce the power dissipation. Both operations are implemented such that they reduce the power dissipation without reducing the fault coverage. We also consider a third operation that attempts to complement arbitrary values in the transparent-scan sequence in order to further reduce the power dissipation.

One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as complements to skewed-load and broadside tests, and also allows them to be computed efficiently. We discuss these properties in the context of transition faults. We describe procedures for selecting the constant vector for the state inputs during a scan operation, and for generating fixed-state tests. We present experimental results to demonstrate the transition fault coverage improvements possible with these tests.

We consider the use of necessary assignments for input lines, referred to as input necessary assignments, as part of a test generation process for path delay faults in standard-scan circuits. Input necessary assignments are computed in polynomial time and provide a unified framework for identifying undetectable faults and generating tests for detectable faults. Within this framework, large numbers of path delay faults can be considered efficiently and accurately. The proposed test generation procedure is able to resolve large numbers of path delay faults associated with the longest paths in benchmark circuits by detecting the faults using broadside tests or showing that they are undetectable by such tests. We also consider the use of input necessary assignments for test compaction.

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the second capture cycle. As a result, a functional broadside test may detect faults that cannot affect functional operation (redundant faults). Addressing this issue completely requires full sequential test generation. We discuss an alternate solution that fits naturally with an existing process for generating functional broadside tests.

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests were defined and studied in the context of full-scan circuits. In this work, we study the definition of broadside and functional broadside tests in partial-scan circuits. A unique property we show is that if the unscanned state variables are observable (through the application of input sequences or through observation points), the fault coverage achievable with functional broadside tests is independent of the level of scan and the subset of scanned state variables. This implies that when functional broadside tests are used to avoid overtesting, using lower percentages of scanned state variables may be possible without reducing the fault coverage significantly. Experimental results support this point.

Both test compaction and test data compression methods provide an opportunity for a tester to apply modified versions of each test, in addition to the original test. We take advantage of this opportunity to achieve additional test data volume reductions. One way to modify a test is to complement some or all of its bits. We represent the way in which modified tests will be obtained by a complementation vector. Experimental results demonstrate that, even when a test set has minimum or close-to-minimum size, the use of a complementation vector allows us to reduce the size of the stored test set further, and almost always below the known lower bound on the size of a test set. The use of a complementation vector is equivalent to a modulo-2 addition operation. We generalize it to modulo-Maddition, for a constantM≥ 2. With modulo-Maddition, each stored test yields up toMtests. It is thus possible to reduce the size of the stored test set even further.

We describe a storage scheme for functional test sequences where a test sequenceTis associated with a primary input vectorBcalled a background vector.Tis stored by storing only the differences between its test vectors andB. We describe a procedure for computing a background vectorBfor a given test sequenceT. We also describe a procedure that modifiesTso as to reduce its storage requirements with respect toB. We present experimental results demonstrating that the single background vectorB, computed based onT, allowsTto be modified such that a vast majority of its entries are equal to the corresponding entries ofB. Consequently, storage ofTreduces to storage of a small number of entries. We also extend the discussion to storage ofTbased on two background vectors. A second background vector provides more flexibility in storingTas a list of entries where it is different from its background vectors. This contributes to a further reduction in storage requirements for certain circuits.

We define the strength of a test for transition faults based on the number of fault effects that can disappear without causing the test to lose the detection of target faults. The removal of fault effects represents the uncertainty created by pattern-dependent effects that can slow-down or speed-up signal-transitions, thus causing fault effects predicted by logic-level simulation to disappear. A test set that consists of higher-strength tests is less susceptible to these effects. We demonstrate that a transition fault test set with higher-strength tests also detects more path delay faults, which represent delay defects that were not targeted during test generation.

Functional broadside tests were defined to address overtesting that may occur with unrestricted scan-based tests. However, the fault coverage achievable by functional broadside tests is lower than the fault coverage achievable by unrestricted scan-based tests. It was observed that skewed-load tests can improve the fault coverage achievable by unrestricted broadside tests. Motivated by these observations, we define functional (and partially-functional) skewed-load tests to improve the fault coverage of functional broadside tests while attempting to curb overtesting. We present experimental results to demonstrate the ability of functional skewed-load tests to improve the fault coverage without exceeding the maximum switching activity of functional broadside tests (which is one indication of potential overtesting).

A test for a delay fault can be considered as covering a transition on one or more lines. A bias in the transition coverage of a delay test set implies that more rising or more falling transitions are covered by the test set. Such a bias is not captured by fault coverage metrics that consider both types of transitions together. We study the bias in the transition coverage of test sets for path delay faults. The results demonstrate that the bias is circuit-dependent. It also depends on the type of two-pattern tests used. In general, broadside tests show more bias than skewed-load tests, while enhanced-scan tests show little bias. We also consider the use of partial-enhanced-scan for reducing the bias exhibited by broadside tests.

In this work, we propose a method to improve diagnosis results when multiple physical defects are present in circuits under diagnosis. To improve diagnosis results when multiple defects are present in a circuit under diagnosis, the proposed method includes (i) analyzing relations among locations of logic faults and their diagnostic metrics to carefully derive physical faults, (ii) a new set covering procedure and (iii) a method to assign scores to faults to derive candidate sets of faults. Experimental results on several industrial designs and several cases of silicon defects show the effectiveness of the proposed diagnosis method.

We describe a storage scheme for functional test sequences where a test sequence T is associated with a primary input vector B called a background vector. T is stored by storing only the differences between its test vectors and B. We describe a procedure for computing a background vector B for a given test sequence T. We also describe a procedure that modifies T so as to reduce its storage requirements with respect to B. We present experimental results demonstrating that the single background vector B, computed based on T, allows T to be modified such that a vast majority of its entries are equal to the corresponding entries of B. Consequently, storage of T reduces to storage of a small number of entries.

Functional broadside tests were defined to avoid overtesting that may occur under structural scan-based tests. Overtesting occurs due to non-functional operation conditions created by unreachable scan-in states. Functional broadside tests were computed assuming that functional operation starts after the circuit is synchronized. We discuss the definition of functional broadside tests for the case where hardware reset is used for bringing the circuit into a known state before functional operation starts. We show that the set of reachable states for a circuit with hardware reset contains the set of reachable states based on a synchronizing sequence. Consequently, the set of functional broadside tests and the set of detectable faults for a circuit with hardware reset contain those obtained based on a synchronizing sequence. In addition, there are differences between different reset states in the sets of reachable states and the sets of detectable faults.

The concept of test vector chains was introduced in the context of simulation-based test generation. Test vector chains provide a specific algorithm for performing single-bit changes in order to obtain new test vectors from existing ones. In this algorithm, two test vectors tη and ti2 are used. The test vector chain C(tn,ti2) is obtained by gradually modifying tη into ti2. Starting from tη, each additional test vector in C(tn,ti2) is one bit further from tη and one bit closer to ti2 until ti2 is obtained. It was demonstrated that a test set T has a significant number of test vector chains that are effective in (1) increasing the numbers of detections of faults that were targeted during the generation of Γ; (2) increasing the fault coverage of faults that were not targeted during the generation of Γ; and (3) increasing the fault coverage of target faults when T does not detect all the target faults.

A deterministic broadside test generation procedure is proposed for transition path delay faults. Under this fault model, a path delay fault is detected if and only if all the individual transition faults along the path are detected by the same test. This is important for detecting both small and large delay defects. To handle the complexity of test generation, the procedure consists of five sub-procedures: a test generation procedure for transition faults, a preprocessing procedure that identifies undetectable transition path delay faults without performing test generation, a fault simulation procedure that identifies transition path delay faults that are detected by the tests for transition faults, a heuristic procedure similar to dynamic test compaction for transition faults that generates tests without backtracking on decisions made for previously detected faults, and a complete branch-and-bound procedure. Experimental results show that for most of the transition path delay faults in benchmark circuits either a test is found or the fault is identified as undetectable.

The existence of multiple copies of the same functional units in a design allows on-line testing to be performed by comparing the output responses of identical circuits when identical input sequences are applied to them. We extend the output response comparison scheme for identical sequential circuits in order to increase the fault coverage and reduce the fault latency of an unknown input sequence. The extension is based on using state variables in addition to primary outputs as part of the output response comparison scheme. The proposed procedure orders the state variables of the circuits such that each additional state variable in the ordered list has the highest possible impact on the on-line testability of the circuits. Depending on other constraints, the first state variables in the list can be selected for inclusion in the output response comparison scheme.

The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work to show that such tests can also be used for testing additional transistor stuck-open faults. Experimental results for coverage improvement in several ISCAS-89 benchmark circuits will be discussed.

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

A multi-cycle (or multi-pattern) scan-based test consists of several primary input patterns, which are applied consecutively in functional mode, between scan operations. Multi-cycle tests can reduce the total number of cycles needed to achieve a target fault coverage. Additionally, such tests exercise the circuit in its functional mode of operation during several clock cycles where the primary input patterns are applied. This is important for detecting defects that are not detected with two-pattern scan-based tests. However, a complete test generation process for multi-pattern tests requires sequential test generation. To generate multi-pattern tests with arbitrary numbers of patterns without performing full sequential test generation, and targeting delay faults, we use a broadside test set as a basis for test generation. We introduce the operation of concatenating broadside tests, and describe a procedure that uses it to form multi-cycle tests. We present experimental results demonstrating that the test sets require significantly fewer test cycles than broadside test sets, for the same transition fault coverage.

Multiple faults are typically detected by test sets for single faults. For bridging faults, we show that fault activation conditions are more difficult to create for certain multiple faults than for the single faults that comprise them. As a result, a test set for single bridging faults may leave significant percentages of detectable multiple faults undetected. We discuss three such cases, corresponding to three types of bridging faults, and present experimental results for one of them. As part of this study we consider the ability of a 10-detection test set for single stuck-at faults to detect multiple bridging faults of this type.

Equivalence and dominance relations used earlier in fault diagnosis procedures are defined as relations between faults, similar to the relations used for fault collapsing. Since the basic entity of diagnostic fault simulation and test generation is a fault pair, and not a single fault, we introduce a framework where equivalence and dominance relations are defined for fault pairs. Using equivalence and dominance relations between fault pairs, we define a fault pair collapsing process, where fault pairs are removed from consideration under diagnostic fault simulation and test generation since they are guaranteed to be distinguished when other fault pairs are distinguished. Another concept, which was used earlier to enhance fault collapsing, is the level of similarity between faults. We extend this definition into a level of similarity between fault pairs and discuss its use for fault pair collapsing. The level of similarity encompasses equivalence and dominance relations between fault pairs, and extends them to allow additional fault pair collapsing.

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cubetis generated at an arbitrary iteration of the test generation process, the test vector improvement step modifiestso as to increase the number of yet-undetected target faults thattdetects. This is done in this paper using a simulation-based process. We show that even iftwas generated using dynamic test compaction heuristics, it is possible to improvetfurther. Whentis partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits oft. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).

We demonstrate that undetectable single stuck-at faults in full-scan benchmark circuits tend to cluster in certain areas. This implies that certain areas may remain uncovered by a test set for single stuck-at faults. We describe an extension to the set of target faults aimed at providing a better coverage of the circuit in the presence of undetectable single stuck-at faults. The extended set of target faults consists of double stuck-at faults that include an undetectable fault as one of their components. The other component is a detectable fault adjacent to the undetectable fault. We present experimental results of fault simulation and test generation for the extended set of target faults.

Transition path delay faults were defined to capture the behavior of both small and large delay defects in a single fault model. The number of detectable transition path delay faults as defined earlier is the same or close to the number of conventional path delay faults that are detectable under the strong non-robust propagation conditions. When the weak non-robust propagation conditions are used, the number of detectable conventional path delay faults is significantly higher. Using what are called the hazard-based detection conditions for transition faults, we define detection conditions for transition path delay faults, under which the number of detectable faults is the same or close to the number of conventional path delay faults that are detectable under the weak non-robust propagation conditions. The fault model still captures the behavior of both small and large delay defects, but the number of detectable faults is significantly higher.

The presence of an undetectable faultuimay modify the response of a detectable faultdjto a test set used for fault diagnosis. This may impact the accuracy of fault diagnosis based on the responses of single faults. Many state-of-the-art diagnosis processes are based on the responses of single stuck-at faults even though their goal is to diagnose defects (including multiple defects) that are different from stuck-at faults. Therefore, we study the effects of undetectable single stuck- at faults on the accuracy of fault diagnosis based on the responses of single stuck-at faults. For this purpose, we consider the cases where the response of a double stuck-at faultui&dj, which consists of an undetectable faultuiand a detectable faultdj, is different from the response of the single faultdj. We show that there are significant, yet manageable, numbers of such faults in benchmark circuits under test sets used for fault diagnosis. In all these cases, a fault diagnosis process based on single stuck-at faults may not identify the locations ofdjanduias candidate defect sites if a defect affects the sites ofdjandui. We conclude that it is important to considerui&djduring fault diagnosis in order not to preclude the sites ofdjanduias candidate defect sites.

We define a new type of detection conditions for delay faults, referred to as hazard-based detection conditions, to enhance the coverage of delay faults using the standard scan test application methods. Some delay faults, including irredundant faults, may be undetectable under the conventional detection conditions. These faults may be detectable under the hazard-based detection conditions. The use of hazard-based detection conditions thus improves the delay fault coverage achievable for a circuit. We consider transition faults under standard scan for the study in this paper.

We propose a path selection criterion to improve the coverage of small delay defects. Under this criterion, every line in the circuit is covered by one of the longest testablepaths or subpathsthat goes through it. Earlier criteria that considered only complete paths (from inputs to outputs) did not use longest testable subpaths, which may be longer than the longest complete testable paths. Earlier criteria that considered subpaths considered only subpaths of longest paths. We apply the proposed criterion to a delay fault model called the transition path delay fault model. This model was introduced to capture both small and large delay defects. We present experimental results to demonstrate that consideration of subpaths improves the circuit coverage relative to the case where only complete paths are allowed.

We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. This is important since it provides a direct link between test quality and the circuit synthesis. We discuss robust fault models for bridging faults and interconnect open faults, and their use as part of a test generation process for a non-robust fault model.

The switching activity of scan-based tests for delay faults is considered as a test compaction heuristic. Two test compaction processes based on the switching activity are described. The results of several experiments are presented where test sets consisting of tests with different switching activity are compared based on their size as well as coverage of untargeted faults. The results demonstrate that test sets where the tests have higher switching activity are smaller. Their untargeted fault coverage is comparable, and sometimes even higher, than that of larger test sets for the same target faults. To avoid overtesting due to high switching activity it is possible to consider functional broadside tests. For other types of tests it is possible to bound the switching activity such that it would not exceed that possible during functional operation.

In this paper, we describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selected. This step allows fault diagnosis to be performed based on a single fault model after identifying the most appropriate one. We describe a specific implementation of this preprocessing step based on what is referred to as the unique output response of a fault model. As an example, we apply it to the diagnosis of multiple stuck-at faults, selecting between single and double stuck-at faults as the fault model for diagnosis. Experimental results demonstrate improvements compared to diagnosis based on single stuck-at faults, and compared to diagnosis based on both single and double stuck-at faults. We also discuss the use of a subset of double stuck-at faults for diagnosis, and the application of the proposed preprocessing step with other fault models.

A recent approach to test generation avoids the assignment of certain input values in order not to prevent target faults from being detected. The test generation process based on this approach is efficient; however, it generates large test sets. We develop a dynamic test compaction procedure for this approach. Our goal is to reduce the test set size by increasing the number of faults detected by each test vector, while keeping the computational complexity as low as that of the original procedure. This is achieved by avoiding the assignment of certain input values in order not to prevent subsets of faults from being detected.

Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed new flush tests and appropriate ordering of flush tests to achieve higher fault coverage. In this paper, we investigate detection of a set of scan cell internal bridging faults extracted from layout. We show that the detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. Half-speed flush tests we proposed earlier to improve the coverage of stuck-at, stuck-on and stuck-open faults also detect additional bridging faults. We classify the undetectable faults based on the reasons for their undetectability. We observe that the driver strengths of the scan cell inputs can be optimized to improve the bridging fault coverage. Both zero-resistance and nonzero-resistance bridging fault models are considered in this work. A low power supply voltage based test method and IDDQ testing are examined for resistive bridging fault detection.

Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that for using n-detection test sets to improve the detection of unmodeled defects. We use a heuristic to target a subset of fault pairs for n-distinguishing in order to improve the efficacy of the patterns generated for aiding diagnosis. Experimental results on the larger ISCAS benchmark circuits are presented to demonstrate the improvements in defect diagnostic resolution due to the use of n-distinguishing test sets. We use randomly selected resistive bridges to represent unmodeled defects. The experimental results also show that the coverage of unmodeled defects by n-distinguishing test sets is similar to that by n-detection test sets even though the number of n-distinguishing tests is typically smaller. This suggests the possibility of using n-distinguishing test sets in place of n-detection test sets in manufacturing test.

SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outperforms earlier static approaches by approximately 23%.

Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number of stuck-at fault pairs it distinguishes. We use the static test compaction process as part of a process that constructs the transparent-scan sequence gradually, using test compaction to prevent the length of the sequence from becoming unnecessarily long.

In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected cells is large. Experimental results on several industrial designs show the effectiveness of the proposed procedures in improving diagnostic resolution, reducing run times of test generation and also reducing the number of test patterns.

We describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selected. This step allows fault diagnosis to be performed based on a single fault model after identifying the most appropriate one. We describe a specific implementation of this preprocessing step based on what is referred to as the unique output response of a fault model. As an example, we apply it to the diagnosis of multiple stuck-at faults, selecting between single and double stuck-at faults as the fault model for diagnosis. Experimental results demonstrate improvements compared to diagnosis based on single stuck-at faults, and compared to diagnosis based on both single and double stuck-at faults.

This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG.

To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the errors in responses due to defects which are captured in scan cells are not directly observed. We propose a simple and effective way to enhance the diagnostic resolution achievable by production tests with minimal increase in pattern counts. In this work we present experimental results for the case of multiple scan chain faults to demonstrate the effectiveness of the proposed method.

We define the notion of a lingering synchronization effect. Such an effect occurs when a primary input cube (an incompletely-specified primary input vector) determines the state of a circuit for several time units after it is applied. Such a primary input cube may prevent certain faults from being detected when it appears in a test sequence. It should therefore be avoided when the goal is to achieve a high fault coverage. We demonstrate that benchmark circuits have primary input cubes with small numbers of specified values (typically one or two), which have lingering synchronization effects. In some cases, the synchronization effects linger for large numbers of time units. We also describe a random test generation process that avoids primary input cubes with lingering synchronization effects, and achieves high fault coverage for benchmark circuits.

We describe a method for improving the quality of n-detection test sets. Unlike earlier methods for achieving the same goal, the proposed method is based on the conventional definition of the number of detections and uses a conventional n-detection test generation process. Under the proposed method, the set of target faults is partitioned into two or more subsets. n-detection test generation is carried out for each subset separately. The resulting test sets are combined into a single test set. Partitioning causes more faults to be targeted directly, and fewer faults to be dropped due to accidental detection. The fault subsets can be selected based on detection conditions of common defects. In this work we partition the set of faults into a subset that consists of all the stuck-at 0 faults, and a subset that consists of all the stuck-at 1 faults. We demonstrate through experimental results that for the same test set size, partitioning the set of faults improves the coverage of untargeted faults (non-feedback four-way bridging faults) compared to n-detection test generation for the unpartitioned set of faults.

A necessary assignment for a fault f is a line value that must be assigned by a test vector that detects f. A higher number of necessary assignments translates into a lower test generation effort since the test generation process has a larger number of values that it must assign, and therefore, fewer options that it can explore. To increase the number of available necessary assignments, we define approximate necessary assignments as line values that are assigned by most of the test vectors for a fault. We describe a heuristic procedure for computing approximate necessary assignments for inputs and demonstrate their effectiveness in reducing the test generation effort of a random test generation process.

We study a property of circuit states referred to as persistence. The persistence pi(s) of a state s is the number of next-state variables whose values are specified (0 or 1) when a fully-unspecified primary input vector is applied to the circuit in state s. When a next-state variable Yi is specified under a fully-unspecified primary input vector, there are faults in the input cone of Yi that cannot be detected on Yi. We demonstrate through experimental results that when lower-persistence states are used as scan-in states, the resulting tests detect larger numbers of faults. Low-persistence states are thus preferable as scan-in states during test generation. We also discuss the computation of low-persistence states.

This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesized International Symposium on Circuits and Systems benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.

The functional operation of a synchronous sequential circuit is defined to start after the circuit is initialized to a known state, typically by a synchronizing sequence. The states that the circuit can visit after it is synchronized are called reachable states, and functional operation consists of state transitions between reachable states. We expand the definition of functional operation to include all the state transitions that may be traversed during the application of the synchronizing sequence. This adds certain state transitions that involve unreachable states to the definition of functional operation. Expanding the definition of functional operation is justified by the fact that the circuit needs to be designed for correct operation during the synchronization process. It is advantageous when functional broadside tests are used to avoid overtesting. We study the effect of the expanded definition on the coverage of transition faults.

In this paper, we describe a new transition fault model for synchronous sequential circuits. Similar to previous models, it addresses the fact that delayed signal-transitions span multiple clock cycles when a test sequence is applied at-speed. It addresses this issue in a different way than earlier models. The model requires the activation of single stuck-at faults with opposite stuck-at values on the same linegat consecutive time units. In addition, it requires the detection of both faults (as single faults) at the same or later time units. Due to the activation of the faults at consecutive time units, there is a 1 rarr 0 or 0 rarr 1 transition at the fault siteg. Since both faults are eventually detected, a deviation from the expected value at either the first or second time unit due to a delay fault ongor due to transitions that started earlier and did not settle will be (or is likely to be) detected. The model can be used together with other models to increase the confidence that delay defects will be detected. As an added advantage, the model helps detect other types of faults that require two-pattern tests, such as transistor stuck-open faults.

We extend the concept of forward-looking reverse order fault simulation ton-detection test sets. Forward-looking reverse order fault simulation is an efficient static test compaction process similar to reverse order fault simulation, but with the advantage that it results in test sets that do not contain any unnecessary tests. The application of test compaction procedures ton-detection test sets is important since the test sets are larger than conventional test sets. We demonstrate that forward-looking reverse order fault simulation produces smaller test sets than reverse order fault simulation and measure the quality of the resulting test sets by their bridging fault coverage.

We describe a method for online testing of delay faults based on the comparison of output responses of identical circuits. The method allows one of the circuits to participate in useful computations during the testing process, while the other circuit must be idle. We refer to this method as semiconcurrent online testing. While unknown input vectors are applied to the circuit that participates in useful computations, the proposed method applies modified vectors to the idle circuit. In this way, different conditions are created for the detection of delay faults, allowing identical delay faults that affect both circuits to be detected. In designing the modified vectors, we ensure that the expected fault-free responses of the two circuits are identical. We also ensure that the hardware for modifying the vectors applied to the idle circuit will be easy to implement on-chip.

In enhanced-scan circuits, a two-pattern test < t i , t j > for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test < t i , t j > based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We investigate a complementary view whereby the goal is to avoid the assignment of certain input values in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Other potential uses of the computed input cubes are in a deterministic test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults. We consider stuck-at faults in full-scan circuits. We also extend the discussion to four-way bridging faults.

A procedure proposed earlier for improving the fault coverage of a random primary input sequence modifies the input sequence so as to avoid repeated synchronization of state variables. We show that in addition to the values of state variables, it is also important to consider repeated setting of other lines to the same values. A procedure and experimental results are presented to demonstrate the improvements in fault coverage of random primary input sequences when the values of selected lines are considered.

We introduce the concept of test vector chains, which allows us to obtain new test vectors from existing ones through single-bit changes without any test generation effort. We demonstrate that a test setT0has a significant number of test vector chains that are effective in increasing the numbers of detections of target faults, i.e., faults targeted during the generation ofT0, as well as untargeted faults, i.e., faults that were not targeted during the generation ofT0.

For volume production of VLSI designs in future technologies fast and accurate diagnosis of manufacturing defects on a large number of chips is necessary to ramp up yields. Methods to speed up commonly used effect-cause fault diagnosis procedures have been recently proposed. These include the use of fault response dictionary. However, for very large industrial designs, these methods either need very large dictionaries or they drastically reduce the speedup achievable by using dictionaries. In this work we propose a method to achieve higher speedup with small sized dictionaries. We achieve this by identifying a set of faults called hyperactive faults for which we create a novel dictionary. Experimental results are presented to demonstrate the effectiveness of the proposed method.

We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.

We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthesis of the circuit. The stuck-at fault model is robust, but other fault models such as certain bridging fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. The ability to achieve 100% fault coverage, or understand why it is not achievable, is important since the requirement to achieve high test quality translates into a requirement to achieve complete fault coverage for target faults, regardless of the metrics used to measure test quality. We discuss a robust bridging fault model and its use as part of a test generation process for a non-robust bridging fault model (a non-robust bridging fault model may have to be used in order to capture the behavior of bridging defects). We also present experimental results related to the robust bridging fault model.

We describe a new type of fault dictionary called a same/different fault dictionary. The same/different fault dictionary is similar to a pass/fail fault dictionary in that it contains a single bit bijfor every modeled fault fiand test vector tj. However, in a pass/fail fault dictionary, bijis determined by comparing the output vector of the faulty circuit with the output vector of the fault free circuit; while in a same/different fault dictionary, bijis determined by comparing the output vector of the faulty circuit with a preselected output vector called a baseline output vector. By selecting appropriately the baseline output vectors for all the test vectors, it is possible to obtain increased diagnostic resolution with a same/different fault dictionary compared to a pass/fail fault dictionary. We describe a procedure for selecting baseline output vectors and present experimental results.

Multiple-voltage is an effective dynamic power reduction design technique, commonly used in low power ICs. To the best of our knowledge there is no reported work for diagnosing multiple-Vdd enabled ICs and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. Using synthesized ISCAS benchmarks, with realistic extracted bridges and parametric fault model; the paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multi-Vdd diagnosis algorithm.

For fault models with large numbers of faults, such as bridging faults, fault collapsing based on dominance relations can be effective in reducing the test generation time by reducing the number of target faults. When dominance relations are used for fault collapsing, a fault fjis excluded from the set of target faults F if it dominates a fault fiin F. However, if firemains undetected after test generation, fjmay remain undetected as well. We define safe fault collapsing to address this issue. For safe fault collapsing with a parameter s, fjis excluded from the set of target faults F only if fjdominates at least s faults fi1,fi2, hellip ,fisin F. In this way, if any of the s faults dominated by fjis detected, fjwill be detected as well. A higher value of s increases the likelihood of detecting fjwithout targeting it. We describe a procedure for computing safe collapsed fault sets, and present experimental results of test generation for four-way bridging faults.

The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture to detect such defects is proposed. Unlike other sequences, like checking experiments, the enhancements are simple and independent of the circuit under test.

Nearly half of the transistors in the logic parts of large VLSI designs typically reside inside scan cells. Faults in scan cells may affect functional operation if left undetected. Such undetected faults may also affect the long term reliability of shipped products. Nevertheless, current test generation procedures do not directly target faults internal to the scan cells. Typically it is assumed that scan chain tests, called flush tests, test the scan cells sufficiently. We showed that flush tests applied at slower clock rates, called half-speed flush tests, and tests for scan cell inputs and outputs, detect stuck-at and stuck-on faults internal to scan cells to a similar extent as checking sequence based tests proposed earlier. In this work, we investigate the detection of opens in transistors internal to scan cells. A new flush test and a new method to apply flush tests are proposed to greatly enhance the coverage of opens. We also propose new scan based tests to further increase the coverage of opens. The proposed tests are shown to achieve the maximum possible coverage of opens in transistors internal to scan cells.

We describe a synthesis-for-testability approach targeting broadside testing of transition faults. We refer to this process as synthesis for broadside testability. Unlike design-for-testability (DFT) procedures that require additional control inputs to implement DFT modes of operation, synthesis for broadside testability uses only the standard scan design and relies on broadside tests to detect target faults. The proposed procedure improves the testability of a circuit by changing next-states of state- transitions from its unreachable states, i.e., states that the circuit cannot enter during functional operation. In this way, it replaces broadside tests of the original circuit with new broadside tests that are more effective in detecting target faults.

Functional operation of a synchronous sequential circuit is defined to start after the circuit is initialized to a known state, typically by a synchronizing sequence. The states that the circuit can visit after it is synchronized are called reachable states, and functional operation consists of state-transitions between reachable states. We expand the definition of functional operation to include all the state-transitions that may be traversed during the application of the synchronizing sequence. This adds certain state-transitions that involve unreachable states to the definition of functional operation. Expanding the definition of functional operation is justified by the fact that the circuit needs to be designed for correct operation during the synchronization process. It is advantageous when functional broadside tests are used to avoid over- testing. We study the effect of the expanded definition on the coverage of transition faults.

Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.

It was shown before that tests applied under nonfunctional operation conditions, which are made possible by scanning in an unreachable state, may lead to unnecessary yield loss. To address this issue, functional broadside tests were defined as broadside tests that use only reachable states of the circuit as scan-in states. Earlier procedures for generating functional broadside tests were not complete, i.e., they did not always detect all the detectable faults or prove that all the undetectable faults are undetectable. In this paper, we address the completeness of the functional broadside tests for transition faults. We describe the implementation of a test-generation procedure that can, for every transition fault, either find a functional broadside test or prove that the fault is undetectable under the functional broadside tests. We present experimental results where complete results are achieved for almost all the benchmark circuits considered.

A transition fault model is described, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal-operation conditions. However, fault simulation and test generation for standard transition faults become significantly more complex due to the need to handle faulty signal transitions that span multiple clock cycles. As a result, each transition fault needs to be considered multiple times, with multiple sizes of the extra delay on the faulty line. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur, thus allowing faults of all possible sizes to be encompassed in a single fault. Fault detection potentially occurs when an unspecified value reaches a primary output. "Pessimistic," "optimistic," and "random" versions of the fault model and corresponding fault coverages are defined. If a single fault coverage is to be computed, the pessimistic one provides the lowest fault coverage. By using the optimistic or random version, it is possible to obtain a range of possible fault coverages that is analogous to the range of sizes of transition faults. For certain applications, it is also possible to include more than one version of every fault in a single set of target faults and to compute a single fault coverage. Experimental results of fault simulation and test generation are presented to demonstrate the behavior of the model and to compare it with other fault models.

Random test sequences may be used for manufacturing testing as well as for simulation-based design verification. This paper studies one of the reasons for the fact that random primary input sequences achieve very low fault coverage for synchronous sequential circuits. It is shown that a synchronous sequential circuit may have input cubes, or incompletely specified input vectors, that synchronize a subset of its state variables, i.e., it forces them to certain specified values. When an input cube c that synchronizes the subset of state variables S(c) has a small number of specified inputs, the input vectors covered by it may appear often in a random primary input sequence. As a result, the sequence will force the same values on the state variables in S(c) repeatedly. This may limit the fault coverage that the sequence can obtain. To address this issue, a procedure is described for modifying a random primary input sequence to eliminate the appearance of input vectors that synchronize subsets of state variables. It is demonstrated that this procedure has a significant effect on the fault coverage that can be achieved by random primary input sequences.

The peak power dissipated in nonscan logic during fast capture cycles of scan-based two-pattern tests for path delay faults is considered. It is first demonstrated that the peak-power dissipation for an enhanced-scan test set, which has the smallest peak-power dissipation, is lower than that for a skewed-load test set and that the peak-power dissipation for a skewed-load test set, which has the smallest peak-power dissipation, is typically (but not always) lower than that for a broadside test set. Test sets that consist of more than one type of tests are then considered. Skewed-load and broadside tests may be used together to improve the fault coverage when this is permissible by a standard scan design. It is demonstrated that using both types of tests can sometimes reduce the peak-power dissipation. Results are also presented of an experiment where an arbitrary test set of one type is modified to reduce the peak power without reducing the fault coverage by introducing tests of another type.

An n-detection test set contains different tests for each target fault. The value of is typically determined based on test set size constraints, and certain values have become standard. Appropriate values for are investigated in this paper by considering the saturation of the n-detection test generation process. As is increased, eventually, the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with drops below a certain level. Three parameters of an n-detection test set are introduced to measure the saturation of the test generation process: 1) the fraction of faults detected times or less by the test set; 2) the fraction of faults detected fewer than times by the test set; and 3) the test set size relative to the size of a one-detection test set. It is demonstrated that the behavior of each one of these parameters follows a unique pattern as is increased, and certain features of this behavior can be used to identify saturation. All the parameters can be efficiently computed during the test generation process.

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.

Functional broadside tests were defined to address overtesting that may occur due to high peak current demands when tests for delay faults take the circuit through states that it cannot visit during functional operation (unreachable states). The fault coverage achievable by functional broadside tests is typically lower than the fault coverage achievable by (unrestricted) broadside tests. A solution to this loss in fault coverage in the form of observation point insertion is described. Observation points do not affect the state of the circuit. Thus, functional broadside tests retain their property of testing the circuit using only reachable states to avoid overtesting due to high peak current demands. However, the extra observability allows additional faults to be detected. A procedure for observation point insertion to improve the coverage of transition faults is described. Experimental results are presented to demonstrate that significant improvements in transition fault coverage by functional broadside tests is obtained.

Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift test method has the advantage that it provides higher fault coverage at reduced test generation time and test pattern counts. However a concern expressed often in the literature is the potential over testing or yield loss caused by the fact that launch off shift operates the circuit under test in non-functional manner. In this paper we present data, for the first time, which points to another potential problem with launch off shift tests. The data presented for ISCAS-89 benchmark circuits shows that a considerable numbers of functionally detectable transition delay faults are not detected by the normally used launch off shift tests that use a single fault activation cycle. Functionally detectable faults that escape tests could cause circuit malfunction in normal operation. Thus launch off shift tests when used in manufacturing test may result in test escapes. We also present data that shows that if launch off shift tests with multiple fault activation cycles are used essentially all functionally detectable faults can be detected.

We describe a diagnostic test generation procedure that targets the equivalence classes of the test set as it is being generated, instead of considering one fault pair at a time (an equivalence class contains faults that are indistinguished by the test set). When an equivalence class is targeted, all the fault pairs in the equivalence class are targeted simultaneously. This reduces the number of test generation targets, and as a result, it reduces the number of tests in the final test set as well as the test generation time. The implementation of the diagnostic test generation procedure is based on a test elimination process that can accommodate equivalence classes of any size.

The use of multiple scan chains was shown to improve the coverage of transition faults achieved by skewed-load tests. For broadside tests, the number of scan chains does not affect the transition fault coverage. We describe an enhanced broadside configuration under which increasing the number of scan chains helps increase the fault coverage. In the enhanced configuration, the first flip-flop of a scan chain operates in skewed-load mode while the other flip-flops operate in broadside mode. This provides flexibility in determining the value of the first flip-flop of every scan chain under the second pattern of a broadside test, thus increasing the transition fault coverage. We also describe a procedure that makes small modifications to a given scan chain configuration in order to improve the transition fault coverage.

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values that should not be assigned to inputs in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Potential uses of the computed input cubes are in a test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults

We describe a diagnostic test generation procedure that deals with the large numbers of target fault pairs by considering subsets of faults. Each subset of faults is targeted separately during diagnostic test generation, and fault pairs are defined only out of the faults included in a subset. With M subsets of size K, the number of fault pairs considered is at most MK(K-1)/2 instead of N(N-1)/2 for a circuit with N target faults. Fault subsets can be defined using information about faults that are likely to be difficult or important to distinguish. In this work, fault subsets are defined based on structural analysis of the circuit.

We consider the problem of determining the location of open defects in interconnects of deep submicron (DSM) designs. The target defect sites for this work are the vias in interconnects which are known to be defect prone. It is known that in DSM designs below 90 nm technology the circuit parameters may vary widely from nominal or design values and process variations make them less predictable. Thus it becomes necessary to develop methods for locating defect sites without accurate knowledge of circuit parameters. Logic diagnosis which is based on gate level net lists is one such method but the resolution of defect sites obtained by logic diagnosis is considered to be unacceptably low for locating open vias. We investigate a procedure that uses minimal information beyond the net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure.

An n-detection test set contains n different tests for each target fault. The value of n is typically determined based on test set size constraints, and certain values have become standard. In this work we investigate appropriate values for n by considering the saturation of the n-detection test generation process. As n is increased, eventually the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with n drops below a certain level. We introduce three parameters of an n-detection test set to measure saturation of the test generation process: (1) the fraction of faults detected n times or less by the test set, (2) the fraction of faults detected fewer than n times by the test set, and (3) the test set size relative to the size of a one-detection test set. We demonstrate that the behavior of each one of these parameters follows a unique pattern as n is increased, and certain features of this behavior can be used to identify saturation. All the parameters are easy to compute during the test generation process.

In this paper we present practical techniques that enable diagnosis of defective library cells in a failing die. Our technique can handle large industrial designs and practical situations like compressed test patterns with multiple exercising conditions per pattern and sequence dependent defects. Being able to accurately differentiate between cell-internal and interconnect defects leads to a faster root cause failure analysis at a reduced cost. This capability was applied on an AMD graphics chip using 90nm at TSMC. In all of the failing dies that underwent physical failure analysis, the defective library cell identified by diagnosis was verified to be correct by failure analysis. Currently this capability is successfully used to diagnose another design using TSMC’s 65nm technology.

Autoscan is a design-for-testability approach proposed earlier that uses scan chains without external scan inputs or outputs in order to reduce the test application time and test data volume of scan. We describe three improvements to the basic autoscan design-for-testability approach based on the following observation. Under autoscan, due to the elimination of external scan inputs, the first flip-flop of a scan chain can only receive its value from the corresponding next-state line. Thus, its state cannot be controlled directly by a scan operation. In the improved autoscan approach, we allow the inverted next-state line to drive the first flip-flop of a scan chain during scan operations. We refer to the improved autoscan approach as autoscan-invert. We describe a scan synthesis procedure appropriate for autoscan-invert and present experimental results.

In this paper we present a new technique to speed up the effect-cause defect diagnosis by using a dictionary of very small size. In the proposed method, a dictionary of small size is used to reduce the number of events (gate evaluations) during the simulation of failing patterns and also a procedure to select a subset of passing patterns for simulation. Although the dictionary size is smaller, experimental results show speed up of effect-cause diagnosis by up to 156times. Experimental results from industrial designs validate the effectiveness of the proposed method.

Generation of$n$-detection test sets is typically done for a single fault model. This paper investigates the generation of$n$-detection test sets by pairing each fault of a target fault model with$n$faults of a different fault model. Tests are generated such that they detect both faults of a pair. To facilitate test generation, the faults included in a single pair are selected such that they have overlapping requirements for their detection. The advantage of this approach is that it ensures the detection of additional faults that would not be targeted during the$n$-detection test generation process for a single fault model. Experimental results with transition faults as the first fault model and four-way bridging faults as the second fault model are presented.

Diagnostic fault simulation is used to determine the pairs of faults distinguished by a given test set or test sequence. Diagnostic test generation is used to generate tests that distinguish pairs of faults. Typically, the test sets or test sequences contain tests that detect all the detectable target faults. In this paper, a framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets. These characteristics are used to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set. Such fault pairs do not need to be considered during diagnostic fault simulation or test generation that starts from a fault detection test set. Experimental results for single stuck-at faults in full-scan benchmark circuits demonstrate that only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. The concept of -sets is extended to define z-detections. This concept uses the results of conventional fault simulation to determine additional fault pairs that are guaranteed to be distinguished by a fault detection test set. The concept of z-sets is also extended to define difference-sets (or d-sets) that provide even fewer targets for diagnostic test generation.

This article proposes a new online voltage scaling (VS) technique for battery-powered embedded systems with real-time constraints. The VS technique takes into account the execution times and discharge currents of tasks to further reduce the battery charge consumption when compared to the recently reported slack forwarding technique [Ahmed and Chakrabarti 2004], while maintaining low online complexity of O(1). Furthermore, we investigate the impact of online rescheduling and remapping on the battery charge consumption for tasks with data dependency which has not been explicitly addressed in the literature and propose a novel rescheduling/remapping technique. Finally, we take leakage power into consideration and extend the proposed online techniques to include adaptive body biasing (ABB) which is used to reduce the leakage power. We demonstrate and compare the efficiency of the presented techniques using seven real-life benchmarks and numerous automatically generated examples.

We describe a procedure for forming n -detection test sets for n >1 without applying a test generation procedure to target faults. The proposed procedure accepts a one-detection test set. It extracts test cubes for target faults from the one-detection test set, and merges the test cubes to obtain new test vectors. By extracting and merging different test cubes in different iterations of this process, an n -detection test set is obtained. Merging of test cubes does not require test generation or fault simulation. Fault simulation is required for extracting test cubes for target faults. We demonstrate that the resulting test set is as effective in detecting untargeted faults as an n -detection test set generated by a deterministic test generation procedure. We also discuss the application of the proposed procedure starting from a random test set (instead of a one-detection test set).

Improving performance, reducing energy consumption and enhancing reliability are three important objectives for embedded computing systems design. In this paper, we study the joint impact of cache size selection on these three objectives. For this purpose, we conduct extensive fault injection experiments on five benchmark examples using a cycle-accurate processor simulator. Performance and reliability are analyzed using the performability metric. Overall, our experiments demonstrate the importance of a careful cache size selection when designing energy-efficient and reliable systems. Furthermore, the experimental results show the existence of optimal or Pareto-optimal cache size selection to optimize the three design objectives

Field programmable memory BIST controllers are becoming a necessity to target manufacturing defects in embedded memories. For 65nm and below, random defects are not the only ones affecting the yield of a process. Systematic as well as parametric defects are now the predominant causes of memory failures and have to be addressed. Conventional memory BIST algorithms are usually targeted to catch random defects. In order to catch such systematic and parametric defects, it is necessary to have the flexibility to apply new algorithms to embedded memories after manufacturing. In this paper, a field programmable memory BIST architecture is proposed to support multiple loops within a test step of an algorithm, including nested loops. These controllers, therefore, guarantee supporting complex algorithm necessary to target defects during failure analysis that could help yield ramp up or reduce test escapes. In addition, the proposed architecture is modular in nature and allows optimizing the complexity of the controller along with area and performance

We show that the functionality of scan chain inputs sometimes exists in a circuit as part of its functional operation, and can be exhibited by applying specific primary input vectors. By relying on such functionality it is possible to hide scan chains as part of a solution that addresses security. It is also possible to reduce the number of external scan chain inputs that need to be added to the circuit as part of the scan implementation, or remove the need to multiplex primary inputs as scan chain inputs. We define inherent scan in functions to capture the functionality of scan chain inputs that exists in a circuit, and show that they can be computed effectively by simulation. We address the case where multiple scan chains are to be used for the circuit

Circuit behavior in the presence of interconnect open defects is affected by four major factors: the capacitances between the floating node and its neighboring nodes, the capacitances inside down-stream gates, initial trapped charge, and the threshold voltages of down-stream gates. Current interconnect open diagnosis methods either ignore all of these factors or consider a subset of them only. Thus the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present an interconnect open defect diagnosis method taking all these factors into account. Experiments conducted on benchmark circuits demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution

In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method.

Generation of n-detection test sets is typically done for a single fault model. In this work we investigate the generation of n-detection test sets by pairing each fault of a target fault model with n faults of a different fault model. Tests are generated such that they detect both faults of a pair. To facilitate test generation, we ensure that the faults included in a single pair have overlapping requirements for their detection. The advantage of this approach is that it ensures the detection of additional faults that would not be targeted during n-detection test generation for a single fault model. Experimental results with transition faults as the first fault model and four-way bridging faults as the second fault model are presented

Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application time for stuck-at faults. We show that similar advantages exist when considering transition faults. We first show that a test sequence under the transparent-scan approach can imitate the application of broadside tests for transition faults. Test compaction can proceed similar to stuck-at faults by omitting test vectors from the test sequence. A new approach for enhancing test compaction is also described, whereby additional broadside tests are embedded in the transparent-scan sequence without increasing its length or reducing its fault coverage

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach

We present a fault collapsing procedure for transition faults based on fault dominance relations. The effectiveness of the procedure is enhanced by introducing what we call extended transition faults. A standard transition fault involves a single line and a transition. A transition fault from the value to the value a' on a line g is represented as g = a rarr g = a'. An extended transition fault involves two different lines with arbitrary values, and it is represented as g1= a1rarr g2= a'2. We demonstrate the importance of extended transition faults in fault collapsing, and describe two fault collapsing procedures. We consider the effects of fault collapsing on test generation

Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%.

We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal operation conditions. However, fault simulation and test generation for the existing fault models become significantly more complex due to the need to handle faulty signal-transitions that span multiple clock cycles. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur. Fault detection potentially occurs when an unspecified value reaches a primary output. Due to the uncertainty that an unspecified value propagated to a primary output will be different from the fault free value, an inherent requirement in this model is that a fault would be potentially detected multiple times in order to increase the likelihood of detection. Experimental results demonstrate that the model behaves as expected in terms of fault coverage and numbers of detections of target faults. A variation of an n-detection test generation procedure for stuck-at faults is used for generating test sequences under this model.

The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously proposed random partitioning scheme is used to generate additional partitions. Experimental results are reported on the five largest ISCAS'89 benchmark circuits and compared with that for the random partitioning scheme and another earlier work using interval-based partitioning scheme.

When multiple copies of the same functional unit are available in a design, fault detection can be achieved by comparing the output responses of two copies (or two identical circuits). This obviates the need for storing test responses or for computing signatures of test responses. The paper proposes the testing of identical circuits using a deterministic test sequence by running the circuits at different speeds. This allows the detection of delay faults even if the two copies are affected by similar faults. The proposed method is particularly suitable in applications where functional sequences are used to bin products or to detect delay faults. The case where one of the copies is run at the full circuit speed while the other copy is run at half the full frequency was considered. To allow output response comparison under these conditions, a procedure for designing an input sequence that produces identical output vectors from the two copies every second time unit was described, assuming that both copies are fault free. It was shown that the existence of such input sequences depends on the initial state. Moreover, it is advantageous to start the two copies from different initial states. Experimental results show that very high fault coverage can be achieved by using such sequences

When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage drops leading to larger gate delays which may cause good chips to fail tests. This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests. Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

We present a test generation procedure for transition faults that minimizes the detection of functionally redundant transition faults in scan circuits. The procedure uses broadside testing. We also propose rules for identifying dominance relations between functionally redundant transition faults and functionally detectable transition faults. Dominance relations can provide two types of lower bounds. (1) A lower bound on the number of functionally detectable transition faults that cannot be detected without detecting any functionally redundant transition faults. (2) A lower bound on the number of functionally redundant faults that have to be detected if all the functionally detectable faults are detected. In our experiments with ISCAS-89 and ITC-99 benchmark circuits we achieve both of the lower bounds for almost all the circuits considered.

A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9 % to 44% average reduction in the fault simulation time for these circuits

In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them.

Design-for-testability (DFT) techniques used for synchronous sequential circuits allow redundant faults, which do not affect the functional operation of the circuit, to be detected after DFT insertion. Detecting such faults can cause a chip that operates correctly to be discarded as faulty. A solution proposed earlier was to mask output values where redundant faults are detected in the circuit with DFT, without masking other faults, which should continue to be detected. We investigate a complementary issue of generating test sets that require as little masking as possible. Our goal is to generate a test set that does not detect any redundant faults (or detects as few redundant faults as possible), such that no output values (or as few output values as possible) would have to be masked. We discuss the relationship of this problem to fault dominance. We then describe a specific procedure based on test selection for deriving test sets that detect as few redundant faults as possible while detecting all the other detectable faults.

It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result, it is shown that built-in test-pattern generation for scan circuits can be based on transition probabilities, instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. It is demonstrated that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits. The case where the circuit has a single scan chain, and the case where the circuit has multiple scan chains are considered.

This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode

Scan design allows a circuit to be tested using states that the circuit cannot enter during functional operation. It was observed that nonfunctional operation during testing may cause excessive currents that can cause a good chip to fail the test because of voltage droops caused by the excessive current demand. A good chip may also fail due to the propagation of signal transitions along nonfunctional long paths, especially during at-speed testing. This problem is studied in this paper in the context of tests for transition faults. A method for determining transition faults that are untestable under functional operation-conditions is described. Two procedures for generating transition-fault tests that use only functional operation conditions are also described. The first procedure accepts as input a broadside test set for transition faults. The second procedure accepts as input a test sequence for the nonscan circuit. Although such a test sequence is more complex to generate and simulate, it results in higher numbers of faults detected under functional operation conditions

To address the large numbers of bridging faults in a circuit, several approaches have been proposed for the selection of subsets of bridging faults as targets for test generation. A different approach that can be viewed as a fault collapsing method based on dominance relations between faults is investigated. It is enhanced by the introduction of dummy bridging faults, which are not real faults but whose tests detect large numbers of real faults. This approach is applied to nonfeedback four-way bridging faults. When no approximations are made, the proposed approach selects a subset of faults such that if they are detected all the nonfeedback four-way bridging faults are guaranteed to be detected. When this subset is too large, the proposed approach can also be applied to a subset of bridging faults preselected using other methods, e.g., realistic bridging faults or hard-to-detect bridging faults. In this case, it allows more bridging faults to be preselected. A new selection criterion and issues related to test generation for the selected faults are also investigated

The quality of test sequences for scan circuits under a test-application scheme called transparent scan as n-detection test sequences is studied. A transparent-scan sequence T is obtained from a compact single-detection combinational test set C. It is shown that for the same number of clock cycles required to apply C, the transparent-scan sequence T detects faults more times than C. It is also noted that a transparent-scan sequence based on a combinational test set contains unspecified values. The effects of specifying the unspecified values of the transparent-scan sequence on the quality of the sequence are studied by considering a random specification of these values. A procedure for modifying the scan-select subsequence of a (fully specified) transparent-scan sequence so as to improve its quality as an n-detection test sequence is also described. Finally, the extension of a transparent-scan test sequence into an n-detection test sequence that detects every target fault at least n times is considered. The results show a slower increase in test-application time with n than when combinational test sets are considered

We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented

Recently design for manufacturability (DFM) has been required to achieve higher process yield. Information obtained from silicon by testing and/or fault analysis is sometimes fed back for redesign of VLSI circuits. In this paper we propose a method to maximize defect coverage of a test set initially generated for stuck-at faults in a full scan sequential circuit by using feed back information from fault analysis. If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. The proposed method improves defect coverage of the test set by not adding new test vectors but modifying test vectors with the information obtained from fault analysis. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND/OR-type bridging faults. Experimental results show that the proposed method significantly decreases the number of non-feedback AND/OR-type bridging faults undetected by a test set generated for stuck-at faults.

This paper describes a circuit independent weighted pseudo random BIST pattern generator based on bit-flipping. The circuit dependent data is stored in memories so that different circuits can use the same BIST structure by only changing the data in the memories. New approaches are proposed for compressing and storing the bit-flipping data. Experimental results show that the proposed method reduces the size of the memory considerably while using similar test lengths as a recent method based on bit-fixing.

Circuit behavior in the presence of bridge defects is affected by three factors: bridge resistance, drive strength of bridged signals and the threshold voltages of downstream gates. Current bridge defect diagnosis methods either ignore all of these factors or consider drive strengths and/or threshold voltages only. Specifically, existing diagnosis methods have not considered the effect caused by bridge resistance. So the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present a bridge defect diagnosis method taking all three factors into account. Experiments conducted on benchmark circuits and one industrial design demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution.

Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform both a worst-case analysis and an average-case analysis to check the effect of restricting n on the unmodeled fault coverage of an (arbitrary) n-detection test set. Our analysis is independent of any particular test set or test generation approach. It is based on a specific set of target faults and a specific set of untargeted faults. It shows that, depending on the circuit, very large values of n may be needed to guarantee the detection of all the untargeted faults. We discuss the implications of these results.

We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI(f) with every circuit fault f. The heuristic estimates the number of faults that will be detected by a test generated for f. Fault ordering is done such that a fault with a higher accidental detection index appears earlier in the ordered fault set and targeted earlier during test generation. This order is effective for generating compact test sets, and for obtaining a test set with a steep fault coverage curve. Such a test set has several applications. We present experimental results to demonstrate the effectiveness of the heuristic.

A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns increase the ability to detect unmodeled defects. The proposed method can be used with any test generation procedure to improve the effectiveness of the tests in detecting unmodeled defects. Experimental results on several industrial designs show the effectiveness of defect aware tests. We also propose a measure to estimate the effectiveness of given test sets in detecting unmodeled defects.

A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation and test generation are discussed and experimental results on benchmark circuits and industrial designs are presented. The experimental results presented show that the tests generated using simpler versions of the proposed fault model achieve higher defect coverage than the tests using two currently popular methods to derive high defect coverage tests.

The large numbers of bridging faults in a circuit resulted in several approaches to the selection of a subset of faults as targets for test generation. These approaches do not guarantee that all the bridging faults (or even that all the bridging faults that are likely to occur) will be detected. We investigate a different approach to the selection of target bridging faults. The approach is based on the introduction of dummy bridging faults, which are not physical faults but whose tests detect large numbers of physical faults. We apply this approach to four-way bridging faults. When no approximations are made, the proposed approach selects a subset of faults such that if they are detected, all the four-way bridging faults are guaranteed to be detected. We also investigate approximations and a test generation approach for the selected faults.

We describe a test generation procedure for path-oriented transition faults that takes into account the fact that operating conditions may change during circuit operation. A path-oriented transition fault is detected through the longest sensitizable path that goes through the fault site. The operating conditions we consider are junction temperature and power supply voltage. Since path delays change with operating conditions, the longest path through a fault site may be different under different conditions. We show that test generation using nominal delays is not sufficient for covering the complete range of operating conditions, even if N-detection test generation is used. Therefore, operating conditions need to be addressed explicitly during test generation. However, since temperature and voltage are continuous variables and represent an infinite number of values in the range, test generation must concentrate on a small selected set of operating conditions. We discuss the selection of these conditions and demonstrate that N-detection test generation with multiple operating conditions is effective in covering the range of operation conditions almost completely.

We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.

Testing of delay faults require two pattern tests. Broadside and skewed-load testing are two approaches to test for delay faults in scan designs. The broadside approach is often preferred over the skewed-load approach in designs that also use the system clock for scan operations, since skewed-load requires a fast (at-speed) scan enable signal while broadside testing does not. In this paper, we propose new scan flip-flops to improve delay fault coverage for circuits with scan using broadside tests. The proposed flip-flops do not require a control signal to switch at-speed. This is a distinct advantage as the design effort required for timing closure of such control signals is significant. We also propose a circuit topology based flip-flop selection procedure that offers a scalable method for increasing the transition fault coverage. Experimental results on industrial circuits are included

A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis.

We describe a procedure for forming n-detection test sets for n > 1 without applying a test generation procedure to target faults. The proposed procedure accepts a one-detection test set. It extracts test cubes for target faults from the one-detection test set. It then merges the cubes in different ways to obtain an n-detection test set. We demonstrate that the resulting test set is as effective as an n-detection test set generated by a deterministic test generation procedure in detecting untargeted faults. Merging of cubes does not require test generation or fault simulation. Fault simulation is required for extracting test cubes for target faults

The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test application time of a test set for a scan circuit is determined by the sum of the number of scan shifts required for applying the test set and the number of primary input vectors in the test set. Compaction procedures that view a full-scan circuit as a combinational circuit reduce the number of test vectors, where a test vector consists of a scan vector and a primary input vector. However, this is not sufficient, and effective procedures must reduce the number of scan operations further than the combinational circuit view allows. Procedures to reduce the test application time by dropping scan operations and applying several primary input vectors between scan operations have been proposed earlier. The compaction procedures proposed in this work reduce the test application time further by using limited scan operations. Under a limited scan operation, the number of shifts is smaller than the length of a scan chain. Scan operations that cannot be dropped are replaced by limited scan operations under the proposed procedures.

Design for testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the circuit outputs. This should be done without masking the detection of other faults of the original circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.

It is shown that fault equivalence and fault dominance relations defined based on the sets of completely specified test vectors that detect each fault may not hold when incompletely specified test vectors are used together with three-value simulation. Experimental results are presented to demonstrate the extent of this phenomenon. Its effects are discussed in general and in the context of a specific application. Possible solutions are also discussed.

This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.

Current designs may contain several identical copies of the same circuit (or functional unit). Such circuits can be tested by comparing the output vectors they produce under identical input vectors. This alleviates the need to observe the output response, and facilitates online testing. We show that testing of identical circuits by output comparison can be done effectively even when the input vectors applied to the circuits are not identical. This allows concurrent online testing even when the circuits are not driven from the same source during functional operation. We investigate several issues related to this observation. We investigate the use of both structural and functional analysis to identify situations where nonidentical input vectors can be used for fault detection based on output comparison. We also consider the use of observation points to improve the fault coverage. We present experimental results to support the discussion and the use of nonidentical input vectors for concurrent online testing of identical circuits.

We propose a design-for-testability technique for synchronous sequential circuits called autoscan. Autoscan uses scan chains similar to conventional scan. However, it gives up the external scan inputs and outputs in order to eliminate the test data volume associated with them. Scan operations under autoscan improve the circuit testability by allowing the circuit state to be modified through shifting. Due to the removal of the scan inputs and outputs, synthesis of scan chains under autoscan does not have to satisfy all the constraints imposed on conventional scan chains. We describe a synthesis procedure for autoscan chains, and demonstrate that autoscan allows us to detect almost all the faults that are detectable using conventional scan. We use random sequences in order to show that sequential test generation is not necessary under autoscan. We also describe a test generation procedure, and discuss the effect of autoscan on fault diagnosis.

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

We study properties of a subset of single stuck-at faults defined based on dominance relations and referred to as maximally dominating faults. These faults were shown to be effective in n-detection test generation and in diagnosis. The properties described here can be useful in additional applications. We suggest two such applications. The first is weighted random pattern generation using three weights, 0, 0.5 and 1. The second application is static test compaction that drops unnecessary tests from a given test set in order to reduce its size.

Test sets for path delay faults in circuits with large numbers of paths are typically generated for faults associated with the longest circuit paths. Such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures. A dynamic test enrichment procedure proposed earlier increases the number of faults associated with the next-to-longest paths that are detected by a test set in order to improve its quality without increasing its size. The earlier procedure is referred to as dynamic since the decision as to which faults associated with next-to-longest paths will be detected is done during test generation. In this work, we describe a postprocessing procedure for test enrichment that accepts a given test set. By processing the tests in reverse order, the proposed procedure increases the number of detected faults associated with next-to-longest paths without increasing the number of tests. We demonstrate the effectiveness of the proposed reverse order test enrichment procedure when applied following, and instead of dynamic test enrichment.

Detecting single stuck-at faults more than once has been shown to be an effective way to achieve high defect coverage. Recently it was observed that the number of tests required to achieve n-detection of single-stuck-at faults using pseudo-random sources may increase as n.logn with increasing values of n. In this paper, we investigate weighted pseudo-random BIST for n-detection of single stuck-at faults. We propose a hardware efficient weighted pseudo-random test pattern generator. Experimental results show that the proposed test pattern generator achieves n-detection of single stuck-at faults with test set sizes growing linearly with n. The hardware overhead grows modestly with n.

This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.

We describe a new approach to fault collapsing that extends fault collapsing based on fault equivalence and fault dominance. The new approach is based on a metric called level of similarity between faults. Informally, a fault f/sub j/ is said to be similar to a fault f/sub i/ with a level of similarity SL/sub i,j/ /spl les/ 1 if a fraction SL/sub i,j/ of the tests for f/sub i/ also detect f/sub j/. If SL/sub i,j/ is high enough, one may exclude f/sub j/ from the set of target faults and rely on the test for f/sub i/ (and tests for other faults) to detect f/sub j/. We describe a procedure for fault collapsing based on the level of similarity, and study its effectiveness experimentally.

We define the concepts of z-sets and z-detections for combinational circuits (or the combinational logic of scan circuits). Based on these concepts we define structural characteristics and characteristics based on fault simulation. We show that these characteristics determine the numbers of fault pairs that are guaranteed to be distinguished by a given fault detection test set. These fault pairs do not need to be considered during diagnostic fault simulation or test generation. We demonstrate that benchmark circuits as well as industrial circuits have these characteristics to a larger extent than may be expected. As a result, only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. In addition, these fault pairs can be identified efficiently.

When test vectors for a full scan logic circuit include unspecified values, conventional 3-valued fault simulation may not compute the exact fault coverage for single stuck-at faults. This paper first addresses the incompleteness of logic/fault simulation based on the conventional 3-valued logic. Then we propose an enhanced method of logic/fault simulation to compute more accurate fault coverage using implicit logic values. The proposed method employs indirect implications. We also propose a new learning criterion to identify indirect implications that are not identified by earlier static learning procedure. Since some indirect implications derived from a fault-free circuit become invalid in the presence of a fault, we use a sufficient condition for an indirect implication to remain valid for the faulty circuit, and give an efficient procedure for more accurate fault simulation. Experimental results demonstrate that the proposed method reduces the number of unknown values at the circuit outputs in logic simulation, and hence it discovers several detected faults that are not declared as detected by the conventional fault simulation.

We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive test compaction compared to other approaches. We demonstrate that, unlike other approaches that provide high levels of test compaction for partial scan circuits, this approach does not increase the number of undetectable faults. We also discuss the monotonicity of the number of undetectable faults with increased levels of scan.

We address the problem of design-for-diagnosability, i.e., improving the accuracy of fault diagnosis or reducing its complexity through the insertion of observation points. To perform design-for-diagnosability efficiently, we use a procedure developed earlier for computing the number of fault pairs, N/sub P/, that are not guaranteed to be distinguished by a given test set. By using the concept of z -detection, N/sub P/ can be computed efficiently without enumerating fault pairs and without performing non-fault dropping fault simulation. We study the possibility of increasing the diagnosability of a circuit by inserting observation points so as to reduce N/sub P/. Our results include the following. (1) We find experimentally the number of observation points that need to be inserted in order to achieve a close-to-minimum value for N/sub P/. (2) We describe an efficient procedure for inserting a given number of observation points so as to reduce N/sub P/. We present experimental results for benchmark circuits to demonstrate the accuracy of using N/sub P/ to guide a design-for-diagnosability process.

A memory BIST enhancement, ESP short for exercising system paths, is described that allows the efficiency and functional capabilities of standard approaches while addressing two important problems. Conventional Memory BIST techniques require MUXes at the inputs of the memory that allow for the inputs to be driven either by system signals or by test signals. These MUXes add delays, in the system path going to the memory, which often has critical timing. ESP eliminates such delays by implementing the MUXing function 'before' scan cells. ESP also uses scan cells to capture the memory output for feeding back to the BIST controller. This output may have traveled through some logic before getting to the recording scan cells. By including the delays of the system input and output paths, ESP allows for verifying that the memory will work correctly as part of the system rather than just as an isolated unit. Using ESP, a memory BIST can catch transition and delay faults that are impractical, or even impossible, to catch otherwise. Therefore, ESP can be useful for all memories but may be crucial for the memories which cannot tolerate the addition of the MUX delay to functional paths.

A circuit may produce unknown output values during simulation of a test set, e.g., due to an unknown initial state or due to the existence of tristate elements. Unknown output values in the output response of a circuit make it impossible to determine a single unique signature for the fault-free circuit when built-in self-test is used for testing the circuit. We consider the problem of synthesizing a logic block that replaces unknown output values in the output response of a circuit with a known constant. The logic block is constructed from building blocks called comparison units. The synthesis procedure ensures that the built-in self-test scheme will be able to detect all the faults detectable by the test set applied to the circuit while allowing a single unique signature to be computed. Two variations of the synthesis procedure are considered, a two-dimensional version suitable for synchronous sequential circuits without scan and for scan circuits with multiple scan chains and a one-dimensional version suitable for scan circuits with a single scan chain.

When storage requirements or limits on test application time do not allow a complete (compact) test set to be used for a circuit, a partial test set that detects as many faults as possible is required. Motivated by this application, we address the following problem. Given a test sequence T of length L for a synchronous sequential circuit and a length M

N-detection test sets are useful in improving the coverage of unmodeled faults. We introduce a measure of quality that allows us to compare two test sets in terms of their ability to detect unmodeled faults based on the concept of n-detections. Using this measure, we describe a procedure for ordering an n-detection test set for stuck-at faults such that the quality of a test set comprised of the first K tests of the test set is as high as possible. This is useful when only K tests of the test set can be accommodated in the tester memory or to help ensure that unmodeled faults are detected as early as possible during the test application process. We present experimental results demonstrating that the proposed ordering yields test sets with increased coverage of unmodeled faults.

A new class of static compaction procedures is described that generate test sets with reduced test application times for scan circuits. The proposed class of procedures combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with a short primary input sequence included in every test and one that tends to generate small numbers of tests with a long, primary input sequence included in one of the tests. A procedure of the proposed class starts from an initial test set that has a large number of tests and long primary input sequences and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time. Several ways of computing the primary input sequences for the initial test set are considered. The most compact test sets are obtained when a test sequence for the nonscan circuit is available and this sequence is used as part of every test in the initial test set. However, it is shown that high levels of compaction can also be achieved without the overhead of test generation for the nonscan circuit. Specifically, we show that the industry practice of holding a primary input vector constant between scan operations can be accommodated. We estimate the ability of the procedure to achieve optimum test sets by computing a lower bound on the number of tests and demonstrating that the procedure achieves or approaches this lower bound.

The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a synchronous sequential circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted from the test sequence initially, to start the restoration process. We also propose a specific procedure for the initial omission process. Experimental results for a variety of circuits and test sequences demonstrate that this procedure has a significant effect on the compacted test sequence length. Intuitively, the new procedure postpones the point at which the compaction procedure saturates, thus allowing smaller test lengths to be obtained before saturation is reached. The importance of continuing to explore this problem is related to the fact that static compaction procedures for synchronous sequential circuits are important for scan circuits as well.

We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults for test generation efficiently, when it is impractical to target all the bridging faults (or all the realistic bridging faults). We demonstrate that the faults selected based on the proposed characterization are indeed hard-to-detect by performing the following experiments. 1) We show that the fault coverage of a given test set, with respect to the selected subset of bridging faults, is lower and more sensitive to the test set than the fault coverage obtained with respect to a random subset of bridging faults of the same size, with respect to the complete set of bridging faults, and when possible, with respect to a subset of realistic bridging faults of the same size. 2) We demonstrate that a test set generated for the selected subset of bridging faults detects other bridging faults more effectively than when a test set is derived for a randomly selected subset of bridging faults of the same size. We also describe an efficient procedure for selecting hard-to-detect bridging faults according to the proposed characterization. This procedure avoids enumeration of all the faults in order to select the hard-to-detect ones. This is important for large circuits where even enumeration of all the bridging faults may not be feasible.

Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional test sequence can still be applied at-speed; however, a higher stuck-at fault coverage is achieved.

Critical paths are analyzed in a CAM and minimum test patterns are proposed to detect delay faults in a CAM. The test patterns derived are shown to be covered by the basic algorithm proposed earlier in (G. Giles et al, Proc. Int. Test Conf. p.471-474, 1985).

We propose a new DFT approach for path delay faults in interconnected circuits. The proposed approach places multiplexers on the interface between two circuits in order to create new testable paths through the interconnection. The new testable paths allow us to increase the number of paths tested in each circuit. This approach does not require interconnected circuits to be isolated by test wrappers.

We explore an approach to input test data compression called realignment. Realignment changes a test sequence T consisting of n-bit vectors into a sequence T(m) consisting of m-bit vectors for m /spl ges/ n. It then compresses T(m) instead of T to achieve larger levels of compression for T(m) than for T. By controlling m, realignment provides a range of possible solutions that differ in the data volume reduction and the amount of memory required between the decompressor and the circuit. The memory is required in order to translate m-bit vectors produced by the decompressor into n-bit vectors required by the circuit. We present experimental results to demonstrate this tradeoff for synchronous sequential circuits.

Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.

We consider the relationship between test data compression and the ability to perform comprehensive testing of a circuit under an n-detection test set. The size of an n-detection test set grows approximately linearly with n. Therefore, one may expect a decompresser that can decompress a compressed n-detection test set to be larger than a decompresser required for a compact conventional test set. The results presented in this work demonstrate that it is possible to use a decompresser designed based on a compact one-detection test set in order to apply an n-detection test set. Thus, the design of the decompresser does not have to be changed as n is increased. We describe a procedure that generates an n-detection test set to achieve this result.

Due to their simplicity transition faults are often used as targets for test generation to detect delay defects. However, one concern documented in the literature is that of overtesting. One of the reasons for overtesting is that DFT approaches, such as scan, change sequentially untestable faults into testable faults. One approach to reducing overtesting is to identify sequentially untestable and redundant faults and not target them during test generation for the circuit with scan. Another application of identifying untestable transition faults is its use in logic optimization. We investigate efficient procedures to identify untestable and redundant transition faults in nonscan synchronous sequential circuits. Experimental results for ISCAS-89 benchmark circuits are presented.

Current design methodologies and methodologies for reducing test data volume and test application time for full-scan circuits allow testing of multiple circuits (or subcircuits of the same circuit) simultaneously using the same test data. We describe a static compaction procedure that accepts test sets generated independently for multiple full-scan circuits, and produces a compact test set that detects all the faults detected by the individual test sets. The resulting test set can be used for testing the circuits simultaneously using the same test data. This procedure provides an alternative to test generation procedures that perform test generation for complex circuits made up of multiple circuits. Such procedures also reduce the amount of test data and test application time required for testing all the circuits by testing them simultaneously using the same test data. However, they require consideration of a more complex circuit.

Recently, Markov sources were shown to achieve 100% fault efficiency at low area overhead when used as pseudo-random pattern generators in scan BIST. In this paper we give a new method of designing Markov sources. The new design attempts to match probabilities of 1 to 0 and 0 to 1 transitions in consecutive bits of a set of test vectors, taking into account that the transition probabilities may be different for different bit positions. Experimental results show that the proposed method considerably reduces the hardware overhead and test lengths required to achieve 100% fault coverage.

Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain diagnosis methods that targeted permanent faults only, the proposed method targets both permanent faults and intermittent faults. Three ideas are presented in this paper. First an enhanced upper bound on the location of candidate faulty scan cells is obtained. Second a new method to determine a lower bound is proposed. Finally a statistical diagnosis algorithm is proposed to calculate the probabilities of the bounded set of candidate faulty scan cells. The proposed algorithm is shown to be efficient and effective for large industrial designs with multiple faulty scan chains. 1

This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. A convolutional compactor can be easily configured into a MISR that preserves most of these properties. Experimental results demonstrate the efficiency of compaction for several industrial circuits.

We propose a new method for reducing test data volume and test application time in scan designs with multiple scan chains. The method uses a reconfigurable switch to apply tests from a limited number of external inputs to a large number of internal scan chains. The reconfigurable switch allows different subsets of scan chains to be connected to the same external input at different times, thus allowing varied tests to be applied to the circuit. 1.

This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detection and correction codes. The technique, called i-Compact, uses Saluja-Karpovsky Space Compactors, but permits detection and location of errors in the presence of unknown logic (X) values with help from the ATE. The advantages of i-Compact are: 1. Small number of output pins front the compactors for a required error detection capability; 2. Small tester memory for storing expected responses; 3. Flexibility of choosing several different combinations of number of X values and number of bit errors for error detection without altering the hardware compactor; 4. Same hardware capable of identifying the line that produced an error in presence of unknowns; 5. Use of non-proprietary codes found in the literature of 1950s; and 6. Independent of the circuit and the test generator.

When storage requirements or limits on test application time do not allow a complete (compact) test set to be used for a circuit, a partial test set that detects as many faults as possible is required. Motivated by this application, we address the following problem. Given a test sequence T of length L for a synchronous sequential circuit and a length M

We consider the problem of built-in test pattern generation for non-isolated scanned cores. When two such cores are interconnected, a block of combinational logic that spans both cores may be created. Our goal is to provide a solution for built-in testing of logic that spans multiple cores. Starting from a given test-pattern generator (TPG), we propose a design-for-testability approach to improve the fault coverage achieved by the TPG. This approach is based on designing the interfaces between pairs of cores such that they support the testing of both cores. The proposed approach does not require any modifications to the cores themselves. In a vast majority of the benchmark circuits considered, the proposed approach results in 100% fault coverage.

We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.

We present a new static test sequence compaction procedure called reverse-order-restoration (ROR) for synchronous sequential circuits. It improves the efficiency of the basic vector restoration-based compaction procedure by reversing the order of the vectors in the original test sequence. This reduces the number of faults to be resimulated after every restoration step. We extend the ROR procedure to a class of radix reverse order vector restoration procedures. These procedures dynamically increase the number of vectors to be restored in each step and, thus, speed up the vector restoration process. We also investigate techniques to improve the compaction levels achieved by the ROR-based compaction procedure. By combining reverse order vector restoration and vector omission, higher compaction levels are achieved. Experimental results on test sequences generated by several test generators show the effectiveness of the proposed techniques.

We describe a property-based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences that achieve high fault coverages at low computational complexity. These include the use of static test compaction, input vector holding with optimal numbers of hold cycles, input vector perturbation, and identification of subsequences that are useful in extending the test sequence. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures.

Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. It is shown that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. A test enrichment procedure is proposed that increases significantly the number of faults associated with the next-to-longest paths that are detected by a test set without increasing its size. This is achieved by targeting both types of faults, but ensuring that the test generation procedure would detect the faults associated with the longest paths, while allowing the procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. The proposed procedure thus improves the quality of the test set without increasing its size. The test enrichment procedure is built on top of a new and effective dynamic test compaction procedure in order to demonstrate that test enrichment is effective even for compact test sets.

We provide a definition of undetectable faults in partial-scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.

We use the fact that outputs of a large circuit depend on proper subsets of the circuit inputs to provide test data compression on the input side. The compressed input test data consists of patterns of length equal to the maximum number of inputs on which an output depends. This is typically smaller than the number of circuit inputs. A distribution block expands every input pattern into several test patterns for the circuit, one test pattern for every input pattern and input subset. We present experimental results to show that significant compression can be achieved by the proposed approach while maintaining complete fault coverage.

We describe a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select, and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits. The resulting test sequences can be applied using conventional test application schemes that support limited scan operations.

We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming a combinational decompressor circuit.

In this paper, a method is presented to schedule tests for core-based SoCs to achieve optimal test completion time for the SoC design by simultaneously determining optimal core clustering, core cluster wrapper width, and pin mapping. For the first time the above mentioned techniques are applied concurrently to solve the SoC test scheduling problem. A heuristic algorithm implementing these techniques to determine an optimal solution is proposed.

This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.

Chronological order enumeration is a static compaction procedure for synchronous sequential circuits that to-date produces the shortest test sequences overall for benchmark circuits. The chronological order enumeration procedure was not meant to compete in computational complexity with the highly-efficient restoration based compaction procedure. Rather, it was developed so as to provide a more aggressive target for static and dynamic test compaction procedures. Nevertheless, we describe in this work several algorithmic methods to improve the efficiency of compaction based on chronological order enumeration. These improvements reduce the run time of chronological order enumeration significantly using the same basic implementation. With these improvements, chronological order enumeration is shown to be faster and more effective than restoration based compaction for sequences produced by an ATPG that already uses restoration based compaction as part of the test generation process. For uncompacted sequences, restoration based compaction followed by the improved chronological order enumeration process is shown to be an effective combination.

We describe a built-in test pattern generation method for delay faults in scan circuits based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the stored sets. The sizes of the sets are minimized before they are stored on-chip in order to reduce the storage requirements and the test application time. The delay fault model we consider is the transition fault model.

In this work we propose a path-oriented test generation procedure called POTENT to generate high quality tests for transition faults. Both weak non-robust and strong non-robust tests can be generated by POTENT. We classify, transition fault tests into six types according to their activation and propagation methods. The basic idea of POTENT is to test a transition fault along a longest testable path passing through the fault site. For transition faults that are activated or propagated through multipaths, heuristics are proposed to maximize the propagation delay of the target fault. We also propose an efficient method to evaluate the quality of a given transition fault test set. Experimental results show that POTENT generates higher quality transition fault test sets than the conventional test generation method.

A circuit may produce unknown output values during simulation of an input sequence due to an unknown initial state or due to the existence of tri-state elements. For circuits tested using BIST, unknown output values make it impossible to determine a single unique signature for the fault free circuit. To accommodate unknown output values in a BIST scheme, we describe a procedure for synthesizing a minimal logic block that replaces unknown output values by a known constant. The proposed procedure ensures that the BIST scheme will be able to detect all the faults detectable by the input sequence applied to the circuit while allowing a single unique signature to be obtained.

Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. We propose a test enrichment procedure that increases significantly the number of faults associated with the next-to-longest paths that are detected by a (compact) test set. This is achieved by allowing the underlying test generation procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. Faults associated with next.-to-longest paths are detected without increasing the number of tests beyond that required to detect the faults associated with the longest paths. The proposed procedure thus improves the quality of the test set without increasing its size.

When a design is manufactured for the first time, it may suffer from timing-related errors that result from inaccuracies in the timing analysi tool used during the design process. Such errors will appear as delay faults in all (or many) of the manufactured chips. In addition, variations that occur during the manufacturing process may cause delay defects that vary across chips. It is necessary to diagnose and correct failures of the first type (in the presence of failures of the second. type) before the chip can be manufactured again. This may have to be repeated until design errors are eliminated. Experiments that enable one to find common fault responses of faulty circuits are described.

We provide a definition of undetectable faults in partial scan cir-cuits under a test application scheme where a test consists of pri-mary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetect-able under this test application scheme. We present experimen-tal results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults. 1.

This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic decision ordering, conflict driven recursive learning and conflict learning. An important feature shared by all these techniques is that they are triggered by the occurrence of a conflict in the generation of tests. Hence, they are not active all the time nor for all the faults. This feature allows the ATPG system that uses these techniques to resolve hard-to-resolve faults with far fewer backtracks and leaves the system as efficient as before in the absence of conflicts. We have incorporated these techniques into a commercial D-algorithm based ATPG tool. The experimental results on full scan versions of ITC'99 benchmark circuits demonstrate an improvement of the ATPG system both in the number of aborted faults and in test generation time.

Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts.

Given a test set for stuck-at faults, a primary input value may be changed to the opposite logic value without losing fault coverage. One can regard such a value as a don't-care (X). The don't care values can be filled appropriately to achieve test compaction, test data compression, or power reduction during testing. However, these uses are better served if the don't cares can be placed in desired/specific bit positions of the test patterns. In this paper, we present a method for maximally fixing Xs on specific bits of given test vectors. Experimental results on ISCAS benchmark circuits show how the proposed method can increase the number of Xs on specific bits compared with an earlier proposed method.

The use of multiple scan chains for a scan design reduces the test application time by reducing the number of clock cycles required for a scan-in/scan-out operation. In this work, we show that the use of multiple scan chains also increases the fault coverage achievable for delay faults, requiring two-pattern tests, under the scan-shift test application scheme. Under this scheme, the first pattern of a two-pattern test is scanned in, and the second pattern is obtained by shifting the scan chain once more. We also demonstrate that the specific way in which scan flip-flops are partitioned into scan chains affects the delay fault coverage. This is true even if the order of the flip-flops in the scan chains remains the same. To demonstrate this point, we describe a procedure that partitions scan flip-flops into scan chains so as to maximize the coverage of transition faults.

Proposes a new pseudo-random pattern generator for scan circuits. The proposed generator uses Markov sources to capture spatial correlations between consecutive bits inside a scan chain as defined by weight sets generated using a weighted random pattern testing method. The weight set generation is based on the analysis of deterministic test sets. The BIST scheme that uses the proposed pattern generator iteratively modifies the generator behavior to obtain a full fault coverage. Experiments conducted on large benchmark circuits demonstrate that the proposed BIST methodology can achieve full fault coverage with a small number of tests and a small hardware overhead.

This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.

We consider the problem of testing of interconnect open defects in combinational circuits with large fanout nodes. We propose a gate level fault model for interconnect opens. The number of interconnect open faults using the proposed model can be very large, being exponential in the fanout size. We describe methods to effectively consider the very large numbers of open faults. These methods include techniques for implicit consideration of open faults, and the use of information about fanout branches driving each primary output to reduce the list of faults. We present experimental results to demonstrate that fault simulation and test generation for the modeled open faults can be carried out efficiently using these techniques.

We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming a combinational decompressor circuit.

We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T/sub 0/ and ensuring that every fault detected by T/sub 0/ is detected by the expanded version of at least one loaded sequence. Specifically, each input sequence S is constructed based on a different fault f and is extracted from T/sub 0/ around a time unit where f is detected by T/sub 0/. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored on-chip at any given time is, on the average, 11 percent of the length of T/sub 0/ and that the total length of all the loaded sequences is, on the average, 48 percent of the length of T/sub 0/. These results are obtained by extracting each sequence S around the first detection time of a target fault f. These results are further improved by considering several time units for every target fault f and selecting the shortest possible sequence based on f.

We describe a method to improve the levels of compaction achievable by static compaction procedures based on vector omission. Such procedures are used to reduce the lengths of test sequences for synchronous sequential circuits without reducing the fault coverage. The proposed procedure enumerates, in increasing chronological order, test sequences consisting of subsets of the vectors included in a given test sequence that needs to be compacted. The unique feature of this approach is that test vectors omitted from the test sequence at an earlier iteration can be reintroduced at a later iteration. This results in a less greedy procedure and helps reduce the compacted test sequence length beyond the length that can be achieved if vectors are omitted permanently as in earlier procedures.

We describe a built-in test pattern generation method for scan circuits. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The sets are stored on-chip and the on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time. We describe two schemes for reducing the set sizes, one where each set stores the values of one subset of primary inputs or state variables and one where a single set is used to store values of different subsets of state variables. We demonstrate the effectiveness of the proposed method as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults. In the latter case, the proposed method is applied to detect the hard-to-detect faults that remain undetected.

Scan circuits are considered under a test application scheme where a test consists of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. The first property-based (simulation-based) test generation procedure under this test application scheme is described. The proposed procedure constructs tests that traverse as many pairs of fault-free/faulty states as possible. Additional techniques are incorporated into this basic procedure to enhance its effectiveness. Also considered for the first time is the set of detectable faults under this test application scheme. It is shown that it is a subset of the set of detectable faults obtained under the test application scheme where scan is applied with every primary input vector. It is also shown that the set of detectable faults depends strongly on the set of scanned flip-flops even when the percentage of scanned flip-flops is very high. This dependence at high levels of scan is significantly weaker when scan is applied with every primary input vector.

Proposes a procedure for generating compact test sets with enhanced at-speed testing capabilities for scan circuits. Compaction refers here to a reduction in the test application time, while at-speed testing refers to the application of primary input sequences that contribute to the detection. of delay defects. The proposed procedure generates an initial test set that has a low test application time and consists of long sequences of primary input vectors applied consecutively. To construct this test set, the proposed procedure transforms a test sequence T/sub o/ for the nonscan circuit into a scan-based test by selecting an appropriate scan-in state and removing primary input vectors from T/sub o/ if they do not contribute to the fault coverage. If T/sub o/ contains long transfer sequences, several scan-based tests with long primary input sequences may be obtained by replacing transfer sequences in T/sub o/ with scan operations. This helps reduce the test application time further. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences.

An n-detection fault simulation process called n-pass n-detection fault simulation is described. n-pass n-detection fault simulation can be implemented such that it has the same computational complexity (and run time) as the conventional n-detection fault simulation process; however, it is more effective for applications where it is necessary to identify tests that detect large numbers of faults. One such application considered in this work is that of ordering a given test set so as to steepen its fault coverage curve. Experimental results are presented to demonstrate that improved test ordering is obtained by using the proposed n-pass n-detection fault simulation process using approximately the same run time as when conventional n-detection fault simulation is used. n-pass n-detection fault simulation is also effective in cases where the value of n is required to change dynamically during the fault simulation process. This is useful in order to accommodate a limit on the run time of n-detection fault simulation, or when it is not possible to specify a value for n in advance.

We propose several techniques to improve a simulation based test pattern generation procedure for sequential circuits. The effectiveness of the proposed techniques is demonstrated through experimental results on a large set of benchmark circuits.

A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results.

A test for a scan design typically starts with a scan-in operation followed by one or more primary input vectors, and ends with a scan-out operation. The length of a test is defined to be the number of primary input vectors included in it. We describe a procedure for reducing the number of different test lengths in a test set TS for a scan circuit. Reducing the number of different lengths reduces the complexity of applying TS to the circuit. The procedure we describe is a postprocessing procedure applied after test generation, and it does not require any modifications to the test generation procedure. A test length L/sub i/ is eliminated from TS by replacing all the tests of length L/sub i/ by tests of length L/sub j/ that exists in TS. In the first phase of the procedure, L/sub j/L/sub i/. We present experimental results to demonstrate that significant reductions in the number of test lengths are possible.

Discusses an improved procedure named forward-looking fault simulation. The term forward-looking refers to the fact that certain tests are dropped because they are not necessary for detecting faults that will be detected later in the simulation process. The authors discuss an efficient implementation of forward-looking fault simulation in an industrial environment. They concentrate on reverse order fault simulation. Parallel pattern single fault propagation (PPSFP) simulation is used throughout the implementation of the forward-looking reverse order fault simulation process, since PPSFP is known to result in fast fault simulation for industrial circuits.

Several methods to reduce the run time and memory requirements of a procedure used to efficiently identify untestable path delay faults are proposed in this work. Based on the correlation between the conditions required for sensitizing subpaths in the fan-out-free regions of a circuit, equivalence relations between the subpaths are defined. Equivalence relations are used to reduce the number of subpaths considered in the identification of untestable paths. Dynamic pruning of the potential search space for identifying pairs of subpaths that cannot be sensitized together is used to achieve additional speedup. Results on benchmark circuits show the effectiveness of the proposed methods.

We propose a new approach to the generation of compact test sets for scan circuits. Compaction refers here to a reduction in the test application time. The proposed procedure generates an initial test set that is likely to have a low test application time. It then applies an existing static compaction procedure to this initial test set to further compact it. As a by-product, the proposed procedure also results in long primary input sequences, which are applied at-speed. This contributes to the detection of delay defects. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences. 1.

We describe a reordering procedure that changes the order of test vectors in a test sequence for a synchronous sequential circuit without reducing the fault coverage. We use this procedure to investigate the effects of reordering on the ability to compact the test sequence. Reordering is shown to have two effects on compaction. (1) The reordering process itself allows us to reduce the test sequence length. (2) Reordering can improve the effectiveness of an existing static compaction procedure. Reordering also provides an insight into the detection by test generation procedures of faults that are detected by relatively long subsequences.

The number of times a fault f in a combinational circuit is detected by a given test set T was shown earlier to affect the defect coverage of the test set. The earlier definition counted each test in T, that detects f, as a distinct detection of f. This definition counts two tests as distinct detections even if they differ only in the values of inputs that do not affect the activation or propagation of the fault. In this work, we introduce a stricter definition that requires that two counted tests would be different in the way they activate and/or propagate the fault. We describe procedures for constructing test sets based on the stricter definition, and compare them to test sets for the earlier, less strict definition. The results show a simple criterion to decide when it may be necessary to combine the two definitions in order to obtain a high quality test set.

Article Share on ITEM: an iterative improvement test generation procedure for synchronous sequential circuits Authors: Irith Pomeranz School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN School of Electrical & Computer Eng., Purdue University, W. Lafayette, INView Profile , Sudhakar M. Reddy Electrical & Computer Eng. Dept., University of Iowa, Iowa City, IA Electrical & Computer Eng. Dept., University of Iowa, Iowa City, IAView Profile Authors Info & Claims GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSIMarch 2001 Pages 13–18https://doi.org/10.1145/368122.368147Published:01 March 2001Publication History 0citation146DownloadsMetricsTotal Citations0Total Downloads146Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this work, a new and effective procedure, called REDI, to efficiently identify redundant single stuck-at faults in combinational logic circuits is proposed. The method is fault oriented and uses sensitizability of partial paths to determine redundant faults. It uses only implications and hence may not determine all the redundant faults of a circuit. However, experimental results presented on benchmark circuits show that the procedure identifies nearly all the redundant faults in most of the benchmark circuits. The key features of REDI that make it efficient are: partial path sensitization, blockage learning, dynamic branch ordering and fault grouping. Experimental results on benchmark circuits demonstrate the efficiency of the proposed procedure in identifying redundant faults in combinational logic circuits.

We propose a dynamic compaction procedure for non-scan synchronous sequential circuits. The procedure combines four compaction techniques. (1) Dynamic ordering of test subsequences generated for yet-undetected faults. (2) Local static compaction is performed every time a new subsequence is added to the test sequence. (3) Short test subsequences are discarded to prevent them from increasing the test length unnecessarily. (4) The test generation process is repeated with a fault order dynamically determined based on the existing test sequence. With these techniques, dynamic compaction yields test lengths that are shorter than all but the most aggressive and computationally expensive static compaction procedure.

We describe a built-in test pattern generation method for synchronous sequential circuits based on partitioning and storage of test subsequences. Under this method, a set of subsequences /spl Psi/ is stored on-chip. On-chip test sequences are obtained by implementing a subset of the Cartesian product /spl Psi/x/spl Psi/x/spl middot//spl middot//spl middot/x/spl Psi/. The set /spl Psi/ is obtained by iterative partitioning of a precomputed test sequence T. The number of subsequences in /spl Psi/ is minimized at every iteration in order to reduce the final storage requirements, the test application time, and the computational effort required to produce the final set /spl Psi/.

This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

A static compaction procedure to reduce test set size for scan designs and a procedure to order test patterns in order to steepen the fault coverage curve are presented. The computational effort for both procedures is linearly proportional to the computational effort required for standard fault simulation with fault dropping. Experimental results on large industrial circuits demonstrate both the efficiency and effectiveness of the proposed procedures.

We consider designs where the same processing units (or circuits) appear multiple times. This is prevalent in current microprocessors and in reliable systems. Fault detection in such designs can be done by comparing output responses of identical circuits when identical input sequences are applied to them. The main advantage of this method over other methods of fault detection is that output responses do not need to be precomputed, and therefore, arbitrary, unknown input sequences can be used for testing. We propose a design-for-testability method for such designs that applies the same modifications to the states of the circuits being compared. If the circuits are fault free, they continue to produce identical output sequences after their states are modified in the same way. However, if one of the circuits is faulty, state modification can help increase the distance between the circuit states and eventually contribute to the detection of the fault. The proposed state modifications can be implemented by using hardware that supports assignment statements in the instruction sets of microprocessors. Depending on the state modification used, the proposed method may be applicable to concurrent, on-line or off-line testing. We present experimental results to support the effectiveness of the proposed method.

Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional sequence is still applied at-speed: however, a higher stuck-at fault coverage is achieved.

The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. We propose a method for obtaining a more gradual increase in the sizes of n detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault dominance relations to identify a small subset of faults whose numbers of detections are likely to have a high impact on the defect coverage of the test set.

Static-test compaction procedures for synchronous sequential circuits may saturate and be unable to further reduce the test-sequence length before the test length reaches its minimum value, resulting in test sequences that may be longer than necessary. We propose a method to take a static-compaction procedure out of saturation and allow it to continue reducing the test-sequence length. The proposed method is based on the replacement of test vectors in the test sequence every time the compaction procedure reaches saturation. Test-vector replacement is done such that the fault coverage of the sequence is maintained. Experimental results using an effective static-compaction procedure demonstrate that reductions in test length can be obtained by the proposed vector replacement method.

We propose a method of modeling pattern dependence as part of the existing delay fault models without incurring the complexity of considering physical effects that cause pattern dependence. We apply the method to transition faults. We define the conditions under which two pattern-dependent transition faults can be said to be distinguished by a given test set. We provide experimental results to demonstrate the diagnostic resolutions obtained under the proposed model. We also present conditions for identifying pairs of indistinguishable pattern-dependent transition faults and propose a procedure for generating diagnostic tests for distinguishable pattern-dependent transition faults.

Fault simulation of a test set in an order different from the order of generation (e.g., reverse- or random-order fault simulation) is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size. We propose an improvement to this type of fault simulation process that makes it even more effective in reducing the test-set size. The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later, hence the name of the improved procedure: forward-looking fault simulation. We present experimental results to demonstrate the effectiveness of the proposed improvement.

We propose an approach for built-in fault diagnosis of synchronous sequential circuits. The proposed approach distinguishes faults based on their detection by modified versions of a fault detection test sequence generated on-chip. The modified versions are defined by one-bit-wide auxiliary sequences, also generated on-chip. The auxiliary sequences indicate which test vectors of the fault detection test sequence need to be applied to the circuit. Experimental results presented indicate that the proposed on-chip test generation method is effective in achieving high levels of diagnostic-resolution.

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged.

Logic circuits may have large numbers of untestable paths. Therefore, it is important for path delay fault testing to identify untestable paths prior to test generation. An earlier method, called partial path sensitization, was able to identify large numbers of untestable path delay faults by analyzing pairs of subpaths. We propose to apply this method to the edge graph of the circuit. In the edge graph, an edge corresponds to two consecutive subpaths. Thus, identification of untestable paths is done based on longer subpaths when the edge graph is used than when the original netlist is used. Experimental results presented in this paper show that the proposed method identifies more untestable paths than when the partial path sensitization method is applied to the original netlist.

We investigate the feasibility of performing fault simulation for gate-level circuits using only subcircuits, without considering the complete circuit. This approach can be used to reduce the memory requirements during fault simulation of large circuits. Subcircuits for fault simulation are defined based on subsets of state variables. For every subset of state variables V, only the input cones of next state variables in V are included in the subcircuit being simulated, as well as input cones of primary outputs. We present experimental results to demonstrate the feasibility of fault simulation using subcircuits.

A test set for scan designs may consist of tests where primary input vectors are embedded between a scan-in and a scan-out operation. A static compaction procedure proposed earlier reduces the test application time of such a test set by removing the scan operations at the end of one test and at the beginning of another test, and concatenating the primary input vectors of the two tests. In this work, we investigate a method to increase the number of tests that can be combined in this way, thus further reducing the number of scan operations and the test application time. This is done by inserting one or more primary input vectors between the two tests being combined. The inserted vectors help detect faults that were originally detected due to the scan operations, allowing us to combine tests that cannot be combined otherwise. We present experimental results to demonstrate that improved levels of compaction can be achieved by this method.

We propose a method of modeling pattern-dependence as part of the existing delay fault models without incurring the complexity of considering physical effects that cause pattern-dependence.Using this model, we define the conditions under which two faults can be said to be distinguished by a given test set.We provide experimental results to demonstrate the diagnostic resolutions obtained under the proposed model.

We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficient to achieve complete coverage of stuck-at faults, since these weights are sufficient to reproduce any specific test pattern. For sequential circuits, the weights we use are defined based on subsequences of a deterministic test sequence. Such weights allow us to reproduce parts of the test sequence, and help ensure that complete fault coverage would be obtained by the weighted test sequences generated.

We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage independent of the circuit implementation. The functional fault model we consider consists of single state-transition faults. The test generation procedure we describe uses one of two approaches at any given time in order to minimize the number of tests while minimizing the test application time. (1) It may use scan to set the state of the circuit, and observe fault effects propagated to the next-state variables. (2) It may use transfer sequences to set the circuit state, or unique input-output sequences to propagate fault effects to the primary outputs. We present experimental results to demonstrate the effectiveness of scan-based functional tests.

Test compaction procedures to reduce the test application time for scan designs terminate when they cannot reduce the test application time without reducing the fault coverage. We propose a procedure for placing observation points that allows higher levels of compaction to be achieved without loss of fault coverage. The observation point values are read only at the last time unit of every test, and therefore, they can be scanned-out at the same time as the next-state values.

A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

We describe a simulation-based test generation procedure for scan designs. A test sequence generated by this procedure consists of a sequence of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. We consider the set of faults that can be detected by test sequences of this form, compared to the case where scan is applied with every test vector. The proposed procedure constructs test sequences that traverse as many pairs of fault-free/faulty states as possible, and thus avoids the use of branch-and-bound test generation techniques. Additional techniques are incorporated into this basic procedure to enhance its effectiveness.

Pattern sensitivity was proposed earlier as a property to guide simulation-based test generation for combinational or full-scan circuits. Sensitivity is a binary property, i.e., a pattern is either sensitive or not. In this work, we replace the binary sensitivity property by a property that assumes a range of values, called the level of sensitivity. We demonstrate that patterns with high levels of sensitivity tend to detect more faults than patterns with low levels of sensitivity, and therefore, it is important to consider the level of sensitivity of test patterns during test generation. We also describe a procedure for generating sensitive patterns with high levels of sensitivity.

The test application time of test sets for scan designs can be reduced (without reducing the fault coverage) by removing some scan operations, and increasing the lengths of the primary input sequences applied between scan operations. In this paper, we study the effects of such a compaction procedure on the ability of a test set to detect defects. Defect detection is measured by the number of times the test set detects each stuck-at fault, which was shown to be related to the defect coverage of the test set. We also propose a compaction procedure that affects the numbers of detections of stuck-at faults in a controlled way.

We present a method of path selection and test generation for path delay faults. The proposed method addresses the fact that logic circuits typically have very large numbers of paths, and a large percentage of these paths are typically untestable. The proposed method selects a set of potentially testable long paths by utilizing non-enumerative identification of untestable paths and removing untestable paths from consideration. Test generation is also applied as part of the proposed method. We demonstrate the effectiveness of the method by presenting results for benchmark circuits.

We consider the problem of validating flip-flop data hold time requirements in sequential circuits. The data hold time violations considered are related to the presence of short paths that allow changes in next-state values to occur fast enough so as to cause latching of erroneous next-states. Three fault models are proposed that are related to the presence of short paths in the circuit. Propagation conditions for robust and non-robust tests for short paths are given. A test generation procedure is described for one of the proposed models, and experimental results are provided for benchmark circuits.

We describe three parameters of output sequences of synchronous sequential circuits that can be used for fault diagnosis of such circuits. These parameters can replace the use of complete or partial output sequences for diagnosis. We investigate the diagnostic resolution that can be achieved using these parameters, the sizes of dictionaries that store the parameters, and the ability to diagnose unmodeled faults.

We propose a new approach for implementing static compaction procedures for synchronous sequential circuits. The procedures we consider belong to the class of procedures that generate the compacted test sequence through restoration of segments (or subsequences) of a given test sequence T. Under the proposed approach, each restored segment detects a single target fault chosen from the faults detected by T at one time unit. A novel parallel pattern simulator is developed for this purpose. Experimental results for benchmark circuits are included.

In some applications, it is desirable to find for a circuit a minimal partial description that allows a certain task to be carried out. A partial circuit description allows the task to be carried out more efficiently since fewer decision points exist based on a partial description compared to the full circuit description. We consider this problem with respect to finite state machines and the following tasks. Starting from a functional description of a finite state machine M in the form of a state table ST, we select a minimal subset of state-transitions ST/sub part//spl sub/ST such that every output sequence that can be produced using state-transitions out of ST can also be produced using state-transitions out of ST/sub part/. We also formulate a similar problem related to the propagation of fault effects from the inputs to the outputs of M and describe a procedure for solving this problem. Applications of these tasks include test generation for circuits described as interconnections of finite-state machines. Experimental results presented show that ST/sub part/ contains a small fraction of the state-transitions of ST.

Full scan design renders every combinationally irredundant fault in a synchronous sequential circuit testable. In this paper, we derive a similar result applicable to design-for-testability techniques that only controls the initial state of the circuit in order to improve its testability. Examples of such techniques are parallel load, reset, and scan when it is used only to set the state of the circuit. We show that if the initial state can be set arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault that is not sequentially or combinationally redundant. Thus, the ability to control the state of the circuit is sufficient for detecting every irredundant fault and observability of the circuit state is not necessary for this purpose. When considering scan, this result implies that scan-out can be used to control the test length and test generation time, but it is not necessary for detecting irredundant faults. We also show that, of all the states of the circuit, it is sufficient to consider as possible initial states (or controllable states) only the states extracted from a complete combinational test set. We demonstrate the use of these observations by presenting experimental results of two applications. In the first application, initial states are selected out of a combinational test set to facilitate deterministic test generation for irredundant faults. In the second application, the ability to set the initial state is used to increase the effectiveness of built-in self-test.

We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorter test application times and smaller memory requirements. As a by-product, the fault coverage is sometimes increased as well. Additionally, the ability to significantly reduce the length of the test sequences indicates that it may be possible to reduce test generation time if superfluous input vectors are not generated.

We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values of n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets.

We propose a procedure for generating test sequences for diagnosis of synchronous sequential circuits based on stuck at faults. In this procedure, we avoid the conventional fault-oriented test generation process by observing that a sequence to distinguish two faults can be obtained from a sequence T that detects both of the faults (such as a test sequence for fault detection) by changing T so as to "undetect" one of the faults, or change the time units or outputs where the fault is detected. To achieve this goal, the proposed procedure eliminates parts of T so as to render some of the faults undetected, or change their detection times or outputs. In the case where faults become undetected by the modified sequence, the detected faults are distinguished from the faults left undetected by the modified sequence based on pass/fall information. A pass/fall dictionary based on modified test sequences is proposed for this case. Alternatively, a standard dictionary can be used, and the proposed procedure can be used to change the time units or outputs where faults are detected in order to distinguish them. We present experimental results to demonstrate the levels of resolution that can be obtained by the proposed procedure with the proposed pass/fail dictionary, and the number of sequences required for this purpose.

Synchronizing sequences are important in facilitating the test generation process for detectable faults, and in identifying undetectable faults. Synchronizing sequences are also important in determining whether an undetectable fault can be removed from a circuit without affecting its normal operation, i.e., in determining whether a fault is "redundant." In this work, we show a class of faults such that a synchronizing sequence for a faulty circuit can be obtained by repeating the synchronizing sequence of the fault-free circuit. Identification of such faults can be done by simulating the faulty circuits under the repeated synchronizing sequence of the fault-free circuit. We present experimental results to demonstrate the existence of such faults in benchmark circuits.

Several functional delay fault models have been proposed before to allow functional test generation for delay faults. In this work, we extend these models to accommodate functional descriptions where inputs and outputs are more naturally represented by vectors carrying non-binary values. Such vectors are typical of high-level functional descriptions. Experimental results show that using the vector-based models does not result in loss of gate-level path delay fault coverage.

We propose a property of input patterns called sensitivity to guide test generation for combinational circuits. Under a sensitive pattern, a change in a single input value causes a change in an output value. Such a pattern is likely to be sensitive to the presence of a fault, and is likely to result in fault detection. We describe a test generation procedure that generates sensitive patterns based on logic simulation of the fault free circuit. The procedure achieves complete fault coverage for the circuits considered.

We describe a property based test generation procedure that uses static compaction to generate test sequences that achieve high fault coverages at a low computational complexity.A class of test compaction procedures are proposed and used in the property based test generator.Experimental results indicate that these compaction procedures can be used to implement the proposed test generator to achieve high fault coverage with relatively smaller run times.

We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory, and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T 0, and ensuring that every fault detected by T 0 is detected by the expanded version of at least one loaded sequence. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored at any time is on the average 10 % of the length of T 0, and that the total length of all the loaded sequences is on the average 46 % of the length of T 0. 1.

In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops.

We propose a procedure to select flip-flops for partial scan targeting the reduction of test length. We show that significant reductions in test length can be achieved by this procedure. In addition, experimental results show that using heuristics that target the test length does not have to increase the numbers of flip-flops that need to be scanned in order to achieve a given level of fault coverage. Consequently, it may be possible to perform partial scan selection targeting the two parameters, test length and fault coverage, without requiring more flip-flops than required for one of the parameters.

New techniques are presented in this paper to improve the efficiency of a test generation procedure for synchronous sequential circuits. These techniques aid the test generation procedure by reducing the search space, carrying out non-chronological backtracking, and reusing the test generation effort. They have been integrated into an existing sequential test generation system MIX to constitute a new system, named MIX-PLUS. The experimental results for the ISCAS-89 and ADDENDUM-93 benchmark circuits demonstrate the effectiveness of these techniques in improving the fault coverage and test generation efficiency.

Describes a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission-based static compaction procedures. Such procedures are used to reduce the lengths of test sequences for synchronous sequential circuits without reducing the fault coverage. The unique feature of the proposed approach is that test vectors omitted from the test sequence can be reintroduced at a later time. Reintroducing vectors helps to reduce the compacted test sequence length beyond the length that can be achieved if vectors are omitted permanently. Experimental results are presented to demonstrate the levels of compaction achieved by the sequence counting approach.

We propose a fault simulation based method to generate test patterns that achieve high fault coverages for combinational circuits. Due to the use of fault simulation, the proposed method is scalable and can be applied to large designs. The unique feature of the proposed method is that it uses a dynamic circuit partitioning scheme. Under this scheme, test patterns are generated so as to activate and propagate faults within specific subcircuits. The circuit is first partitioned statically. If it turns out that certain areas of the circuit still contain undetected faults, additional sub-circuits are added to the originally selected ones in order to better cover these areas. We present experimental results using stuck-at faults and bridging faults as the fault model driving the dynamic partitioning scheme.

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modifications to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and performance overheads. The proposed technique allows us to achieve complete coverage of detectable delay faults. A simple test generation procedure that guarantees complete coverage when used with the proposed technique is also described.

We describe the application of the following tools to ITC-99 benchmark circuits. Deterministic test generation: The test generation procedure MIX [1], and its extension MIX + [2], combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It includes a simulation-based test generation procedure based on LOCSTEP [3], a deterministic test generation procedure, and a test generation procedure based on genetic optimization. It assumes fault detection under the restricted multiple observation time approach [4]. Property-based test generation: The test generation procedure PROPTEST [5], [6] uses several simulation-based techniques to generate test sequences without resorting to branch-and-bound procedures. The techniques include static compaction based on vector restoration [7] to capture the most effective test subsequences of the test sequence, holding of test vectors [8] and perturbation of test vectors. PROPTEST achieves very high fault coverages at very low test generation times in spite of its relatively low complexity. Identification of undetectable faults and removal of redundant faults: Identification of undetectable faults prior to test generation can save the potentially wasted effort in targeting undetectable faults. Redundant faults can be removed from the circuit as a way to simplify the circuit and/or the test generation process. Procedures to identify undetectable faults and remove redundant faults were described in [9]-[11]. The definitions from [12] and [13] are used in these procedures. Selection of partial scan flip-flops: The partial scan selection procedure of [14] achieves the same fault coverage as full scan design by eliminating sequentially undetectable faults. The efficiency of the procedure is due to the use of several scan selection phases based on difficult to control flip-flops, and fast identification of undetectable faults. Sequential ATPG is invoked only in the last phase, when several flip-flops are already scanned, and the circuit is easier to handle by ATPG. The tools can currently handle single clock designs consisting of basic gates and D flip-flops. We are extending the tools to handle multiple clock designs and other primitives.

The effect of test compaction on fault diagnosis is experimentally investigated. Results for combinational and sequential circuits indicate that the diagnostic resolution achieved by compacted tests is only minimally lower than that for uncompacted tests. Furthermore, the diagnostic resolution of the compacted tests can be enhanced to be the same or better than that for the uncompacted rests while still retaining compactness.

This paper presents a technique and tool (SymSim) for symbolic fault-simulation of data-paths specified at the Register-Transfer Level (RTL) constrained by specific control sequences. SymSim achieves this using a symbolic value system suitable for RTL simulation. It also computes and maintains input dependency information at each node in the design using a novel artifact called Dependency Set which at any time-frame contains all primary input symbols that effect the current value on that node. Symbolic fault-simulation can be used along with a symbolic test-generator to detect multiple faults with a single test to reduce test length and and generation time.

We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.

We describe a path selection procedure that selects target faults for path delay fault test generation. Since large numbers of path delay faults may be untestable, the proposed procedure does not select a fixed set of paths. Instead, it provides compactly represented subsets of paths, referred to as super-paths, and allows the test generation procedure to select one path out of each subset based on testability considerations.

We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values of n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets.

We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The procedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.

Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In this work, we propose a representation of test patterns for genetic optimization based test generation, where subsets of inputs are considered as indivisible entities. Using this representation, crossover between two test patterns t/sub 1/ and t/sub 2/ copies all the values of each subset either from t/sub 1/ or from t/sub 2/. By keeping input subsets undivided, activation and propagation capabilities of t/sub 1/ and t/sub 2/ are expected to be captured and carried over to the new test patterns. Experimental results presented show that the proposed scheme results in complete stuck-at test sets and n-detection test sets for combinational circuits, even in cases where other procedures report incomplete fault coverages.

For the original paper see ibid., vol. 16, no. 7, p. 759-62 (1997). Here Pomeranz and Reddy comment on the aforementioned paper by K. Heragu et al.

We propose a new static test compaction procedure for synchronous sequential circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. The previous procedure that achieved high levels of compaction using this approach attempted to omit test vectors from a given test sequence one at a time or in subsequences of consecutive vectors. The omission of each vector or subsequence required extensive simulation to determine the effects of each omission on the fault coverage. The procedure proposed here first omits (almost) all the test vectors from the sequence, and then restores some of them as necessary to achieve the required fault coverage. The decision to restore a vector requires simulation of a single fault. Thus, the overall computational effort of this procedure is relatively low. The loss of compaction compared to the scheme that omits the vectors one at a time or in subsequences is small in most cases. Techniques to speed up the restoration process are also investigated, including consideration of several faults in parallel during restoration, and the use of a parallel fault simulator. Experimental results are presented to demonstrate the effectiveness of vector restoration as a static compaction technique.

It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems.

We propose a technique to speed up restoration-based static test sequence compaction for synchronous sequential circuits. The proposed algorithm reverses the order of the test vectors during restoration. Specifically, every time a subsequence of T is restored to detect a subset of faults, the subsequence is placed at the end of the compacted sequence denoted by T/sub p/. In this way, a fault detected by T/sub p/ is guaranteed to remain detected by T/sub p/ at the end of the compaction process, and need not be resimulated as was the case with some of the earlier restoration based compaction methods. Experimental results presented in this paper demonstrate the effectiveness of the proposed procedure.

We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. For every subsequence, it also accepts the vector to be scanned-in before the subsequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences. The reductions in test application time of the proposed procedure are demonstrated through experimental results.

The use of appropriate storage schemes for test patterns and test responses on a tester may result in reduced memory requirements, and thus reduced tester cost. Such storage schemes result in new test compaction objectives beyond the need to reduce the number of test patterns as much as possible. We propose test generation procedures that take such test compaction objectives into account. Experimental results are presented to demonstrate the effectiveness of the proposed procedures in reducing the storage requirements of the resulting test sequences.

We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.

In most applications of digital logic circuits, the circuit function is either specified (0,1) or unspecified (don't - care) for every input condition. However, there are also applications where any one of a subset of functions is an acceptable solution, even though it is not possible to represent all the functions in terms of output don't-cares. In this case, we say that the function is flexible. In this work, we propose a synthesis procedure for flexible functions based on functional blocks called comparison units.

Proposes a non-scan design-for-testability (DFT) method to increase the testability of synchronous sequential circuits. Non-scan DFT allows at-speed testing, as opposed to scan or partial-scan based DFT that normally leads to low-speed testing and longer test application times due to scan operations. The proposed method is based on the identification of several types of restrictions imposed by the combinational logic of the circuit on the values that can be assigned to the next-state variables. These restrictions limit the set of states the circuit can reach, thus limiting the set of input patterns that can be applied to its combinational logic during normal operation. This in turn limits the fault coverage that can be achieved. The proposed DFT procedure is different from other non-scan based DFT procedures in that it relies on lines available locally to drive the inserted DFT logic, avoiding the routing of primary input lines to the flip-flops, and the routing of internal lines to the primary outputs.

We introduce a new concept for test sequence compaction referred to as recycling. Recycling is based on the observation that easy-to-detect faults tend to be detected several times by a deterministic test sequence, whereas hard-to-detect faults are detected once towards the end of the test sequence. Thus, the suffix of a test sequence detects a large number of faults, including hard-to-detect faults. The recycling operation keeps a suffix S/sub 1/ of a test sequence T/sub 1/ and discards the rest of the sequence. The suffix S/sub 1/ is then used as a prefix of a new test sequence T/sub 2/. In this process, S/sub 1/ is expected to detect the more difficult to detect faults as well as many of the easy-to-detect faults, resulting in a new sequence T/sub 2/ which is shorter than T/sub 1/. Recycling is enhanced by a scheme where several faults are targeted simultaneously to generate the shortest possible test sequence that detects all of them.

We describe a time-efficient procedure for identifying undetectable and redundant faults in a synchronous sequential circuit, without using a sequential circuit test pattern generator. The proposed procedure is based on the use of a limited length iterative logic array model of the circuit, and has two phases. In the first phase, faults that will not be proved to be undetectable are identified. In the second phase, undetectable faults are identified out of the remaining faults using a combinational circuit test generator. Sequential static learning on the fault-free circuit and a subset of unreachable states are used in the proposed procedure to increase the amount of information available when considering an iterative logic array model of limited length. An undetectable fault in a synchronizable circuit that leaves the faulty circuit synchronizable is identified as a redundant fault. Experimental results presented in this work demonstrate the effectiveness of the proposed techniques in finding undetectable and redundant faults. Larger numbers of undetectable and redundant faults are found compared to earlier works.

We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determination of the test sequence applied to the circuit-under-test, using fewer logic gates than the original scheme. In addition, a procedure to match the parameters of the test pattern generator to the circuit-under-test is proposed to replace the random selection used in the basic scheme. The effectiveness of these improvements is demonstrated through experimental results.

We propose a procedure for generating test sequences for diagnosis of synchronous sequential circuits based on stuck-at faults. The test generation procedure avoids the conventional fault-oriented test generation by observing that a sequence to distinguish two faults can be obtained from a sequence that detects both of the faults (such as a test sequence for fault detection) by changing the sequence so as to "undetect" one of the faults. To achieve this goal, the proposed procedure eliminates parts of a test sequence for fault detection so as to render some of the faults undetected. The faults that are detected by the resulting sequence are distinguished from the faults left undetected by the sequence based on pass/fail information. A pass/fail dictionary suitable for diagnosis with the resulting test sequences is also proposed. Alternatively, a conventional dictionary can be used, and the proposed procedure can be used to change the time units or outputs where faults are detected, in order to distinguish them. We present experimental results to demonstrate the levels of resolution that can be obtained by the proposed procedure with the proposed pass/fail dictionary, and the number of sequences required for this purpose.

We describe a time-efficient procedure for removing sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use the properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit. By removing several redundant faults simultaneously, the number of repetitions of the test generation procedure invoked to identify redundant faults is reduced. Experimental results presented in this work demonstrate the effectiveness of the proposed removal procedure.

We consider two topics related to the testing of synchronous sequential circuits. The first topic deals with synchronizable circuits and their synchronizing sequences. Synchronizing sequences are important in facilitating the test generation process for detectable faults, and in identifying undetectable faults. They are also important in determining whether an undetectable fault can be removed from a circuit without affecting its normal operation. We show a class of faults for which a synchronizing sequence for the faulty circuit can be easily determined from the synchronizing sequence of the fault free circuit. We also consider circuits that have a reset mechanism, and show how reset can ensure that no single fault would cause the circuit to become unsynchronizable. The second topic we consider deals with test sequence partitioning to speed up static test compaction. We propose a procedure for partitioning a given test sequence into subsequences such that the cumulative fault coverage of all the subsequences, when applied as independent test sequences, is equal to the fault coverage of the original sequence. Each subsequence can then be compacted independently.

N-detection stuck-at test sets were shown to be effective in achieving high defect coverages for benchmark circuits. However, the definition of n-detection rest sets allows the same set of faults to be detected by several different tests, thus potentially detecting the same defects. We propose an extension of the n-detection model that alleviates this problem by considering m-tuples of faults and requiring that different tests would detect different m-tuples. We present experimental results to support this model.

We propose a method of fault diagnosis at the chip level that reduces the number of simulations required to locate defect site(s) by logically partitioning the circuit into subcircuits. Candidate subcircuits that potentially contain the defect site(s) are identified and further partitioned until the defect site is located with the required resolution. Both stuck-at faults and nonfeedback bridging faults are considered as target fault models to represent defects. At the base of the fault location procedure is a procedure to identify subcircuits that potentially contain the fault site. This procedure is matched to the fault model being considered, thus allowing the same partitioning scheme to be applied to various fault models. The procedure presented here is applicable to combinational and fully scanned sequential circuits. Experimental results are presented to demonstrate the effectiveness of circuit partitioning in reducing the number of fault simulations required to locate a fault.

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.

The use of three-valued logic for the fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of a high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. Based on this observation, we propose a fault simulation procedure that uses a conventional fault simulation procedure enhanced by a simple implication procedure. The proposed fault simulation procedure identifies faults that are detected under the multiple observation time approach and under a special case of this approach, called the restricted multiple observation time approach. The results of the proposed simulation procedure are compared to the results of a previously proposed procedure to demonstrate its effectiveness. Heuristics to guide a test generation procedure whose test sequences are effective for faults that can only be detected under the multiple observation time approach are also described.

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. In addition, by breaking an untestable path into two or more testable subpaths, it is possible to obtain a fully testable circuit. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. When the number of paths is sufficiently small, and if the test generation procedure to be used for the circuit is known, a procedure is given to perform test-point insertion directly targeting the path delay faults that are still untestable. Experimental results are presented to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Test sets that detect each stuck-at fault n>1 times (called n-detection stuck-at test sets) were shown to be effective in achieving high defect coverages. In addition, a pseudofunctional fault model defined before was shown to result in test sets having similar defect coverages. Previous studies of n-detection stuck-at test sets and pseudofunctional test sets were for combinational circuits, In this paper, we study detection stuck-at test sequences and pseudofunctional test sequences for synchronous sequential circuits. Considering stuck-at faults, we propose five definitions of the number of detections achieved by a test sequence. These definitions lead to five different definitions of n-detection stuck at test sequences. We discuss the effects of these definitions on fault-simulation and test-generation procedures and present experimental results for benchmark circuits to evaluate their relative effectiveness. The experimental results indicate the usefulness of the simplest definition in generating test sequences that achieve improved defect coverages. We also describe a pseudofunctional fault model that extends previous definitions. We describe fault-simulation and test-generation methods for this model and give experimental data to evaluate its effectiveness. The results indicate that this model too can be used to generate test sequences with improved defect coverage. Its advantages and disadvantages compared to the n-detection stuck-at model are also considered.

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

Autonomous circuits such as linear feedback shift registers (LFSRs) and cellular automats are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuit-under-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSRs and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults.

A previously proposed test generation procedure based on genetic optimization proved to have several advantages in terms of fault coverage; however, it produced large test set sizes. We investigate a way to generate compact test sets using this procedure by embedding it into a test compaction procedure. The compaction procedure constructs a compact test set out of the best tests contained in several test sets produced by the genetic optimization based test generation procedure. Using this approach, it is possible to significantly reduce the test set sizes obtained.

We develop the basic definitions and procedures for a test generation concept referred to as templates that magnifies the effectiveness of test generation by taking advantage of the fact that many faults have "similar" test sequences. Once a template is generated, several test sequences to detect different faults are derived from it at a reduced complexity compared to the complexity of test generation.

We present an improved procedure for fault simulation under themultiple observation time approach based on state expansion.Under state expansion, an incompletely specified state reachedduring fault simulation is replaced by 2{k} states, each one assigninga different combination to k unspecified present state variables.For each expanded state, additional output values are thenimplied. As a result, a fault that cannot be identified as detectedusing conventional simulation may now be identified as detected.The procedure proposed here enhances state expansion by backwardimplications to take advantage of every present state variablevalue specified under state expansion. As a result of usingbackward implications, fewer states need to be considered afterstate expansion, fewer state expansions are potentially neededfor every fault, and the number of faults that can be efficientlyconsidered is increased. Experimental results are presented tosupport these claims.

We consider the problem of generating tests for single stuck-at faults that remain valid in the presence of undetected single stuck-at faults. We show that enumeration of all subsets of faults that may occur in the circuit without being detected may be too computation intensive, and is not necessary to obtain high-quality test sets. We present a test generation procedure to generate tests that remain valid in the presence of undetected faults. The procedure targets simultaneously multiple subsets of undetected faults that may be present in the circuit. It thus allows test generation time to be minimized by allowing the number of subsets of faults considered explicitly to be minimized. Based on this test generation procedure, several approximate procedures are also explored.

We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed test application. We introduce a uniform, parametrized structure for test pattern generation. By matching the parameters of the test pattern generator to the circuit-under-test, high fault coverage is achieved. In many cases, the fault coverage is equal to the fault coverage that can be achieved by deterministic test sequences. We also investigate a method to minimize the size of the test pattern generator, and study its effectiveness alone and in conjunction with the insertion of test-points.

The authors propose a new procedure for static compaction that belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its size without reducing the fault coverage. The previous procedures that achieved high levels of compaction using this technique attempted to omit test vectors from a given test sequence one at a time or in consecutive subsequences. Consequently, the omission of each vector or subsequence required extensive simulation to determine the effects of each vector omission on the fault coverage. The proposed procedure first omits (almost) all the test vectors from the sequence, and then restores some of them as necessary to achieve the required fault coverage. The decision to restore a vector requires simulation of a single fault. Thus, the overall computational effort of this procedure is significantly lower. The loss of compaction compared to the scheme that omits the vectors one at a time or in subsequences is small in most cases. Experimental results are presented to support these claims.

We describe an approach to test generation for synchronous sequential circuits that accepts a given test sequence T and targets only faults that could not be detected by the test generation procedure that produced T (hard to detect faults). For every fault f that remains undetected by T, the proposed procedure extracts from T a small number of subsequences (two or three subsequences) that can be combined to form a test sequence for f. It then adds these sequences, if found, to T. By exploring only test sequences that can be extracted from T, a restricted search space for test generation is obtained, and it can be thoroughly explored. Experimental results show that non-trivial numbers of additional faults can be detected by using the proposed procedure to extend a given test sequence T.

Test sets that detect each stuck-at fault n>1 times (called n-detection test sets) were shown to achieve higher defect coverages than conventional single stuck-at 1-detection test sets. Previous studies of n-detection test sets concentrated on combinational circuits. In this work, we study n-detection test sequences for synchronous sequential circuits. We propose four definitions of the number of detections achieved by a test sequence. We describe fault simulation and test generation procedures based on these definitions, and evaluate them on benchmark circuits by using non-feedback bridging faults to model defects. The results indicate the usefulness of the simplest definition in generating test sequences that achieve improved defect coverages.

In this work, fault location based on a fault dictionary is considered at the chip level. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall diagnosis effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS-85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient than dynamic diagnosis. Next, a method to derive small dictionaries without losing resolution of modeled faults is proposed, based on extended pass/fail analysis. The same procedure is applicable for selecting internal observation points to increase the resolution of the test set. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the proposed methods.

A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified faulty machines. Experimental results are presented to demonstrate the effectiveness of implicit fault enumeration in detecting large numbers of multiple faults and in guaranteeing detection of all the faults or all the faults up to a specific multiplicity.

We present a method to generate test sequences that detect large numbers of faults (close to or higher than the number of faults that can be detected by deterministic methods) at a cost which is significantly lower than any existing test generation procedure. The generated sequences can be used alone or as prefixes of deterministic test sequences. To generate the sequences, we study the test sequences generated by several deterministic test generation procedures. We show that when deterministic test sequences are applied, the fault-free circuits go through sequences of state transitions that have distinct characteristics which are independent of the specific circuit considered. Test sequences with the same characteristics are generated in this work by using logic simulation only on the fault-free circuit, and by considering several random patterns as candidates for inclusion in the test sequence at every time unit. By fault simulating these sequences, we find that the fault coverage achieved is very close to the fault coverage achieved by deterministic sequences, and sometimes is even higher.

We consider the problem of correcting errors in a macro-based circuit. Our formulation of the problem allows the correction of errors that arise both in the context of design error correction before the circuit is realized, and when a physical circuit needs to be corrected or diagnosed. Two error classes are defined, namely, component errors and line errors. Both single and multiple errors are considered. Accurate correction procedures are given for single errors. Heuristics are used for correcting multiple errors. Experimental results are given to demonstrate the correction procedures presented.

This paper addresses the problem of obtaining accurate fault coverages for the gate delay fault model. For a gate delay fault, it is not sufficient to only find a test. One also has to accurately determine the size of the fault detected. We first show that previous methodologies for determining gate delay fault coverages have certain limitations. A method is then investigated to determine all the possible ranges of detected fault sizes, using the traditional fixed sampling time approach. However, with the constraints of a realistic inertial delay model, it is then shown that it might still not be possible to achieve the coverages required to guarantee circuit operation without malfunctions. A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible. An alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverages obtained under the proposed delay model. Results of experiments performed to evaluate these methods are given.

It was recently observed that, in order to improve the defect coverage of a test set, test generation based on fault models such as the single-line stuck-at model may need to be augmented so as to derive test sets that detect each modeled fault more than once. In this work, we report on test pattern generators for combinational circuits that generate test sets to detect each single line stuck-at fault a given number of times. Additionally, we study the effects of test set compaction on the defect coverage of such test sets. For the purpose of experimentation, defect coverage is measured by the coverage of surrogate faults, using a framework proposed earlier. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction if the test set is computed using appropriate test generation objectives. Moreover, two test sets generated using the same test generation objectives, except that compaction heuristics were used during the generation of one but not the other, typically have similar defect coverages, even if the compacted test set is significantly smaller than the noncompacted one. Test generation procedures and experimental results to support these claims are presented.

Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines such that all feedback loops are included within the submachines. We consider a test generation procedure that takes advantage of such a decomposition. The paper focuses on one of the subproblems of the test generation problem, the input sequence propagation problem. The problem occurs when a test sequence T is applied to an embedded machine M'. The fault effects of the target faults of M' appear on the outputs of M' and must be propagated through a machine M driven by M'. We propose a solution to the problem of propagating the fault effects of a machine M' through another machine M. The solution maximizes the number of faults whose fault effects are propagated simultaneously. In this way, the overall test generation time and the test application time are minimized.

The advantages of the multiple observation time approach for fault diagnosis have been demonstrated before by a fault diagnosis procedure based on partial specification of initial states. It was also shown that it is possible to perform fault simulation under the multiple observation time approach at very low computational overhead compared to conventional simulation. In this work, we combine these procedures and propose a low-complexity fault diagnosis procedure under the multiple observation time approach. Several observations made in this work allow us to increase the effectiveness of the proposed diagnosis scheme in terms of the resolution it achieves and its complexity.

We consider delay testing of a specific class of logic circuits, the so called 'unate gate networks (UGNs)', which are of importance for the realization of dynamic CMOS logic and in the field of on-line error detection. It has been shown earlier, that UGNs can be tested completely for delay faults with 'universal' test sets. This result even holds for designs which are not completely path delay testable, since the above test sets check the temporal correctness of a circuit by testing 'path systems' instead of single paths. A universal test set only depends on the computed function and thus, is valid for any unate gate network implementation of this function. This universal test property has to be paid by an increase in test set size, since a design independent test set will in general be larger than a design dependent one. In this paper, we show how to tailor a universal test set to a specific design in order to reduce its size maximally without losing test quality. Experimental results demonstrate that the resulting delay test sets are very compact, and large savings in test set size of up to 96.71% can be achieved compared to the universal test set.

Article Free Access Share on On static compaction of test sequences for synchronous sequential circuits Authors: Irith Pomeranz Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA Electrical and Computer Engineering Department, University of Iowa, Iowa City, IAView Profile , Sudhakar M. Reddy Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA Electrical and Computer Engineering Department, University of Iowa, Iowa City, IAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 215–220https://doi.org/10.1145/240518.240558Published:01 June 1996Publication History 114citation239DownloadsMetricsTotal Citations114Total Downloads239Last 12 Months7Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We define a new delay fault model, called the double transition fault model. Under this model, a fault is associated with a pair of lines and a pair of transitions on these lines. The model captures the effects of defects that increase the delays of two (or more) individual lines by an amount that causes the circuit to fail when signals are propagated through both lines. It thus provides a simplification of the path delay fault model, that does not suffer from the exponential behavior of this model. We propose a test generation procedure for double transition faults, based on reordering of a given test set for stuck-at faults. The procedure does not require enumeration of all double transition faults, and is thus applicable to circuits with large numbers of lines. We present experimental results of this procedure for several benchmark circuits.

We propose a method of fault diagnosis that reduces the number of simulations required to locate defect site(s) by logically partitioning the circuit into subcircuits. Candidate subcircuits that potentially contain the defect site(s) are identified and further partitioned, until the defect site is located with the required resolution. Experimental results are presented to demonstrate the effectiveness of circuit partitioning in reducing the number of fault simulations.

Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speech, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.

Sharing of logic among the various primary outputs of a circuit reduces the overall size of the circuit. However, shared logic may have adverse effects on the number of paths and on the path delay fault testability of the circuit. In this work, we propose a procedure to reverse the effects of logic sharing when it causes a significant increase in the number of paths and a significant reduction in testability. Experimental results show that the proposed procedure is an effective preprocessing step of global optimization, that increases the effectiveness of resynthesis procedures based on local transformations.

We study the effects of test compaction on the defect coverage of test sets for modeled faults. Using a framework proposed earlier, defects are represented by surrogate faults. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction, if the test set is computed using appropriate test generation objectives. Moreover, two test sets, one compacted and one non-compacted, generated using the same test generation objectives, typically have similar defect coverages, even if the compacted one is significantly smaller than the uncompacted one. Test generation procedures and experimental results to support these claims are presented.

We consider the removal of redundant logic from synchronous sequential circuits that have synchronizing sequences. The logic to be removed is identified by determining line stuck-at faults that do not affect the operation of the circuit. Such signal lines and some of the logic surrounding them can be removed without affecting the operation of the circuit. We show that circuits that have synchronizing sequences have certain properties that help in identifying logic that can be removed. Specifically, their state diagrams have a strongly connected component that contains all the synchronization states. This strongly connected component, called the main strongly-connected component, is reachable from all other strongly connected components. In addition to redundant faults that can always be removed, we show that there are two types of partially detectable faults in circuits that have synchronizing sequences. In the presence of the first type of faults, the circuit becomes unsynchronizable. Signal lines carrying such faults cannot be removed. The other type of partially detectable faults leave the circuit synchronizable. We show that such faults do not affect the main strongly connected component, and hence the corresponding signal lines can be removed without affecting the operation of the circuit after it is synchronized. We also define weakly synchronizable circuits acid derive similar results regarding the removal of redundant logic in them. The class of removable lines is thus extended beyond those corresponding to redundant faults to include some partially detectable faults as well. We present experimental evidence to the existence of partially detectable faults that correspond to signal lines that can be removed in benchmark circuits.

The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is described, and methods for synthesizing circuits with reduced lower bounds on the numbers of tests are developed. Experimental results are presented to demonstrate various aspects of the problem.

A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural (logic network) approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural (logic network) information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods.

The effectiveness of residue code checking for online error detection in parallel two's complement multipliers has only up until now been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recoding circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be self-testing, and thus achieve the totally self-checking goal for the overall circuit, are also derived.

We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Experimental results are presented to evaluate the effectiveness of the compaction procedure.

We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit.The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units.Comparison units are fully testable for stuck-at faults and for path delay faults.In addition, they have small numbers of paths and gates.These properties make them effective building blocks for synthesis of testable circuits.Experimental results demonstrate reductions in the number of gates and paths and increased path delay fault testability.The random pattern testability for stuck-at faults remains unchanged.

Recently, it has been shown in [1] and [2] that in order to verify the correct timing of a manufactured circuit not all of its paths need to be considered for delay testing. In this paper, a theory is developed which puts the work of these papers into a common framework, thus allowing for a better understanding of their relation. In addition, we consider the computational problem of identifying large sets of such not-necessary-to-test paths. Since the approach of [1] can only be applied for small scale circuits, we develop a new algorithm which trades quality of the result against computation time, and allows handling of large circuits with tens of millions of paths. Experimental results show that enormous improvements in running time are only paid for by a small decrease in quality.

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. It can also potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of branch and bound strategies. A parameter called /spl Delta/ is used to control the number of functional faults targeted and thus the number of tests generated. If /spl Delta/ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given function. An appropriate subset of tests can be selected once the implementation is known. The test sets generated for various values of /spl Delta/ are fault simulated on gate-level realizations to demonstrate their effectiveness.

A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified faulty machines. Experimental results are presented to demonstrate the effectiveness of implicit fault enumeration in detecting large numbers of multiple faults.

Summary form only given. As the testing area becomes mature, the challenges it poses shift. We describe some of these challenges and how they are addressed in recent works in various areas of testing. In recent years, the formulations of testing problems have changed from "given a problem, find a solution" to "given a problem and quality measures, find a high-quality solution". Quality guarantees in the form of lower and upper bounds and optimal solutions are derived, in addition to the more conventional demonstration of performance on benchmark circuits. Quality guarantees allow one to measure the distance between a given solution and an optimal solution, and provide criteria for evaluating a new procedure that are more effective than comparison to previously proposed procedures. We review several areas where bounds and optimal solutions have been found. Most procedures are specific to a given problem, and cannot be reused to solve other problems. In contrast, general-purpose paradigms allow a large variety of problems to be solved cost-effectively by plugging in the appropriate procedures into the same algorithm. Such paradigms allow faster program development and reuse of expertise acquired in solving other problems under the same paradigm. We describe several attempts at using existing paradigms and developing new ones, that successfully compete with special-purpose procedures. Recent works address testing issues at increasingly higher levels of the design cycle and offer an integrated treatment of design and test. High-level failure models are considered as well as solutions that are completely independent of a failure model. We describe some of these works and the advantages of the two directions. We conclude with an (incomplete) list of challenges for future research.

The use of three-value logic for fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. The proposed simulation procedure is compared to a previously proposed one to demonstrate its effectiveness.

We propose a procedure to generate compact test sets for bridging faults under I/sub DDQ/ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures.

It is generally thought that accurate analysis of aliasing requires non-fault dropping fault simulation. We show that fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. The fault dropping process is most effective when the test set size is small. Extensions to large test sets are also considered. We present a fault simulation procedure that takes maximum advantage of fault dropping and present experimental results to support its effectiveness.>

We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.>

A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter (e.g., operand size), and indirectly, to random-logic circuits as well. Under the proposed approach, exhaustive search for an optimal solution is performed for small versions of the target circuit, obtained by scaling-down all the size parameters of the circuit (e.g., by reducing the operand size). The optimal solutions obtained for the small circuits are studied, and analytic rules are derived to capture their common features. Using these rules, the solutions are scaled-up into a high-quality solution for the large target circuit. The method, its feasibility and limitations are described in this work. The method is applied to two problems related to testing of digital circuits, namely, test generation for stuck-at faults and test generation for path delay faults.>

This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M < N test vectors, without loss of fault coverage. During test generation, we also find a lower bound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.

We consider the problem of correcting multiple design errors in combinational circuits and in finite-state machines. The correction method introduced for combinational circuits uses a single error correction scheme iteratively to correct multiple errors. It uses a heuristic measure that guides the selection of single, local circuit modifications that reduce the distance between the incorrect implementation and the specification. The distance is measured by the size of a correction hardware, which is a block of logic that can be added to the implementation in order to correct it without performing additional circuit modifications. The correction method for finite-state machines is based on the use of pairwise distinguishing sequences for specification and implementation states, and employs the same hardware correction scheme. Experimental results are presented to support the effectiveness of the proposed methods.>

A test generation procedure for path delay faults is proposed that targets all path delay faults in the circuit-under-test. The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a nonenumerative method of considering faults that never explicitly targets any specific path delay fault. Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults.

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability.Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs.Each one of these subsets can be tested separately.The number of paths that need to be tested directly is thus reduced.Test-point insertion is done to reduce the number of paths, using a time-efficient procedure.Indirectly, it also reduces the number of tests and renders untestable paths testable.Experimental results are presented to demonstrate the effectiveness of the method proposed in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

The multiple observation times approach was proposed as a test generation approach for fault detection, and was shown to alleviate deficiencies of conventional test generators. In this work, the multiple observation times approach is applied to fault location. It is shown that the use of multiple observation times has the potential of significantly enhancing the resolution of a given test set. A definition of pass/fail diagnosis suitable for the multiple observation times approach is also given. Experimental results are provided to demonstrate the approach and its advantages. 1.

Conventional tools for test generation and fault simulation appear to the test engineer as black boxes which neither communicate their results in a convenient way, nor allow for any interactive guidance by the test engineer. In contrast, the HIT system presented in this paper supports interactive test engineering, thus combining the power of state level test generation algorithms with the high level knowledge of the test engineer. Since the HIT system has been integrated into a hierarchical design system (CADIC), the results of test tools can be visualized at the hierarchical circuit specifications given by the designer. Based on this visualization, the critical, untestable areas of the circuit can be easily located. Additionally, the test engineer is supplied with flexible test tools, which allow to actively guide the test development process. Thus, module specific test strategies can be applied or high level knowledge about the functionality of the overall circuit can be 'communicated' to speed-up test generation and redundancy identification. An application example shows that with simple strategies for interactive test engineering the results of test generation can be improved dramatically.

A completely testable circuit does not have any undetectable or redundant faults. We consider the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults. The method proposed is based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults. Thus, the proposed approach reduces the circuit size in addition to reducing or eliminating the extra hardware that may be otherwise necessary to render the circuit completely testable. A theoretical framework for achieving this goal was established earlier (1993). In this work, we give a detailed procedure based on the concepts of the previous work and give experimental results of its application.

This paper presents a method of test compaction for stuck-at faults in combinational circuits, that complements previously proposed methods and allows further reduction in test set size in a cost-effective way. A given test set is compacted by generating additional test vectors. Each test vector added allows the removal of two or more test vectors from the existing test set, thus reducing its size. Experimental results for benchmark circuits demonstrate the effectiveness of the method.>

Considers undetectable and redundant faults in synchronous sequential circuits. The authors state and formally prove results regarding the types of faults identified as undetectable and/or redundant by existing test generation procedures and by procedures proposed specifically for this purpose. They distinguish between procedures that identify undetectable faults and procedures that identify redundant faults. They also give a detailed characterization of the types of faults that can be classified by each procedure considered and the types of faults that cannot be classified. The authors present examples and experimental evidence of these limitations.>

Examines the vertex deletion problem for weighted directed acyclic graphs (WDAGs). The objective is to delete the fewest number of vertices so that the resulting WDAG has no path of length >/spl delta/. Several simplified versions of this problem are shown to be NP-hard. However, the problem is solved in linear time when the WDAG is a rooted tree, and in quadratic time when the WDAG is a series-parallel graph.>