IC test methodologies all generate scan tests based on logical stuck-at and timing fault models that assume only a single passive physical defect localized at some circuit node. However, transistors fabricated in advanced technologies are subject to increasing random process variations that can significantly impact multiple devices, and result in highly nonlinear circuit behavior under specific circuit operating conditions. These changes can cause failures missed by current test methods that mostly target passive defects. We make the case for “variation aware” testing of high-performance digital circuits that prioritizes targeting changes in the most performance sensitive device parameters. Our specific focus in this paper is on developing reliable tests for timing failures caused by random variations in transistor threshold voltages.

Stringent quality requirements for safety-critical applications drive the demand for "zero defects" in modern ICs. In this context, delay characterization of standard cells for resistive open defects is an increasing concern due to aggressive timing margins in digital circuits. The problem is made worse by the large number of open defect sites in standard cells, combined with a wide range of defect resistance values for each site. This incurs possible prohibitive costs for defect simulation and characterization. To alleviate this complexity, we propose Resistive Fault Dominance (RFD) for resistive open defects. RFD eliminates simulations of certain open defects with intermediate defect resistance values that are guaranteed to exceed specified timing margins for standard cells, based on tests for specific "dominant" open defects. This can significantly reduce the computational costs of cell library characterization and simulation effort by 84%-91%. An algorithmic fault simulation methodology for resistive open defects on parasitic-extracted (PEX) transistor-level netlist is developed.

Silent Data Corruptions (SDCs) pose a critical challenge to computer system reliability, arising from vulnerabilities across different layers of the computing stack. This paper addresses this challenge through three complementary contributions that systematically target SDCs from hardware manufacturing to application-level resilience. First, we analyze timing failures caused by random process variations in advanced technology nodes, revealing that extreme slow paths at lower voltages are dominated by single weak transistors—insights crucial for manufacturing and in-field testing. Second, we introduce an LLM-driven framework that generates targeted functional test programs to induce SDCs, demonstrating its effectiveness in stressing hardware, uncovering latent vulnerabilities, and increasing energy consumption in a given device under test (DUT), making it a valuable tool for in-field testing. Third, as machine learning continues to drive advancements across critical domains such as healthcare, finance, and autonomous systems, ensuring its reliability is paramount. However, the susceptibility of these applications to SDCs threatens their reliability and robustness. To address this, we propose Fidelity-Q, a novel fault injection methodology to evaluate the impact of SDCs on Quantized Neural Networks (QNNs), showing that lower-bit quantization increases error susceptibility. Collectively, these contributions provide a comprehensive approach to identifying, analyzing, and mitigating SDCs across the computing stack, from hardware testing to machine learning applications.

We make the case, supported by recently published industrial data, that many of the hard to detect failures that escape post manufacturing tests and contribute to silent data corruption are timing failures resulting from significant increases in the delay of random circuit paths caused by manufacturing process variations. However, these are challenging to target at test because high coverage scan path delay tests are impractical. This research is investigating the characteristics of extreme statistical outlier slow paths in circuits with the goal of finding alternate test methods to detect and screen them out. We are particularly focused on low voltage operation because circuit delays due to process variations are greatly accentuated in that environment. A significant observation from this research is that delay increases from variability are not uniformly distributed among the gates in a potentially failing slow path. Instead, most of the delay increase is concentrated in a single gate. This suggests that node oriented TDF timing tests may remain at least partially effective in detecting many of the timing failures caused by process variations. We show how the test voltage and clock timing of the applied TDF scan tests can be optimized to enhance the likelihood of detection of these marginal timing parts.

For large scale data center fleets, a single Silent Data Error (SDE) event leading to computational inaccuracies has the potential to be disruptive to their end users especially when mission critical workloads are being run. With large deployments of machines in the data center, SDE rates as low as 10FIT can be detected. At the same time, silicon die area and core count in an SOC is continuing to increase with advanced packaging technologies further making it challenging. Intel has developed DCDiag tool that has a suite of diverse tests that rely on pseudo-random data and instruction combinations to detect data miscompute. These tests can be studied empirically to develop optimization methods to identify test content for effectively detecting SDEs at CPU manufacturing flow, ODM screening flow and infield fleets. While optimizing screening content is key and could be different across product generations, detecting SDEs is challenging since many of the data miscompare errors are dependent on a combination of conditions that may exist during an error. This leads to poor repeatability of DCDiag tests to capture the SDE fails which demands long test times and/or resiliency methods to minimize impact. This presentation outlines the challenges for SDE detection from CPU manufacturing to Data Center fleets and the why the notion of resilience in HW and SW is critical in data centers.

Chip manufacturers and hyperscalers are becoming increasingly aware of the problem posed by Silent Data Errors (SDE) and are taking steps to address it. Major computing facilities operators like Meta and Google have emphasized the critical role of SDEs in today’s microprocessors. Numerous studies in the literature have highlighted the severity of this issue, especially in datacenter applications operating at large scales. These errors can lead to data loss and require a significant amount of time and effort to resolve through debugging engineering efforts, which can take months to complete. In this paper, we provide an overview of the issue of SDEs, including an explanation of the problem and the current methods used to address it, as well as gaps that still exist in addressing the issue. We also discuss the different sources of SDEs, including post-manufacturing testing failures, voltage and timing marginalities, and hard-to-detect faults. The paper emphasizes the impact of timing marginalities as a significant source of SDEs. Finally, our spotlight points to the architecture and system dimensions of the problem: we describe the challenges of measuring the true (still unknown) rates of SDE from CPUs, and emphasize on the role of detailed microarchitectural simulation models for this purpose. We present data on the severity of SDEs and their predicted rates under various operating conditions, sources of faults, and technology fabrication nodes.

There has been speculation that the source of many of the unpredictable and hard to diagnose intermittent errors being increasingly observed in operation are timing marginalities, accentuated in low voltage operation, that escape detection during test. To investigate this possibility, we present a comprehensive study, combining analytical modeling with simulation, of the impact of random process variations on the timing of CMOS gates and circuit paths when operating at significantly reduced voltages. Our analysis is validated with the help of production test data recently published by a large industrial team for an advanced FinFET technology [1]. A key, somewhat unexpected, observation from this study is that virtually all variability paths that are statistical outliers, slow enough to cause timing failure, contain a single extremely weak transistor which contributes a large share of the increased delay. This suggests that TDF timing tests, that target localized “lumped” delay defects, may also detect many timing failures caused by distributed delays from process variations. The perceived need for path delay testing to target such failures is at least partially mitigated. We further show how the results of the analysis in this paper can be leveraged for conditioning the voltage and timing of the applied TDF scan tests to help enhance detection of such marginal timing parts, thereby reducing test escapes and minimizing system level tests.

Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases in test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted by DC tests. Recent research has shown the need for multi-pattern tests where intermediate defect resistance values are concerned, as opposed to extreme values considered by prevalent test techniques. In this research, we show that there exist ranges of short defect resistance values that escape traditional DC tests while incurring unexpectedly large delay values for specific two-pattern stimuli. It is seen that these resistance values are approximately in the range of defect resistance values observed for realistic short defects in industry. These defects must therefore be prioritized from a circuit level critical path delay testing perspective to minimize overall circuit DPPM. Such catastrophic increase in delay is due to the fact that specific shorts in standard cells influence the delays of logic gates feeding into and out of the standard cell, resulting in path delay increase of 50X-SOX with respect to the delay of a single cell. Two-pattern tests are derived for such faults and simulation results on standard cell designs and ripple carry adders are presented to further our arguments.

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on-shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.

The recycling of used integrated circuits (ICs) has raised serious problems in ensuring the integrity of today’s globalized semiconductor supply chain. This poses a serious threat to critical infrastructure due to potentially shorter lifetime, lower reliability, and poorer performance from these counterfeit new chips. Recently, we have proposed a highly effective approach for detecting such chips by exploiting the power-up state of on-chip SRAMs. Due to the symmetry of the memory array layout, an equal number of cells power-up to the 0 and 1 logic states in a new unused SRAM; this ratio gets skewed in time due to uneven NBTI aging from normal usage in the field. Although this solution is very effective in detecting recycled ICs, its applicability is somewhat limited as a large number older designs do not have large on-chip memories. In this paper, we propose an alternate approach based on the initial power-up state of scan flip-flops, which are present in virtually every digital circuit. Since the flip-flops, unlike SRAM cells, are generally not perfectly symmetrical in layout, an equal number of scan cells will not power-up to 0 or 1 logic states in most designs. Consequently, a stable time zero reference of 50% logic 0s and 1s cannot be used for determining the subsequent usage of a chip. To overcome this key limitation, we propose a novel solution in this paper that reliably identifies used ICs from testing the part alone, without the need for any additional reference data or even the netlist of the circuit. Through scan testing of the IC, we first identify a significant number of asymmetrically stressed flip-flops in the design, divided into two groups. One group of flip-flops is selected such that it mostly experiences the 1 logic state during functional operation, while the other group mostly experiences the 0 state. The resulting differential stress during operation causes growing disparity over time in the number of 0s (and 1s) observed in these two groups at power-up. When new and unaged, these two groups behave similarly, with similar percentage of 1s (or 0s). However, over time the differential stress makes these counts diverge. We show that this changing count can be a measure of operational aging. Our simulation results show that it is possible to reliably detect used ICs after as little as three months of operation.

Traditional low cost scan based structural tests no longer suffice for delivering acceptable defect levels in many processor SOCs, especially those targeting low power applications. Expensive functional system level tests (SLTs) have become an additional and necessary final test screen. Efforts to eliminate or minimize the use of SLTs have focused on new fault models and improved test generation methods to improve the effectiveness of scan tests. In this paper we argue that given the limitations of scan timing tests, such an approach may not be sufficient to detect all the low voltage failures caused by circuit timing variability that appear to dominate SLT fallout. Instead, we propose an alternate approach for meaningful cost savings that adaptively avoids SLT tests for a subset of the manufactured parts. This is achieved by using parametric and scan tests results from earlier in the test flow to identify low delay variability parts that can avoid SLT with minimal impact on DPPM. Extensive SPICE simulations support the viability of our proposed approach. We also show that such an adaptive test flow is also very well suited to real time optimization during the using machine-learning techniques.

Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today's very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation-and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC'99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.

Opens are known to be one of the predominant defects in nanoscale technologies. Especially with an increasing number of complex cells in today's VLSI designs intra-gate opens are becoming a major problem. The generation of tests for these faults is hard, as the timing of the circuit needs to be considered accurately to prevent the invalidation of the generated tests through hazards. Current test generation methods, including new cell aware tests that explicitly target open defects, ignore the possibility of hazard caused test invalidation. Such tests can fail to detect a significant fraction of the targeted opens. In this work we present a waveform-accurate hazard-aware test generation approach to target intra-gate opens. Our methodology is based on a SAT-based encoding and allows the generation of tests guaranteed to be robust against hazards. Experimental results for large benchmarks mapped to the state-of-the-art NanGate 45nm cell library including complex cells show the test generation efficiency of the proposed method. Large circuits were efficiently handled - even without the use of fault simulation. Our experiments show that on average, about 10.92 % of conventional hazard-unaware tests will fail to detect the targeted opens because of test invalidation - these are reliably detected by our new test generation methodology. Importantly, our approach can also be applied to improve the effectiveness of commercial cell aware tests.

The European Test Symposium (ETS) Best Paper Award, which was introduced in 2004 when the European Test Workshop (ETW) turned into the ETS, aims to maintain and encourage the quality of papers and presentations in the ETS technical program.

Localized small delay defects, for example due to degraded transistor drive strength caused by a broken fin, are a growing concern in current FinFET and emerging gate all around (GAA) technologies. Such defects are currently targeted by timing-aware Transition Delay Fault (TDF) tests that aim to test the target nodes along the longest path. The resulting tests often require considerable test generation time, have high test data volume, and at times do not provide the desired coverage. In this paper, we show that Path Delay Fault (PDF) test generation can be exploited to not only generate the timing tests more efficiently, but the resulting TDF test sets are also more compact and perform better on commonly used delay test coverage metrics. This is because all TDF faults along a PDF targeted timing-critical path can be detected efficiently by generating a single PDF test. This efficiency is not explicitly exploited by node oriented TDF test generation even when the TDFs are targeted along the longest paths. We demonstrate the effectiveness of our methodology for a range of benchmark circuits by comparing the results from a commercial timing-aware ATPG (TA-ATPG) with our new approach that efficiently exploit PDF tests wherever possible. The proposed new approach results in approximately 12.5% reduction in pattern volume, 35% reduction in ATPG runtime and also a 5% improvement in delay test coverage (DTC) when compared to existing TA-ATPG approaches.

With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. This is because CMOS circuits experience a large number of hazards during circuit inputs switching which are not modeled by classical tools. Hazards may activate some TSO faults considered untestable by classical ATPGs. The generation of tests that target such hazard activated opens can result in a very significant DPPM improvement - if used. In this paper, we present the first deterministic methodology for targeting hazard activated opens. It is based on a waveform-accurate SAT-based modeling and allows to accurately determine if a TSOF is detectable by hazard activation - or not. In addition, we provide a thorough investigation of the additionally achievable fault coverage using the state-of-the-art NanGate 45nm as well as NanGate 15nm cell libraries.

Due to the prohibitive costs of semiconductor manufacturing, most system-on-chip (SoC) design companies outsource their production to offshore foundries. An untrusted foundry can manufacture and sell additional unauthorized chips for profit in violation of their contract. This overproduction can not only cause significant loss of revenue to the designer, but may also have national security implications in case of sensitive designs. Over the years, researchers have proposed different design obfuscation techniques by modifying the underlying functionality to prevent this unauthorized overproduction of chips. An untrusted foundry/assembly cannot sell chips unless they are activated. A chip works properly only when it is activated with a key, which needs to be kept secret from any adversary. However, Boolean satisfiability (SAT)-based algorithms have shown to efficiently break key based obfuscation methods. In this paper, we present a novel secure cell design for implementing design-for-security (DFS) infrastructure to prevent of leaking the key to an adversary under any circumstances. Importantly, our design does not limit the testability of the chip in any way, including post-silicon validation and debug.

Physically Unclonable Function (PUF) circuits are designed to provide part-specific responses that are random across different copies of the circuit by exploiting the unavoidable process variations in nanometer scale fabrication. This property can be used as an important building block in security and cryptographic applications including key generation and challenge-response authentication. A major problem, however, is to ensure PUF response stability and reliability in the presence of circuit and environmental noise. SRAM based PUFs are most promising in this regard but still require extensive output error correction because the response of many cells in the memory array is not consistent. Unfortunately, all such "weak" cells cannot be determined in advance to allow their unstable responses to be masked out. In this paper we present a new SRAM PUF design that allows all the unstable weak cells to be reliably identified over the full range of operating conditions including temperature, electrical noise, and aging. By using the remaining "strong" cells, each instantiation of our SRAM PUF provides the same consistent and repeatable response every time it is challenged, without any need for error correction. Experiments reported here show that relatively few (of the order of 10%) SRAM PUF cells are truly stable in the presence of realistic circuit noise; in addition to the expected noise level, this number also depends on the random variability in the manufacturing process. Our simulation results show that the new SRAM PUF can be designed to maintain good robustness against any level of expect circuit and environmental noise, and is resilient to aging.

Cell Aware testing (CAT) has received much publicity in recent years, with several reported success stories in screening defects missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Significant additional fallout from cell aware tests has also been reported for automotive parts already screened to stringent “zero-defect” standards. Importantly, the vast majority of these test escapes were observed to cause failure in actual system application, pointing to a serious field reliability issue. This raises some important questions: What are these new defects that are being detected by cell aware tests? Why are they missed by traditional stuck-at and TDF testing? Why has this problem only recently been discovered? Can traditional cell unaware test generation be enhanced to detect these faults? This tutorial presents a detailed study of the cell aware test generation methodology to answer these questions. The aim is not only to analyze and understand the defects in modern standard cell libraries missed by traditional tests that are uniquely covered by this new test approach, but also which of these test escapes necessarily need cell layout information for detection, and which can be systematically targeted in a layout unaware manner by enhanced stuck-at and two-pattern test generation. The large majority of the additional fallout from cell aware tests appears to be from the delay patterns that primarily target open defects. However, the structural limitations of scan DFT can limit the detectability of open defects even with CAT. Commonly employed LOC delay tests are not sufficient to screen all open defects capable of generating erroneous circuit outputs. We show that hazard activated open defects are the likely causes of at least some of the failures being observed in system level tests (SLT) even after parts are screened with CAT.

In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.

In some complex deep sub-micron designs, the variations in interconnect delay has a significant impact on the production yield of the product. In this paper, we develop a theoretical explanation for the unexpectedly higher process related timing variability shown by long interconnects that are driven by high drive strength gates. This gets even worse due to conventional gate delay variability and other random process effects. Our analysis is supported by actual silicon data and further validated by detailed Monte-Carlo (MC) simulations. Unfortunately, traditional scan based transition delay fault (TDF) timing tests can miss these variability induced delay faults on long interconnects which lies on the critical paths. We propose a methodology to identify high variability paths dominated by such long interconnects, with the aim of developing high quality delay timing tests. Specifically, we develop a heuristic based path selection algorithm to identify potentially slow paths that can contribute to test escapes in production. We further extend our approach to generate high quality delay timing tests for the target paths using the proposed "three pass" method.

The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in circuits implemented from primitive logic gates, they do not model a type of open fault found only in complex CMOS gates. We refer to these as cross wire open (CWO) faults. In this paper, we develop the first tests that target CWOs. Although we observe that the fault list of potential CWOs can be significantly reduced if the layouts of complex gate cells used in the design are available, we present test generation methodologies both with and without this layout information. CWO fault coverage results for scan based tests are presented for ISCAS89 and ITC99 benchmark circuits that have been resynthesized using an open source cell library containing complex gates.

Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances of internal circuit nodes that have been tapped for node controllability and observability by malicious circuitry. Current path delay measurement and side channel Trojan detection techniques are unable to detect Trojans that present low loading to such tapped circuit nodes, especially in the presence of large manufacturing process variations. In this paper, a high-resolution Trojan detection method for digital logic based on pulse propagation is developed. The method exhibits 25X -- 30X higher diagnostic resolution (ability to measure small capacitive loads on internal circuit nodes) as compared to current path delay based Trojan detection techniques in the presence of significant manufacturing process variations. Further, a key benefit is that theoretically, as opposed to path delay measurement based methods, the diagnostic resolution of the test approach is independent of circuit logic depth over and above the benefits already mentioned above. Test methods and test infrastructure compatible with existing scan based techniques are described. Simulation results are presented to prove the viability and effectiveness of the proposed Trojan detection scheme and especially for circuits with large logic depths (35-70 gates) suffering from worst case process variation effects.

Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant fraction of the timing defects, including many unique failures that are missed by LOC test. This suggests the use of combined LOC and LOS test to increase the TDF coverage beyond that attainable by LOC tests alone. However, to maximize the detection of real delay defects, the LOS tests must be applied at the fastest possible speed (up to the functional clock rate) within the timing limitations of the scan enable. To support such testing, in this paper we present the first test technique to reliably evaluate the switching speed of the scan enable signal. This can vary significantly for individually manufactured instances of the same design due to normal process variations at advanced technology nodes, amplified by near quadratic delays in the long interconnect lengths of this broadcast signal. Once the scan enable speed is determined, LOS tests can be applied at the fastest, most effective speed. Furthermore, the availability of this effective low cost LOS test capability also facilitates the partitioning of the scan flip flops through the use of multiple scan enable signals that apply the delay test in mixed LOS and LOC modes in the different partitions. We show that the use of only two scan enable signals in such an approach can significantly increase TDF test coverage, and raise it very close to the highest possible that is achievable only by enhanced scan.

The rapidly increasing variability in circuit performance in highly scaled technologies has given rise to novel “better-than-worst-case” circuit design methods. They aim to overcome worst-case clock timing requirements by employing a shorter clock period and allowing occasional errors to occur; these are detected and recovered from by low-cost error detection and correction techniques. We investigate conditions under which timing error detection based on the memory element duplication with delayed capture is reliable even under extreme variations, where the key problem arises from short-path invalidation mechanisms. We consider two known mitigation techniques: buffer padding and latch placement. The derived conditions can yield the interval of clock periods within which an adaptive frequency scaling strategy may reliably operate. We show that buffer padding is impossible if variability exceeds a certain limit, but latch placement always yields a solution, works for more clock frequencies, and tends to incur less area costs, at the cost of clock power.

Better-than-worst-case timing design methodologies aim at increasing throughput by speeding up the clock to the point where circuit timing margins are reduced to zero and even beyond. In low power designs such as Razor, this efficiency improvement is translated into power savings at a fixed operational clock rate through adaptive and dynamic voltage scaling. The main challenge in such designs is the development of efficient mechanisms to detect and recover from the occasional timing errors that can occur. We survey recently published designs in this domain with a special focus on the error detection and recovery approaches employed. Experimental prototype processors implemented by ARM and Intel are also discussed.

Open defects in CMOS circuits can cause a gate output to go into a high impedance, or “floating” mode, for some input patterns. Since such defects display (large) delay fault behavior, they are commonly assumed to be covered during structural testing by scan based TDF timing tests. TDF tests are generally applied in the launch-on-capture (LOC) scan test mode to avoid “overtesting” the circuit timing from non-functional launch states; also many designs do not support a high speed scan enable to allow at-speed launch-on-shift (LOS) timing tests. Unfortunately, launching timing tests from functional states alone, or even LOC states (which are a superset of functional states), is not sufficient to screen all open defects capable of generating erroneous circuit outputs. CMOS circuits experience a large number of hazards during switching transitions, which result in many more transient logic levels at internal circuit nodes than those predicted by steady state analysis from functional states. Such hazards can activate open defects by precharging a faulty gate output to an incorrect value which is then locked in once the inputs stabilize with the gate output in a high impedance state due to the open. Consequently, many open defects that are commonly assumed to be functionally redundant based on steady state analysis, can in fact be activated in operation and cause circuit failure. These must be targeted during manufacturing tests. In this paper we present a deterministic methodology for targeting hazard activated open defects using not only LOC and LOS tests, but also a new DFT approach that further increases the available test launch states to achieve high coverage. We further show that virtually all of the remaining undetected opens are in fact truly redundant, and do not pose a threat even in the presence of hazards.

Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic values through the charging of the floating node by small leakage currents in the circuit, although with large delays. It is well known that many open defects are not covered by commonly employed TDF launch on capture (LOC) scan delay tests; the coverage of specially generated transistor stuck-open tests published in the literature is only modestly better. It is commonly assumed that such undetected open faults are benign because the circuit states needed to activate them cannot be reached in normal functional operation. However, traditional test generation only considers final “steady state” signal values and ignores transients. In practice CMOS circuits experience many more transient states from the large number of hazards that occur during switching transitions. Many undetected open defects can be activated by such hazards during normal operation and cause a functional error. Such open faults must be detected by tests targeting low DPPMs. In this paper we present an ATPG based delay test methodology to target a key class of such hazard activated open faults that are not detected by traditional stuck open tests. Through detailed SPICE simulations, we show that the detected open defects can in fact be activated by such tests and therefore result in erroneous outputs in normal functional operation.

Hazards have been known to have the potential to invalidate tests for stuck-open faults in CMOS circuits. In this paper we show that hazards can also predictably allow the detection of stuck-open faults that may be undetectable by traditional TDF launch-on-capture (LOC) scan delay tests. Importantly, the detected open faults are not redundant, and can in fact be activated in normal functional operation leading to functional errors. We identify such defects in benchmark circuits and present a LOC test selection method capable of predictably detecting the open defects through initialization by a hazard.

Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass (Fairchild Semiconductor) planted the first seeds of using current testing as part of a structural approach to validate integrated circuits when publishing the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby; it would draw practically nothing — just the leakage current. It was therefore a fact that CMOS circuits with increased standby power consumption were defective. In 1981 Mark W. Levi demonstrated the concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) in his ITC'1981 paper “CMOS is most Testable”. This paper kicked off a lot of research on IDDQ fault modeling, IDDQ defect detection capabilities, IDDQ and reliability, IDDQ efficiency. Much of that research happened in the late eighties — early nineties by “Chuck and Jerry”, exploring the benefits, followed by studies done by HP, IBM, TI, Philips, Alcatel, Ford Micro, … Since then IDDQ testing became synonym to current testing. Extensive research revealed the IDDQ capabilities. Despite its demonstrated defect detection capabilities and screening efficiency, it was not an easy way for IDDQ to make it to the production test floor. The initial lack of commercial available ATPG tools and suitable measurement solutions were the hurdles to take.

Devices manufactured in 20 nm and smaller geometry technologies will potentially be very large by today's standards, they will also have new characteristics implied by things like process variability and adoption of FinFET transistors. The industry has cumulatively adopted more and more sophisticated fault models that use timing as well as layout information. There is a growing body of experimental data showing it is still insufficient. The next area of focus will be the quality of test. Cell-aware test is one of the most promising approaches developed over the last five years aimed at improving the quality of test while maintaining the efficiency of gate-level approach. This approach combines two levels of abstraction to provide trade-offs between accuracy and efficiency. The first step creates the cell-aware test library models. It starts with standard cell libraries and performs layout extraction. Realistic defects (bridges and opens) are injected into the SPICE netlist, and analog fault simulation is performed to determine the conditions under which the defects are detected. Those conditions are aggregated to create a compact and efficient representation of the libraries for ATPG done at the gate-level. Generation of library views for cell-aware test is performed only once for a given standard cell library. The final cell-aware ATPG generates the high quality test patterns based on the cell-aware library views. This guarantees that the investment in gate-level ATPG infrastructure could be efficiently utilized. The technology has been used on a number of high-volume industrial designs. The experimental data show a significant increase of defect coverage and the corresponding improvement of defect rate.

Start of the "Special session 4B: Elevator talks" section of the conference record.

The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Qcritof a standard 6T SRAM cell.

In this paper, we focus on the detection of small gate-oxide defects, which can escape production tests but lead to early-life-failures (ELF) during normal operation. Very-Low-Voltage (VLV) and MinVDD testing have been proposed in the past to screen such “weak” ICs. However, small defects that are not severe enough to trigger logic failures can still escape such tests given the fact that power supply voltage cannot be arbitrarily lowered in a given technology. We suggest a novel approach for increasing the sensitivity of detection of these small gate-oxide defects by applying timing tests in a reduced power supply environment. While not severe enough to cause logic failures, small oxide defects can still introduce observable anomalies in the timing of affected paths, which is amplified at reduced power supply voltages. Experimental simulation results using NanGate 45nm technology are provided to substantiate our conclusions.

Exhaustive speed testing of all the cores under extreme inter and intra-die process variations in a large chip multi processor (CMP) is expensive in terms of test time and may not guarantee full CMP functionality due to lack of coverage of timing failures induced by second-order effects such as cross talk, power/ground bounce and speed-limiting design bugs that are not "caught" by relevant combinatorial design verification algorithms. The goal of this research is to develop a methodology that allows the "safe" speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures. Accordingly, baseline speeds using conventional tests are determined for each CMP core using a comparison based speed-tuning algorithm. To prevent "blue screens" from any test escapes, relevant applications are then run on the CMP in "fail-safe/redundant" mode to "top-up" speed-defect coverage. Over a period of time, using a concurrent tuning algorithm, the true "safe speeds' of all the cores are determined in O(log(Fp)) steps, independent of the size of the array, where Fp is the number of discrete clock speeds possible. Subsequently, each core is run "independently" at its highest "safe' clock speed achieving maximum possible CMP performance.

End-of-road map CMOS (<;=10nm) technology is expected to display extreme random variability in device parameters, resulting in a very large spread in the speed of individual gates. Based on reasonable statistical estimates, virtually every large circuit in this environment can be expected to contain several extremely slow statistical outlier gates which will severely limit performance in synchronous designs. To address this challenge, gate level tuning techniques have recently been proposed [2] that can potentially speed up the slow gates to recover much of this lost performance. However, such tuning significantly increases power dissipation, and therefore must only be activated in the relative few performance limiting outlier gates. Consequently, application of such tuning techniques requires that the slow outlier gates be correctly diagnosed for proper tuning. This presents the challenging problem of diagnosing multiple delay faults in the circuit. In this paper we show how the performance tuning capability of the circuit can itself be exploited, in combination with scan delay tests, to address this problem. Our approach involves selectively tuning and speeding up subsets of suspect gates, and then uniquely identifying the slow outlier gates based on whether the tuning eliminates the slow path or not. We show that such an approach can correctly diagnose multiple slow gates in large circuits for successful performance tuning.

Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal signals of a chip. However, this property also facilitates hackers to use scan architecture as a means to breach chip security. This paper addresses this issue by proposing a new method called Secure and testable Scan design through Test Key Randomization(SSTKR). SSTKR is a key based method to prevent hackers from stealing secret information. Linear Feedback Shift Register (LFSR) is used to generate authentication keys to be embedded in test vectors. Unique key is used for every test vector which prevents scan based side channel attacks effectively. Any attempt to steal secret information will lead to a randomized response. SSTKR has very low area and test time overhead without performance penalty. Our approach also facilitates in-field test of the chip.

Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal operation. In this paper, we propose a modified design of a scan flip-flop which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on performance. The new scan flip-flop disables the slave latch during scan, and uses an alternate low cost dynamic latch in the scan path instead. Methods for generating slave latch disable control signal are also presented.

As technology scales, resistive defects, particularly via voids, are becoming an increasing problem. While such defects may only cause a small timing increase along some signal paths during test, they often grow and lead to early life failures in the field. Testing for small delay defects is therefore receiving considerable attention in recent years because the traditional burn-in approach to screen out such “infant mortality” failures is becoming prohibitively expensive in nanometer scale technologies. Unfortunately, random process variations can give rise to variability in circuit timing comparable to the resistive delay faults being targeted. This makes it critical to distinguish between the two so as to avoid discarding slow parts that are not reliability risks and can in fact be appropriately speed binned and safely used. In this paper we present a innovative strategy to show how this can be done by observing the relative change to switching delay of the slow path with variation in the power supply voltage. Our proposed approach exploits a novel key observation that the relative delay contribution of a performance outlier transistor increases noticeably with decreasing VDD, while the relative delay contribution from resistive delay defects decreases with increasing VDD.

Adaptive testing is a generic term for a number of techniques which aim at improving the test quality and/or reducing the test application costs. In adaptive tests, the test content or pass/fail limits are not fixed as in conventional tests, but dependent on other test results of the currently or previously tested chips. Part-average testing, outlier detection, and neighborhood screening are just a few examples of adaptive testing. With this Embedded Tutorial, we are offering an introduction to this topic, which is hot in the test community, to the wider DATE audience.

Testing using a random access scan (RAS) design-for-test approach is experiencing renewed interest because of the potential for lower test application time, low power dissipation, and low test data volume compared to standard serial scan. In this paper we propose a significant modification and enhancement to the T-Flip-Flop based cell design for Random Access Scan (RAS). Importantly, the new RAS cell can allow the overlap of the test response read out with the loading of the next test input patterns within the same memory addressing cycle, thereby masking out the need for a separate memory cycle to read the test response in many cases. This can greatly reduce test application time. Experimental results show that the Modified T-Flip-Flop based scan cell is able to mask about 33% to 76% of reads. Further, this new RAS cell also eliminates the need for clock gating and additionally achieves reduction in gate overhead as much as about 20% compared to the existing T-flip-flop based RAS cell design.

Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random "care" bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.

Faster-than-rated clock delay tests aimed at targeting small delay defects can generate a large number of unknown X values because the test response for all paths longer than the (over clocked) test clock period must be marked X. Current test compression techniques cannot efficiently handle such a large number of X responses. We propose a simple multiplexing scheme for output test data compression which avoids any compaction of the test response. Just as input test compression techniques take advantage of the fact that there are only a small number of ¿care¿ bits in the ATPG generated test inputs, our new approach leverages the fact that not all the output bits in the captured test response need be observed. In most cases, observing only selected 2-5% of the test response bits captured in the scan chains can still result in the same target test coverage as when all output bits are observed, albeit at the expense of requiring some additional TDF delay test vectors. Since no test result compaction is performed, the new approach is capable of handling an unbounded number of X-states during aggressive delay testing. Experimental results show that test time/data volume reduction of 10X or better appears viable.

In this paper, an architectural framework for post-silicon tuning of nanoscale CMOS circuits is developed. The tuning methodology is driven by a ¿tunable¿ gate design that allows the gate to be switched from a high-speed/high-power mode to a low-speed/low-power mode under digital control. A small number of ¿critical¿ logic gates are replaced with tunable gates for post-silicon power-performance tuning. In addition, supply voltage and body bias can be employed as hardware ¿tuning knobs¿ as well to deal with delay and leakage variations. After silicon is manufactured, the hardware ¿knobs¿ are programmed through the use of an implicit self-test methodology that can be exercised by the proposed self-adaptation architectural framework. It is seen that the delay yield can be improved by an average of 40% with minimal impact on area.

Enhanced scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial enhanced scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS'89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.

There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that errors do not impact the Quality of Service of the end application or to allow errors to occur and correct them using error tolerance mechanisms. Specific signal processing algorithms have been shown to be inherently tolerant to errors. However, large general purpose processors experience virtually zero errors under supply voltage scaling up to a certain scaling level and then exhibit “massive errors” or “complete breakdown”. The problem is made worse by the fact that low power design methodologies force devices to be sized in such a way as to make a large number of circuit paths “critical”. Under all of the above constraints, what is the best way to build low power systems of the future using deeply scaled CMOS technologies? Is the use of voltage overscaling along with error resilience techniques realistic? Can we allow errors to occur and compensate for them with high confidence? Under what conditions will design guardbanding be absolutely necessary? If we do let errors occur periodically, will customers buy the associated products and is there a marketplace for such error-resilient ICs?

Scan based timing comparison tests offer a potential solution to the problem of small delay detection in aggressive nanometer technologies. However, such tests require that circuit delays be unambiguously captured in the scan chains using multiple fast clocks. To ensure this, only those signals that are known to be hazard free at capture are analysed for timing information from the scan-out data. In this paper we present the first systematic ATPG driven approach for generating high coverage output hazard free TDF tests for scan delay testing. Results indicate that acceptable coverage can be achieved, no worse than about 10% below the unconstrained TDF coverage for both LOS and LOC tests, even in the presence of significant process variations.

We present a new structural delay test methodology that identifies small timing anomalies in dual/multi core processor circuits by comparing the relative switching time of identical circuit paths in the multiple cores. A difference in switching delay beyond the statistically observed worst case within-die timing variation indicates a defect. The proposed test is purely a comparison test between identical cores to detect manufacturing defects and does not measure absolute circuit timing. Common mode noise effects such as power supply droop, clock stretching, etc. are automatically compensated and do not impact the test results. Furthermore, the test response can be captured at multiple sample times, including faster than the rated clock period to target small delays on short paths. We present a practical approach for implementing such a test that alternately uses one core as a timing reference to test for delays in another identical core using slightly different capture clocks to allow for normal intradie parameter variations. Test results are obtained in real time without the need for any post processing. Early experimental results show good potential for this new technique.

Enhanced scan designs support high coverage TDF testing but with significant overhead. We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. Experimental results using commercial ATPG tools show that 60-90% of the TDF coverage benefits of enhanced scan can be achieved at 10-30% of the cost.

The Delay Test Scan Flip-Flop (DTSFF) has been recently presented as a low cost DFT technique to achieve both launch-on-shift (LOS) and launch-on-capture (LOC) scan delay tests, without the need for a fast scan enable signal. Such a combined delay test strategy can achieve near perfect transition delay fault (TDF) coverage which eludes commonly supported LOC only delay tests. In this paper we show that a partial DTSFF scheme, which replaces only 20-40% carefully chosen scan flip-flops in the scan chain with the new DTSFF can achieve most of the coverage benefits of a full DTSFF design while minimizing area overhead.

Most scan based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-onshift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but require a fast scan enable. We present a low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge. Our new design is much more efficient when compared to other recent proposals, and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve TDF coverage approaching 95% for the ISCAS89 benchmarks.

Architectural restrictions of scan greatly limit the effectiveness of traditional scan based delay tests. It has been recently shown that additional testing for delays on short paths using fast clocks can significantly lower DPM. However, accurately obtaining the needed timing information for such tests from simulation is extremely difficult. The simulations must not only accurately account for the effects of process parameter variations, but also power supply noise and crosstalk from the excessive switching activity of scan tests. We suggest that learning signal timing information on silicon to "calibrate" such tests can be much more accurate and cost effective. However, such an approach requires that the outputs of the applied tests be hazard free to avoid learning incorrect timing due to a glitch at the output. Simulation results presented here indicate that such output hazard free test can be obtained with an average coverage only about 10% below the transition delay fault coverage for both launch-on-shift (LOS) and launch-on-capture (LOG) modes.

Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer combinational circuits. The tolerance estimates generated by the tool match SPICE-generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT), which uses the tolerance estimates generated by ASERTA. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation-based optimization methodology, the sizes, supply voltages, and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added capacitive loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our approach has a significantly better energy-delay-reliability tradeoff compared with others.

This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. Specially designed test chips were designed and tested to verify the applicability of the methodology. Simulation studies were also conducted to investigate the effectiveness of the technique. The results presented here clearly establish the significant potential of the proposed new delay testing approach

Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose a scheme to reduce the power consumption of combinational domino logic blocks while maintaining the performance. We replace the PMOS precharge transistor with an NMOS transistor to reduce the overall power consumption of the gate at the expense of higher delay. We use a heuristic algorithm to replace the fast, high power gates on the off-critical paths with slower, low power gates while maintaining the circuit performance. Our technique reduces dynamic energy of ISCAS'85 circuits by 16.25%.

VLSI circuits have been traditionally tested individually following manufacture; the same tests being applied to all ICs. However, as manufacturing test costs continue to show a disproportionate increase in relation to IC fabrication costs, innovative new statistical methods are being introduced to optimize testing. Such methods fall into two broad categories: those that exploit statistical information in regard to the variation of process parameters on wafers, and those that exploit the statistics of defect distributions on wafers. This tutorial presents test methodologies that span both these categories and illustrate their effectiveness with experimental results from a number of recent studies on production circuits from LSI Logic, IBM, Intel and TI

For nanometer designs, many subtle defects lead to excessive delays in signal paths that cause reliability concerns. Traditional test-based diagnosis methods can only identify the failing nodes without the capability to tell the defect nature behind the observed delay faults. This differentiation is important for gathering accurate defect statistics for process improvement during yield ramp-up. In this paper we presented an effective delay defect analysis methodology that can quickly categorize the delay defects into either transistor related defects or resistive interconnect defects. The new delay defect/failure characterization method is based on low voltage test and delay defect detection in slack interval (DDSI) method. Experimental results were presented to validate the effectiveness of the new method. Practical considerations were also addressed for adoption of the methodology.

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. In this paper, the problem of leakage power variation minimization in the presence of spatially correlated across-die process variations is addressed. It is shown that with minimal impact on delay, the placement of low-Vt gates in a layout can be performed in such a way to maximize the yield for a specified leakage power upper bound. For the obtained placement of low Vt gates, the layout can then be optimized for other important criteria such as wire length. Simulation of across-die variations for ISCAS benchmarks is performed and guidelines for distributing the low-Vt gates across the die are developed.

In this paper we propose architecture for random access scan (RAS) that minimizes the signals to the RAS flip-flops (FF), and provide an estimate of the area overhead. Two global signals, scan-in and mode control, have been eliminated compared to previous RAS designs presented in the literature. For 'n' flip-flops, instead of routing 'n' address wires, one to each FF, we use /spl radic/n wires in an 'x-y' matrix layout. A unique toggle mechanism is introduced in the RAS FF that eliminates the scan-in signal wire and reduces the vector set up time to 60% compared to traditional serial scan (SS). Serial scan induces unnecessary circuit activity during scan that causes the circuit under test (CUT) to dissipate a significant amount of power. Our design reduces this power dissipation by 99%. The problem of delay testing is highly constrained in SS and the scan-cell is often modified to assist delay testing. Any single input change delay test can be directly applied in our design. Hence all testable paths in the circuit can be effectively tested without constraints. We also propose a multistage scan-out system to observe the addressed FF avoiding a slow output bus.

We present a new structural self-timed delay test methodology that identifies timing anomalies in the circuit by comparing the relative switching time of the different signal lines feeding the scan chains. These are observed by capturing the circuit's response to a delay test at multiple sample times, at and below the design cycle time. A timing defect is detected if there is a reversal in the switching order of any two outputs from that reliably predicted by simulation (or measurement on golden circuits), while allowing for processes variations

Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.

A new delay-testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. The simulation showed orders of magnitude delay defect detection efficiency improvement. In this paper we investigated the yield loss problem and proposed a practical production test based on delay defect detection in slack interval (DDSI).

Based on reliability simulation and reliability hotspot identification with simulator ARET, a concept of local design-for-reliability is proposed and a detailed redesign algorithm has been developed for CMOS digital circuits under device degradation mechanisms, such as hot-carrier and gate oxide wear-out. This algorithm improves circuit overall reliability by modifying channel length of hotspot gate and channel widths of some other gates around hotspot iteratively. By performing local redesign for reliability, circuit reliability can be significantly improved, while the originally designed overall circuit performance is still maintained.

A new delay testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. We evaluate the effectiveness of this new approach through the simulation of injected delay faults in the ISCAS benchmark circuits. The simulations are performed using a simple switched RC (resistor-capacitor) switching delay model. The results indicate that the new delay testing approach is orders of magnitude more effective in detecting and diagnosing smaller delay defects that increase circuit path delays by 10-50%. The new methodology can address increasing concerns that failure to detect such small delay faults during test may be the cause of significant unreliability in emerging nanometer technologies.

To accomplish effective IC reliability evaluation and design-for-reliability (DFR), a reliability, simulator ARET was developed at Georgia Tech. ARET simulates IC reliability at both component and system levels. It also handles the ICs with physical defects generated in fabrication by a statistical approach. ARET was verified by a series of stress tests conducted at The Boeing Company, which has shown a promising accuracy. In order to perform a practical DFR, another distinct feature - reliability hotspot identification was developed in ARET. By sensitivity analysis, it can determine the weakest components in the circuit under certain failure mechanisms, which allows a local design update to obtain an improved IC reliability. This makes DFR feasible by saving huge amount of work that needs to be performed in a complete VLSI circuit re-design for reliability.

Escapes from manufacturing test: A large system built out of well-tested components can still have a significant probability of failure due to test escapes. Unfortunately field testing is unlikely to detect such failures because manufacturing tests, carried out on individual parts and on assembled (sub)systems, are far more comprehensive. Indeed, any proposed field test can be applied as part of manufacturing tests, but reapplying all manufacturing tests is generally not possible in the field. Thus it is unrealistic to expect a significant number of manufacturing test escapes to be picked up by subsequent field-testing, unless the defects “grow” in the field and cause additional malfunction. Concurrent test methods, such as self checking, on the other hand, can be effective here since they can detect errors for input conditions not observed during test.

Built-in self-test (BIST) is an attractive design-for-test methodology for core-based SoC design because of the minimal need for test access when tests are generated and evaluated within the core itself. However, the scan based logic BIST approach being widely considered for this application suffers from two significant weaknesses: slow test-per-scan execution, and a limited capability for detecting realistic timing and delay faults, critical in deep submicron technologies. The new multimode scan based approach presented here supports test-per-clock BIST, which runs orders of magnitude faster, and also provides significantly better delay fault coverage.

The integrated yield-reliability model for integrated circuits allows one to estimate the yield, following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures, and defects causing infant mortality failures. The 2-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields, is shown, for the first time, to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ appreciably from calculations that ignore clustering. This is particularly apparent when wafer probe yields are low, and clustering is high.

This paper validates an integrated yield-reliability model for redundant memory using yield and stress test data from a 36 Mbit SRAM memory chip and an 8 Mbit embedded DRAM chip. In both cases, those chips determined functional following wafer test and repair were subjected to voltage stress and burn-in. It is shown that the yield-reliability model can accurately model not only the fraction of die with 0, 1, 2, ... repairs, but also predict the number of stress test failures for a die with a given number of repairs. Because defects in integrated circuits tend to cluster, it has been suspected that repaired die have a greater chance of containing early-life reliability defects than die with no repairs. Repaired die should therefore be more likely to fail stress tests than die with no repairs. This work presents the first experimental validation of these statements. In particular, experimental results indicate that, as predicted by the yield-reliability model, the stress test failure probability is linearly related to the number of repairs; the slope of this line is intimately related to the degree to which defects cluster over the wafer. Model predictions are in excellent agreement with observed data.

An integrated yield-reliability model is verified using burn-in data from 77,000 microprocessor units manufactured by IBM Microelectronics. The model is based on the fact that defects over semiconductor wafers are not randomly distributed, but have a tendency to cluster. It is shown that this fact can be exploited to produce die of varying reliability by sorting die into bins based on how many of their neighbors test faulty. Die that test good at wafer probe, yet come from regions with many faulty die, have a higher incidence of infant mortality failure than die from regions with few faulty die. The yield-reliability model is used to predict the fraction of good die in each bin following wafer probing as well as the fraction of failures in each bin following stress testing (e.g. burn-in). Results show excellent agreement between model predictions and observed data.

In this paper a systematic scan-path design with duplicated and inverted duplicated memory elements is proposed. Contrary to a known solution (Raina et al., 2000), no additional control lines for additional multiplexors are needed. Full controllability and observability of the proposed scan-path is demonstrated.

Integrated circuits can exhibit significant early life or infant mortality failures. Methods to estimate and/or reduce the number of such failures are therefore of great interest to industry. Applications employing multi-chip modules (MCMs), where several die must be independently reliable, are particularly vulnerable to early life failures. Maximizing the reliability of each die is therefore of significant importance. This paper presents an integrated yield-reliability model that allows one to estimate the number of burn-in failures for repairable memory chips, a common component in many MCMs. Since defects in integrated circuits tend to cluster, memory chips that have been repaired have a greater chance of containing a latent defect than chips with no repairs. The result is a higher incidence of infant mortality failure among memory chips that have been repaired.

Defects have long been known to cluster on semiconductor wafers. Recent research has shown that this fact may be exploited to produce die of high reliability, (i.e. decreased infant mortality), by sorting die into bins based on how many of their neighbors test faulty. Die that test good at wafer probe, yet come from neighborhoods with many faulty die, have a higher incidence of infant mortality failure than die from neighborhoods with few faulty die. Analysis of burn-in results from the SEMATECH test methods experiment suggests that such a binning approach has the potential to isolate a high quality bin that displays very few burn-in failures. This paper presents the first analytical model that quantifies the reliability improvement one might expect when binning die based on local region yield.

In this paper we propose a new method for the design of duplex fault-tolerant systems with early error detection and high availability. All the scannable memory elements (flip-flops) of the duplicated system are implemented as multimode memory elements according to Singh et al. (1999), thus allowing during normal operation the accumulation of a signature of its states in its scan-paths. By continuously comparing a 1-bit sequence of the compacted scan-out outputs of the accumulated signatures of the duplicated systems an error can be already detected and a recovery procedure started before an erroneous result appears at the system outputs when a computations is completed. The accumulation of a signature during normal operation can also be used for debugging at-speed. For this application the system need not be duplicated.

We present the first experimental results to establish that a binning strategy based on defect clustering can be used to screen bare die for early life failures. The data for this study comes from the SEMATECH test methods experiment.

The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with a full scan capability to support custom test vectors, diagnosis, and design debugging. A key feature is the ability to support pseudorandom at-speed delay testing of the functional circuit paths without imposing any performance penalty on the design beyond that for traditional scan. This paper presents a CMOS design for the MSME, and investigates benchmark circuits designed with this memory element. The results show that very high stuck-at and transition delay test coverage can be achieved for most cases using the pseudorandom self-test mode alone. Evaluation of layouts indicates low to moderate area overhead.

This paper introduces a new multimode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the need of any design changes. As in the case of scan, the new element is used in place of regular flip-flops in the design library. Interconnect overhead is comparable to scan with reset. Concurrent with normal operation, the design accumulates a signature of the state variables in the scan-register configured as a multiple input signature analyzer (MISA). Thus virtually complete state observability is achieved without the need of scanning-out the state for each test-input. The pseudorandom states of the MISA can also be utilized as state inputs in circular testing. In this way, most faults are covered in a pseudorandom, "test per clock" mode. Only a few random pattern resistant faults require scan, greatly reducing test application time. Pseudorandom delay testing of the true normally active circuit paths is also possible. Two-pattern tests are supported. Finally, we show that the new memory element can also be used for fault-tolerant design.

Die screening based on the locality of defects has long been informally practised in the industry whereby dice from wafers, or parts of the wafer, that display high defect levels are discarded. More recently this approach has been refined such that test results for neighbouring dice on the wafer are also considered in evaluating test results for a particular die. It has been shown in principle, using negative binomial statistics for defect distributions on wafers, that such an approach can much better optimize test costs and screen for low defect levels in bare dice and packaged chips. In this paper we present, for the first time, experimental test data to demonstrate the effectiveness of this new approach. Our results are based on extensive testing of 4784 dice on 23 wafers from an IBM process. We show that bare die screening based on defect clustering considerations can significantly reduce defect levels in dice that pass wafer probe tests. This approach also has the potential to screen out burn-in failures. Thus it offers new low cost strategies for delivering high quality "known- good" die (KGD) for MCM applications.

We recently proposed a wafer-based testing approach which for the first time employs defect clustering information on the wafer to optimize test cost and defect levels in the shipped product. Preliminary analysis of this approach had implicitly assumed that the probability that a test detects a faulty circuit is independent of the number of faults in that circuit. This assumption may be optimistic. In this correspondence, we study the effect of clustering and test transparency on defect distributions in individual dice, and its impact on the fault detection capabilities of a given test set. We show here that significant defect-level improvements in the shipped product can indeed be achieved by exploiting defect clustering in optimization testing.

IDDQ testing is known to be very effective in detecting shorts in CMOS circuits. It has also been reported that open defects that lead to "floating" transistor gates can also be detected if the gate acquires a sufficient voltage to leak measurable current. Recent experiments evaluating a new on-chip IDDQ sensor indicated the possibility of additional detection mechanisms for other types of open failures, including open source and drain connections. To investigate this in more detail, we designed and fabricated two test chips in CMOS technology containing the 74181 ALU circuit. Our test chips include the capability of replacing, one at a time, individual cells in the 74181 circuits with back up cells that each contain a single open defect. In this way in addition to the fault free circuits, a total of 59 faulty circuits can be configured, each containing a different open defect. It was found that IDDQ testing with random vectors detected 48 of the 59 open defects. Analysis of the experimental data reveals new mechanisms that explain the detection of floating gate and open source and drain failures.

In this paper we present an experimental study on the effectiveness of I/sub DDQ/ testing using the differential built-in current sensor (BICS) circuit. Two new test chips were designed and fabricated implementing a CMOS version of the 74181 ALU chip. In copies of this circuit we included the capability of activating 45 different "realistic" CMOS faults: inter- and intra-layer shorts and opens. We examine the fault coverage of the differential BICS for these realistic faults. A significant finding of our study is that I/sub DDQ/ testing has the potential to detect several classes of "opens". Moreover, these include precisely those open faults for which two pattern voltage tests can get invalidated because of transient switching states.

Distributed self-diagnosis approach proposed for multiprocessor systems is also effective for integrated circuit wafers containing a number of identical circuits. Here the testing of each node is based on the majority voting on the test results from itself and neighboring nodes. In this paper, we identify that the unanimous voting (UV) approach always outperforms the individual voting (IV) approach, irrespective of the number of voting cells and fault rate. Based on the UV approach, the optimal number of tests is obtained. We also introduce an adaptive voting scheme by which the test overhead of the traditional voting schemes can be significantly reduced.>

A scheme for improving test coverage of traditional built-in self-test (BIST) methods through test diversity by combining IDDQ testing with BIST is described in this paper. To support the test diversity approach, the authors present a new differential architecture for built-in current sensing (BICS) which mitigates some of the performance limitations of previous designs and allows at-speed testing for practically-sized circuit partitions. A test circuit incorporating the IDDQ testing elements of the new BIST architecture has been fabricated through MOSIS, using 2.0-micron n-well technology. Results of tests performed on the actual circuit show that it accurately detects all of the test faults implanted in the circuit at speeds of up to 31.25 MHz. The test design establishes the feasibility of incorporating IDDQ testing in a realistic at-speed BIST environment.>

Proposes a wafer based testing approach which for the first time employs defect clustering information on the wafer to optimize test cost and defect levels in the shipped product. Preliminary analysis of this approach had assumed that the probability that a test detects a faulty circuit is independent of the number of faulty dies in the neighborhood of the circuit under test. Here, the authors relax this assumption by making test transparency a function of the number of faults. In this paper they study the effect of clustering on test transparency and defect levels based on maps of particle distributions on test wafers.>

An adaptive testing procedure that uses spatial defect clustering information and the available test results for neighboring dies to optimize test costs for VLSI testing is proposed. For the same average test costs, the approach shows the potential for better than a factor-of-two improvement in average defect levels. Perhaps more significantly, it allows the separation of high-quality circuits with defect levels more than order of magnitude better than the average for the production run. The proposal is orthogonal to all other approaches for improving defect levels and can be combined with them.>

Introduces a new adaptive testing algorithm that uses spatial defect clustering information and available test from neighbouring dies to optimize test lengths during wafer-probe testing. When applied to the defect distribution data for 12 sample wafers collected by Saji and Armstrong, the new approach showed potential for providing improvement in overall product quality. In this paper, the authors conduct a more general study to evaluate the proposed new test optimization algorithm based on the widely accepted negative binomial model for defect distributions on a wafer. The objective is to obtain a more accurate measure of the magnitude of the defect-level improvements that can be expected under various yield and defect-clustering conditions.>

We propose a new adaptive testing procedure that uses spatial defect clustering information to optimize test lengths during wafer-probe testing. For the same average test lengths, our approach shows better than a factor-of-two improvement in average defect levels. It further allows the separation of high-quality dies with defect levels more than an order of magnitude better than the average for the production run. Our proposal is orthogonal to all other approaches for improving defect quality and can be combined with them.

The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone. >

Although a number of defect-tolerance schemes for two-dimensional VLSI/WSI (wafer scale integration) processor arrays have been proposed in the literature, none is efficient enough always to guarantee a restructured array that utilizes all the good processors on the wafer while using only a limited number of interconnection channels. The authors present a restructuring scheme that can achieve this (no matter how severely clustered the faults) with a maximum channel width of three, provided the total number of faults in the array are within some stated limits. For practical size arrays, this limit is large enough so as not be be restrictive in practice. Moreover, the scheme also works extremely well, in a probabilistic sense, for a larger number of faults, when the failed processors are severely clustered.>

The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown that their layouts readily lend themselves to fault-tolerant designs for overcoming fabrication defects in large-area and wafer-scale implementations of binary-tree architectures.>

An efficient scheme is presented for embedding a complete binary tree architecture in a two-dimensional array of processing elements. The scheme utilizes almost 100% of the processing elements in the array as actual computing elements, with small and asymptotically optimal propagation delay. The maximum edge length is optimal for trees with up to six levels. The scheme is compared with other designs proposed in the literature and shown to be significantly better.>

In the proposed scheme, spare PEs are located at interstitial sites within the array. Each spare can functionally replace any one of the neighboring primary PEs that are connected to it. Because spares are physically close to the PE that they replace, restructured interconnections are short, minimizing performance degradation. This structure can incorporate different levels of redundancy depending on how many of the interstitial sites are used to locate spares, and also how many spares are placed at each site. The author gives a polynomial time algorithm for assigning operational spares to failed primary PEs. He also gives area efficient layouts for such structures, and designs for implementing the switching network needed for reconfiguration. A procedure for deciding the optimum level of redundancy so as to maximize chip area utilization is also shown. The main attractive features of interstitial redundancy are short (fixed length) PE interconnections and high utilization of failure-free PEs. The analysis shows that for a wide range of array sizes and PE survival probabilities, 45-55 percent utilization of failure-free PEs on the chip can be achieved.>

A design procedure is presented for realizing multiple-valued sequential logic functions as tree structured networks of sequential universal logic modules (SULM's). Both definite and nondefinite finite state machines can be realized using this approach. The SULM employed is a multiple-valued multiplexer-flip-flop cascade that can be efficiently implemented in multiple-valued technologies.