This paper presents an efficient methodology for FPGA arithmetic design based on Boolean function optimization. Focusing on constant multiplication, modular multiplication and reduction, and division by constants, the proposed approach achieves up to 20× LUT reduction and up to 50% delay improvement compared to Vivado-generated designs. Experimental results also demonstrate competitive area–delay trade-offs relative to FloPoCo, highlighting the effectiveness of the method for high-performance FPGA arithmetic implementations.

As RISC-V ISA continues to gain traction for both embedded and high-performance computing, the demand for advanced monitoring tools has become critical to fine-tuning the applications' performance. Current RISC-V hardware performance monitors already provide basic event counting but lack sophisticated features like event-based sampling, which are available in more established architectures such as x86 and ARM. This paper presents the first RISC-V Event-Based Sampling (RVEBS) system for comprehensive performance monitoring and application profiling. The proposed system builds upon existing RISC-V specifications, incorporating necessary modifications to enable the desired functionality. It also presents an OpenSBI extension to provide privileged software access to newly implemented control status registers that manage the sampling process. An implementation use case based on an OpenPiton processor featuring a CVA6 core on 28nm CMOS technology was presented. The results indicate that the proposed scheme is lightweight, highly accurate, and does not impact the processor's critical path while maintaining minimal impact on overall application performance.

High-order epistasis detection is challenging, making it important to efficiently leverage today's supercomputers.The fastest approaches are those relying on binary precision tensorized operations on modern GPUs.This paper presents a novel approach that significantly surpasses the state-of-theart in high-order epistasis detection by leveraging previously unexplored domain-specific features on the genotype distribution patterns in the dataset.It accelerates time-to-solution with a computational step that reduces the volume of data that needs to be processed to count genotypes.The proposed approach achieves 4× higher performance on a A100 GPU than the previously fastest approach when processing balanced genotype distributions.Evaluation on datasets with unbalanced genotype distributions, which is something that is bound to happen in real datasets, results in significantly higher performance.The proposed accelerating scheme exhibits high scalability.Epistasis detection searches on the MeluXina supercomputer with 32 A100 GPUs resulted in a speedup of up to 30× in comparison to a single GPU, and in achieving a performance scaled to sample size of up to 13 Peta SNP combinations per second for the genotype distribution most unfavorable to the proposed accelerating scheme.

Multi-layer perceptrons (MLPs) are widely used to model complex nonlinear relationships across various applications, but achieving high accuracy while minimizing energy and resource consumption is crucial in resource-limited environments. Computations based on the most significant digit first (MSDF) process digits from left to right, allowing early access to the most significant digits during initial processing. This characteristic enables the early termination of computations once the desired output accuracy is achieved, thereby leading to efficient and cost-effective implementations. This paper explores early termination techniques for applying MSDF computations in the MLP. An ASIC-based MLP architecture is designed to perform serial computations on digits. The efficiency of the proposed MLP design during inference using the MNIST handwritten digit classification dataset is analyzed. Results show that the proposed design achieves a minimum delay and energy consumption reduction of at least 47% while maintaining high accuracy compared to state-of-the-art designs.

ABSTRACT Sparse tensors have become prevalent data structures in multiple applications, such as medical imaging and machine learning, making operations that decompose them, that is, creating smaller structures that retain most of the original information, essential. Two of the most commonly used tensor decomposition methods are the Canonical Polyadic and Tucker Decomposition, with the most time‐consuming operations being the MTTKRP and TTM‐chain, respectively. Modern computing platforms combine multiple devices with different architectures to achieve unprecedented levels of performance, creating an environment where portability is as important as performance. To tackle this challenge, this work proposes SYCL‐based MTTKRP and TTM‐chain approaches for sparse tensors, which are portable to any CPU or GPU, extending previous literature by handling mode‐4 and mode‐5 tensors and tackling the TTM‐chain operation as a whole, allowing for further optimizations. The experimental results show that the proposed approaches present linear to superlinear scalability as the problem size grows and outperform the portable state‐of‐the‐art by 4.9× on average.

This article presents an energy-efficient serial multiply-accumulate (MAC) unit based on the most significant digit first (MSDF) approach, specifically aimed at neural networks operating in resource-constrained and low-energy environments. The proposed MAC unit has been integrated into two neural network architectures: a multilayer perceptron (MLP) and a denoising autoencoder. For the MLP, we employ a pre-trained model for handwritten digit classification using the Modified National Institute of Standard and Technology (MNIST) dataset. Hardware synthesis using 45 nm CMOS technology shows that the MSDF-based MLP achieves a favorable trade-off between hardware metrics, such as reduced circuit area and energy per neuron, and reaches a good classification accuracy of 97.4%. In the case of the autoencoder, the proposed MAC unit is utilized in a pre-trained denoising autoencoder for the same dataset. The autoencoder employs MSDF-based mixed precision across layers to reduce computational resources and loads while preserving high-quality image reconstruction. A comprehensive evaluation of image correctness, signal fidelity, and visual quality metrics was conducted to assess the impact of varying precision levels across different layers. The results indicate that the proposed approach achieves an effective denoising performance with balanced hardware requirements.

Epistasis detection is a bioinformatics application that searches for associations between sets of single nucleotide polymorphisms (SNPs) and a given trait of a population. Epistasis detection is a computationally complex problem, especially when tackling interaction orders above two. This paper presents a pioneering approach for performing third-order epistasis searches that has been devised around the bulk-synchronous parallel (BSP) model of execution, which is used in processor designs that target artificial intelligence (AI) workloads, such as Graphcore’s Intelligence Processing Unit (IPU). We propose a parallelization approach and a set of optimizations to efficiently exploit the computation and communication resources of these novel AI processors to perform precise bioinformatics searches. The proposed approach achieves a performance of 3.9 Tera SNP combinations evaluated per second, scaled to sample size, on an IPU-M2000 AI accelerator, while close to a linear speedup (up to 15.01×) is achieved with 16 IPU-M2000 accelerators.

This paper proposes a method for hardware integer division by a constant, based only on combinational logic, i.e. without requiring storage and feedback in calculations. The proposed scheme for division consists of adders and encoders, where encoders are systems of Boolean functions. The proposed divisor provides at the output the quotient and the residue (at the same time or separately). Experiments conducted on FPGA demonstrate up to three times improvement in area cost compare to the optimized divisor circuits provided by the Xilinx tools, while the delay is improved by 25% for dividends with less than 48-bit. It is also shown in this paper that the proposed approach is scalable, and in comparison to the state-of-the-art, the proposed approach improves the area or the delay, or both for many constant values and input bit sizes.

Increased attention to RISC-V open Instruction Set Architecture (ISA), a base ISA with a variety of optional extensions, has fueled its move from embedded devices to the high-performance computing arena, with the proliferation of RISC-V-based accelerators. However, the absence of powerful performance monitoring tools often results in poorly optimized applications and, consequently, limited computing performance. While the RISC-V ISA already defines a hardware performance monitor (HPM), research and development on RISC-V-based devices have been more focused on architectures and compilers rather than tools to support monitoring performance. To overcome this limitation, a comprehensive set of extensions and modifications to the Performance analysis tools for Linux (perf/perf_events) are proposed in this paper, and a PAPI library interface is presented. These new extensions comprise not only the Linux kernel but also the OpenSBI interface, and aim to achieve full support for the RISC-V performance monitoring specification. The conducted testing and evaluation were carried out on a HiFive Unmatched board and on a CVA6 core, but the proposed extensions, and the corresponding implementation, are easily portable to other systems.

This book contains the proceedings of the 33rd edition of the International Conference on Field Programmable Logic and Applications (FPL) held in Gothenburg on September 4th to 8th, 2023.

Heterogeneity is emerging as one of the most profound and challenging characteristics of parallel environments. From the macro level, where distributed systems are built around heterogeneous networks connecting multiple nodes with computing devices of diverse architectures, to the micro level, where ever-deeper memory hierarchies and specialized accelerators are increasingly common, the impact of heterogeneity on parallel processing is rapidly increasing. Traditional parallel algorithms, programming environments and tools designed for legacy homogeneous multiprocessors achieve at best a small fraction of the efficiency and performance expected from highly heterogeneous parallel computing systems. Therefore, innovative models, algorithms, programming environments and tools are required to efficiently tackle the challenges and fully exploit the resources of modern parallel and heterogeneous platforms. The international workshop on algorithms, models and tools for parallel computing on heterogeneous platforms (HeteroPar) is a premium forum for researchers on algorithms, programming languages, tools, and theoretical models for efficiently solving complex problems on heterogeneous parallel platforms. The 14th edition of HeteroPar (2022) took place in Glasgow, Scotland, co-located with the Euro-Par annual international conference. The workshop includes one keynote and 11 technical presentations. The selected papers cover a good spectrum of research topics in heterogeneous computing showing the challenges present on these modern platforms, hopefully indicating to interested readers possible directions for further research in this field. On behalf of every reader of this Special Issue, the Guest Editors would like to thank all the authors who submitted their papers and worked hard to respond to Reviewers' requests in due time, all the anonymous reviewers who participated in the review process providing helpful suggestions, as well as the Editor in Chief and the entire staff of Wiley's Concurrency and Computation: Practice and Experience who oversaw the whole process.

The rapid progress in quantum computing has initiated a new round of cryptographic innovation, that is, developing postquantum cryptography (PQC) to resist attacks from well-established quantum computers. In this brief, we propose a novel compact and optimized polynomial multiplier accelerator (COPMA) for high-performance implementation of learning-with-rounding (LWR)-based PQC. As not many LWR-based PQC schemes are available in the literature, we have just used Saber, the National Institute of Standards and Technology (NIST) third-round PQC standardization finalist, as a typical case study example. First of all, we have formulated the polynomial multiplication, the major component of Saber, into a novel “subpolynomial”-based processing format for compact computation (yet has the potential for fast operation). Then, we have designed the proposed algorithm into an area-efficient polynomial multiplication hardware accelerator with high-frequency operational capability. Finally, we have verified the efficiency of the developed COPMA and have deployed it to build a cryptoprocessor. The implementation and analysis demonstrate the superior performance of the proposed COPMA. The proposed strategy is highly efficient and can be extended to build other PQC hardware accelerators.

The improved accessibility of gene sequencing technologies has led to creation of huge datasets, i.e. patient records related to certain human diseases (phenotypes). Hence, deriving fast and accurate algorithms for efficiently processing these datasets is a paramount concern to enable some key healthcare scenarios, such as personalizing treatments, explaining the occurrence of and/or susceptibility to complex conditions and reducing the spread of infectious diseases. This is especially true for high-order epistasis detection, one of the most computationally challenging problems in bioinformatics, where associations between a given phenotype and single nucleotide polymorphisms (SNPs) of a population can often only be uncovered through evaluation of a large number of SNP combinations. To tackle this challenge, we propose a novel fourth-order epistasis detection algorithm that leverages tensor processing capabilities of two distinct accelerator architectures by efficiently mapping core computations related to processing quads of SNPs to binary tensor-accelerated matrix operations. Experimental results show that the proposed approach delivers very high performance even in single-GPU environments, e.g., 27.8 and 90.9 tera quads of SNPs per second, scaled to the sample size, were processed on Titan RTX (Turing) and A100 (Ampere) PCIe GPUs, respectively. Being the first approach that exploits tensor cores for accelerating searches with interaction order above three, the proposed method achieved a performance of up to 835.4 tera quads of SNPs per second on the 8-GPU HGX A100 server, which represents performance two or more orders of magnitude higher than that of related art.

Developments in Genome-Wide Association Studies have led to the increasing notion that future healthcare techniques will be personalized to the patient, by relying on genetic tests to determine the risk of developing a disease. To this end, the detection of gene interactions that cause complex diseases constitutes an important application. Similarly to many applications in this field, extensive data sets containing genetic information for a series of patients are used (such as Single-Nucleotide Polymorphisms), leading to high computational complexity and memory utilization, thus constituting a major challenge when targeting high-performance execution in modern computing systems. To close this gap, this work proposes several novel approaches for the detection of three-way gene interactions in modern CPUs and GPUs, making use of different optimizations to fully exploit the target architectures. Crucial insights from the Cache-Aware Roofline Model are used to ensure the suitability of the applications to the computing devices. An extensive study of the architectural features of 13 CPU and GPU devices from all main vendors is also presented, allowing to understand the features relevant to obtain high-performance in this bioinformatics domain. To the best of our knowledge, this study is the first to perform such evaluation for epistasis detection. The proposed approaches are able to surpass the performance of state-of-the-art works in the tested platforms, achieving an average speedup of 3.9× (7.3× on CPUs and 2.8× on GPUs) and maximum speedup of 10.6× on Intel UHD P630 GPU.

Optimization problems are becoming increasingly difficult challenges as a result of the definition of more realistic formulations and the availability of larger input data. Fortunately, the computing capabilities of state-of-the-art heterogeneous systems represent an opportunity to deal with the main complexity factors of these problems. These platforms open the door to the definition of robust metaheuristic solvers, in which parallel computations of different nature can be efficiently mapped to the most suitable architectures and hardware resources. This work investigates the combination of multi-level parallelism and heterogeneous computing to address an important multiobjective problem in bioinformatics: phylogenetics. A parallel metaheuristic approach, based on the joint exploitation of parallel tasks at the algorithm, iteration, and solution levels, is proposed to tackle computationally intensive inferences on CPU+GPU systems. Different heterogeneous design alternatives are also discussed, in accordance with the way the interactions between CPU and GPU are handled. The experimental evaluation of the proposal on real-world biological datasets points out the benefits of using multi-level, heterogeneous strategies, reporting accelerations up to 396× over the baseline metaheuristic as well as significant energy savings with regard to other parallel approaches, without impacting multiobjective solution quality.

Recently, there has been much interest in the use of convolutional neural networks (CNN) for mobile user localization in massive multiple-input multiple-output (MIMO) systems operating at millimeter wave (mmWave) frequencies. However, current CNN-based approaches cannot predict the confidence interval bounds for the localization accuracy. While the Bayesian neural network (BNN) method can be employed to estimate the model uncertainty, it entails a high computational cost. In this letter, the Monte Carlo (MC) dropout based method is proposed as a low-complexity approximation to BNN inference for capturing the uncertainty in a CNN-based mmWave MIMO outdoor localization system, without sacrificing accuracy. The proposed method is evaluated by means of simulations using a ray-tracing model of urban propagation at 28GHz. Results show that the localization uncertainty region can be properly determined and that their shape depends on the maximum power received at the user.

This paper proposes two architectures for the acceleration of Number Theoretic Transforms (NTTs) using a novel Montgomery-based butterfly. We first design a custom NTT hardware accelerator for Field-Programmable Gate Arrays (FPGAs). The butterfly architecture is expanded to a Modular Arithmetic Logic Unit (MALU) and for greater reuse and easier programmability a six-stage pipeline Linux-ready RISC-V core is extended with custom instructions. The performance of the proposed architectures is assessed on a Xilinx Ultrascale+ FPGA and with an Application-Specific Integrated Circuit (ASIC) on$28{n}\text{m}$CMOS technology. In FPGA, the results for custom acceleration show reductions of 30%, 90% and 42% in the number of Lookup tables (LUTs) and registers, Block RAMs (BRAMs) and Digital Signal Processors (DSPs), while providing a speedup of 1.9 times, in comparison with the state of the art. The ASIC results show that at 1 GHz the proposed architecture is in average 45% and 52% less area and power hungry, respectively, compared to the state of the art. Furthermore, the proposed MALU, operating as an additional execution unit, increases the overall area of the extended RISC-V core by only 10%, without significant changes in the frequency of operation.

Inter-algorithm cooperative approaches are increasingly gaining interest as a way to boost the search capabilities of evolutionary algorithms (EAs). However, the growing complexity of real-world optimization problems demands new cooperative designs that implement performance-driven strategies to improve the solution quality. This article explores multiobjective cooperation to address an important problem in bioinformatics: the reconstruction of phylogenetic histories from amino acid data. The proposed method is built using representative algorithms from the three main multiobjective design trends: 1) nondominated sorting genetic algorithm II; 2) indicator-based evolutionary algorithm; and 3) multiobjective evolutionary algorithm based on decomposition. The cooperation is supervised by an Elite island component that, along with managing migrations, retrieves multitrend performance feedback from each approach to run additional instantiations of the most satisfying algorithm in each stage of the execution. Experimentation on five real-world problem instances shows the benefits of the proposal to handle complex optimization tasks, in comparison to stand-alone algorithms, standard island models, and other state-of-the-art methods.

No abstract available.

The Number Theoretic Transform (NTT) plays a central role for supporting high-performance polynomial multiplication on Post-Quantum Cryptography (PQC) and Fully-Homomorphic Encryption (FHE). This paper proposes a novel Montgomery-based butterfly to efficiently implement NTTs on FPGAs. This proposal is supported on prime moduli suitable for FHE, which minimizes the requirements to allow the speedup of the computation of the butterfly. A search algorithm is presented to select these moduli, while flexibility is a target in all parameters making the proposed architectures well-suited for FHE and PQC schemes. We experimentally evaluate the effectiveness of the novel butterfly-core on a Xilinx Virtex-7 device. The results show reductions up to 19%, 41%, 37%, and 67% in the number of lookup tables, slices, flip-flops, and Digital Signal Processors (DSPs), respectively, in comparison to the related state of the art. By integrating the proposed butterflies in a complete NTT accelerator, a speedup of up to 1.42 is achieved, while less than half of the number of DSPs are required, when compared to the other proposals. Moreover, the integration of the proposed accelerators to design FHE-based processors is discussed.

The investigation of highly-efficient parallel algorithms targeting modern heterogeneous systems can provide bioinformaticians new mechanisms to find relations between genetics, phenotype and environment. This paper proposes an approach for fourth-order exhaustive, i.e. as precise as possible, epistasis detection targeting modern heterogeneous systems. Being implemented in Data Parallel C++ / SYCL, the proposed approach relies on technologies and tools built around open standards, making it able to target different types of architectures and devices. As a means to show interoperability with hardware from different sources, we have included performance results obtained from execution on different systems. Scaled to the number of samples, the proposed approach achieved a performance per GPU stream core of up to 236, 472 or 487 mega quads of SNPs processed per second, on GPUs with the Gen9.5, Gen12 and Turing architectures. This metric is reported for different implementation variants combining different considered optimizations. The proposed approach is able to target a wide range of CPU and GPU devices, enabling more users to access high-throughput epistasis detection software.

The substitution of nucleotides at specific positions in the genome of a population, known as single-nucleotide polymorphisms (SNPs), has been correlated with a number of important diseases. Complex conditions such as Alzheimer's disease or Crohn's disease are significantly linked to genetics when the impact of multiple SNPs is considered. SNPs often interact in an epistatic manner, where the joint effect of multiple SNPs may not be simply mapped to a linear additive combination of individual effects. Genome-wide association studies considering epistasis are computationally challenging, especially when performing triplet searches is required. Some contemporary computer architectures support fused XOR and population count as the highest throughput operations as part of tensor operations. This article presents a new approach for efficiently repurposing this capability to accelerate 2-way (pairs) and 3-way (triplets) epistasis detection searches. Experimental evaluation targeting the Turing GPU architecture resulted in previously unattainable levels of performance, with the proposal being able to evaluate up to 108.1 and 54.5 tera unique sets of SNPs per second, scaled to the sample size, in 2-way and 3-way searches, respectively.

State-of-the-art implementations of homomorphic encryption exploit the Fan and Vercauteren (FV) scheme and the Residue Number System (RNS). While the RNS breaks down large integer arithmetic into smaller independent channels, its non-positional nature makes operations such as division and rounding hard to implement, and makes the representation of small values inefficient. In this work, we propose the application of the Hybrid Position-Residues Number System representation to the FV scheme. This is a positional representation of large radix where the digits are represented in RNS. It inherits the benefits from RNS and allows to accelerate the critical division and rounding operations while also making the representation of smaller values more compact. This directly benefits the decryption and the homomorphic multiplication procedures, reducing their asymptotic complexity, in dimension n, from O(n2log n) to O(n log n) and from O(n3log n) to O(n3), respectively and has resulted in noticeable speedups when experimentally compared to related art RNS implementations.

Genome-wide association studies are performed to correlate a number of diseases and other physical or even psychological conditions (phenotype) with substitutions of nucleotides at specific positions in the human genome, mainly single-nucleotide polymorphisms (SNPs). Some conditions, possibly because of the complexity of the mechanisms that give rise to them, have been identified to be more statistically correlated with genotype when multiple SNPs are jointly taken into account. However, the discovery of new associations between genotype and phenotype is exponentially slowed down by the increase of computational power required when epistasis, i.e., interactions between SNPs, is considered. This paper proposes a novel graphics processing unit (GPU)-based approach for epistasis detection that combines the use of modern tensor cores with native support for processing binarized inputs with algorithmic and target-focused optimizations. Using only a single mid-range Turing-based GPU, the proposed approach is able to evaluate 64.8×1012and 25.4×1012sets of SNPs per second, normalized to the number of patients, when considering 2-way and 3-way epistasis detection, respectively. This proposal is able to surpass the state-of-the-art approach by 6× and 8.2× in terms of the number of pairs and triplets of SNP allelic patient data evaluated per unit of time per GPU.

The conversion from a Residue Number System (RNS) to a weighted representation is a costly inter-modulo operation that introduces delay and area overhead to RNS processors, while also increasing power consumption. This paper proposes a new approach to decompose the reverse conversion into operations that can be processed by the arithmetic units already present in the RNS independent channels. This leads to a more effective reuse of the processor circuitry while enhancing parallelism. Experimental results show that, when the proposed techniques are applied to architectures based on ripple-carry adders for the traditional 3-moduli set, the delay is improved in average by 16 percent, the circuit area by 36 percent and the power consumption by 47 percent. When carry-lookahead adder topologies are considered, these improvements are in average of 45 percent for the circuit area and 58 percent for the power consumption while the delay is only slightly reduced. The proposed techniques are applied to a use case in digital filtering, showing an increase in throughput/area of up to 1.25 times, and average reductions in energy consumption of 15.6 percent. This work is a step forward to the usage of RNS in practice, since reverse conversion underpins other hard inter-modulo operations, like comparison, scaling and division.

In an ever more data-centric economy, machine learning models have risen in importance. With the large amounts of data companies collect, they are able to develop highly accurate models to predict the behaviours of their customers. It is thus important to safeguard the data used to build these models to prevent competitors from mimicking their services. In addition, as this type of techniques finds its way into areas that need to deal with more sensitive information, like the medical industry, the privacy of the data that needs to be classified also has to be ensured. Herein, this topic is addressed by homomorphically evaluating Support Vector Machine (SVM) models, in a way that guarantees that a client learns nothing about the model except for the classification of his data, and that the service provider learns nothing about the data. Whereas, previously, Fully Homomorphic Encryption (FHE) has mostly focused on either bit-wise or value-wise computations, SVMs present an additional challenge since they combine both: during an initial phase a kernel function is evaluated that makes use of real arithmetic, and during a second phase the sign bit has to be extracted. Novel techniques are herein proposed that allow for speedups of up to 2.7 and 6.6 for the evaluation of polynomials and the determination of sign, respectively, in comparison to the state of the art. Finally, it is shown that the proposed techniques do not deteriorate the classification accuracy of the SVM models.

The increasing demand for Web services encourages commercial cloud service providers to publish their own services with various functional and nonfunctional capabilities in different cloud platforms. The aggregation of atomic services from multiple service repositories is the main idea of the service composition concept in multiclouds. The cloud Web service composition is a suitable way for satisfying users' complex requests by integrating services from different clouds in order to create a new value-added composite service. The time required to serve a composite service by a multicloud environment is an important parameter, which depends on different factors, ranging from the service composition and selection algorithm to the number of atomic services published in the clouds. In this paper, a model based on timed colored Petri nets (TCPNs) is proposed to evaluate the service composition in multicloud environments while minimizing the number of clouds involved in serving a composite service request. The proposed TCPN graphically models the process of request submission, composite service analysis, service selection, and service provisioning in a multicloud environment. It also assesses both mean response time of the environment and probability of dropping composite requests. The verification of the accuracy of the proposed model is done by comparing the results obtained from the TCPN model, in two different scenarios, with the results from the CloudSim framework. These results confirm that our proposed TCPN model can appropriately model the system and evaluate its performance more efficiently than the CloudSim.

The Residue Number System (RNS) is a numeral representation enabling for more efficient addition and multiplication implementations. However, due its non-positional nature, modular reductions, required for example by Elliptic Curve (EC) Cryptography (ECC), become costlier. Traditional approaches to RNS modular reduction resort to the Montgomery algorithm, underpinned by large basis extensions. Recently, Hybrid-Positional Residue Number Systems (HPRs) have been proposed, providing a trade-off between the efficiency of RNS and the flexibility of positional number representations. Numbers are represented in a positional representation with the coefficients represented in RNS. By crafting primes of a special form, the complexity of reductions modulo those primes is mitigated, relying on extensions of smaller bases. Due to the need of crafting special primes, this approach is not directly extensible to group operations over currently standardised elliptic curves. In this paper, the Hybrid-Polynomial Residue Number System (HyPoRes) is proposed, enabling for improved modular reductions for any prime. Experimental results show that the modular reduction of HyPoRes, although at most 1.4 times slower than HPR for HPR-crafted primes, is up to 1.4 times faster than a generic RNS approach for primes of ECC standards.

With 5G millimeter wave communications, the resulting radiation reflects on most visible objects, creating rich multipath environments. The radiation is thus significantly shaped by the obstacles it interacts with, carrying latent information regarding the relative positions of the transmitter, the obstacles, and the mobile receiver. Through a pre-estabilhed codebook of beamforming patterns transmitted by a base station, the concept of beamformed fingerprints for mobile devices' outdoor positioning has been previously proposed. In this paper, a tailored hierarchical convolutional neural network is proposed to further leverage the structure in the aforementioned hidden information. Average errors of down to 3.3 meters are obtained on a simulation environment based on realistic outdoor scenarios, containing mostly non-line-of-sight positions, making it a very competitive and promising alternative for outdoor positioning.

This paper investigates the performance of epidemic routing, in mobile social networks (MSNs), which makes use of the store-carry-forward paradigm for communication. Real-life mobility traces show that people have skewed location visiting preferences, with some places visited frequently and some others infrequently. In order to model epidemic routing in MSNs, we first analyze the time taken for a node to meet the first node belonging to a set of nodes restricted to move in a specific subarea. Afterwards, a monolithic stochastic reward net (SRN) is proposed to evaluate the delivery delay and the average number of transmissions under epidemic routing by considering skewed location visiting preferences. This monolithic model is not scalable enough, in terms of the number of nodes and frequently visited locations. In order to achieve higher scalability, the folding technique is applied to the monolithic SRN and an approximate folded SRN is proposed to evaluate the performance of epidemic routing. Discrete-event simulation is applied to cross-validate the proposed models. Results indicate that the monolithic model has higher accuracy in predicting the performance of epidemic routing. The approximate folded model also achieves a good accuracy and can be solved for a network with a large number of nodes/frequently visited locations. This model is more accurate than the ordinary differential equation approach.

Inter-modulo arithmetic operations, such as reverse conversion and scaling, are important but difficult operations in the RNS domain. This paper proposes efficient arithmetic units to perform this hard class of RNS operations for a new family of augmented three-moduli sets {2n+k,2n−1,2n+1−1}(0≤k≤n)⁠. Experimental results for 65 nm CMOS technology show that the proposed reverse converter reduces the delay by about (17.6−33.4)% in comparison with the state of the art. Moreover, this work presents the first architecture of a scaler dedicated for this augmented three-moduli sets.

NUMA platforms, emerging memory architectures with on-package high bandwidth memories bring new opportunities and challenges to bridge the gap between computing power and memory performance. Heterogeneous memory machines feature several performance trade-offs, depending on the kind of memory used, when writing or reading it. Finding memory performance upper-bounds subject to such trade-offs aligns with the numerous interests of measuring computing system performance. In particular, representing applications performance with respect to the platform performance bounds has been addressed in the state-of-the-art Cache-Aware Roofline Model (CARM) to troubleshoot performance issues. In this paper, we present a Locality-Aware extension (LARM) of the CARM to model NUMA platforms bottlenecks, such as contention and remote access. On top of this, the new contribution of this paper is the design and validation of a novel hybrid memory bandwidth model. This new hybrid model quantifies the achievable bandwidth upper-bound under above-described trade-offs with less than 3 percent error. Hence, when comparing applications performance with the maximum attainable performance, software designers can now rely on more accurate information.

Residue number systems (RNSs) are efficient alternatives to positional number systems, providing fast and power-efficient computational systems. The key feature of the RNS benefitting modern embedded systems and the Internet-of-Thing (IoT) edge devices is its energy efficiency. Modular addition is the most important and frequent operation applied on the components of RNS, including arithmetic units in the channels as well as forward and reverse converters. The small and medium dynamic range requirements of low-power embedded and edge devices make the usage of the thermometer coding (TC) and one-hot coding (OHC) viable, reducing the power consumption and improving the energy efficiency of modulo addition in comparison to regular binary representations. Based on these techniques, this paper presents two new energy-efficient modular adders, which, due to the carry-free internal computations, are also highly performing. The proposed modular adders based on the TC and OHC result in average improvements of 38% and 34.5% for the delay, 27% and 14.5% for the circuit area, 29.5% and 6.3% for energy consumption, and about 54.9% and 44.2% for the area-delay product (ADP), respectively, in comparison with the related state of the art.

Millimeter wave frequencies paired up with MIMO antennas employing beamforming are seen as critical enablers of next generation networks. However, selecting the most beneficial beamforming weights in a codebook-enabled downlink transmitter is a lengthy task, as the existing methods rely on some form of channel measurement. In fact, if the used codebook is too large, the traditional methods might fail to select an appropriate entry within the channel coherence time. In this paper, a new method to assist the beam selection is proposed, based on data obtained from previous connections. Through the continuous update of the set of optimal codebook entries for each position, the search space required for each connection can be greatly reduced if the user position is known. The simulations performed show that retrieving the sets of codebook entries in single user scenarios required less than 51 ns. For multi-user scenarios, results exceeding 10 simultaneous users using a 16 entry codebook were achieved, requiring less than 600 μs. The obtained results show that the proposed method can greatly reduce the beam selection latency and energy requirements, opening the door to powerful millimeter wave networks.

Reversible logic is a computing paradigm that has attracted significant attention in recent years due to its properties that lead to ultra-low power and reliable circuits. Reversible circuits are fundamental, for example, for quantum computing. Since addition is a fundamental operation, designing efficient adders is a cornerstone in the research of reversible circuits. Residue Number Systems (RNS) has been as a powerful tool to provide parallel and fault-tolerant implementations of computations where additions and multiplications are dominant. In this paper, for the first time in the literature, we propose the combination of RNS and reversible logic. The parallelism of RNS is leveraged to increase the performance of reversible computational circuits. Being the most fundamental part in any RNS, in this work we propose the implementation of modular adders, namely modulo 2n-1 adders, using reversible logic. Analysis and comparison with traditional logic show that modulo adders can be designed using reversible gates with minimum overhead in comparison to regular reversible adders.

With millimeter wave wireless communications, the resulting radiation reflects on most visible objects, creating rich multi path environments, namely in urban scenarios. The radiation captured by a listening device is thus shaped by the obstacles encountered, which carry latent information regarding their relative positions. In this paper, a system to convert the received millimeter wave radiation into the device's position is proposed, making use of the aforementioned hidden information. Using deep learning techniques and a pre-established codebook of beamforming patterns transmitted by a base station, the simulations show that average estimation errors below 10 meters are achievable in realistic outdoors scenarios that contain mostly non-line-of-sight positions, paving the way for new positioning systems.

In this paper, the performance of a grid resource is modeled and evaluated using stochastic reward nets (SRNs), wherein the failure–repair behavior of its processors is taken into account. The proposed SRN is used to compute the blocking probability and service time of a resource for two different types of tasks: grid and local tasks. After modeling a grid resource and evaluating the performability measures, an algorithm is presented to find the probability mass function (pmf) of the service time of the grid resource for a program which is composed of grid tasks. The proposed algorithm exploits the universal generating function to find the pmf of service time of a single grid resource for a given program. Therefore, it can be used to compute the pmf of the service time of entire grid environment for a workflow with several dependent programs. Each possible scheduling of programs on grid resources may result in different service times and successful execution probabilities. Due to this fact, a genetic-based scheduling algorithm is proposed to appropriately dispatch programs of a workflow application to the resources distributed within a grid computing environment. Numerical results obtained by applying the proposed SRN model, the algorithm to find the pmf of grid service time, and the genetic-based scheduling algorithm to a comprehensive case study demonstrate the applicability of the proposed approach to real systems.

The High Efficiency Video Coding HEVC standard provides a higher compression efficiency than other video coding standards but at the cost of an increased computational load, which makes hard to achieve real-time encoding/decoding for ultra high-resolution and high-quality video sequences. Graphics Processing Units GPU are known to provide massive processing capability for highly parallel and regular computing kernels, but not all HEVC decoding procedures are suited for GPU execution. Furthermore, if HEVC decoding is accelerated by GPUs, energy efficiency is another concern for heterogeneous CPU+GPU decoding. In this paper, a highly parallel HEVC decoder for heterogeneous CPU+GPU system is proposed. It exploits available parallelism in HEVC decoding on the CPU, GPU, and between the CPU and GPU devices simultaneously. On top of that, different workload balancing schemes can be selected according to the devoted CPU and GPU computing resources. Furthermore, an energy optimized solution is proposed by tuning GPU clock rates. Results show that the proposed decoder achieves better performance than the state-of-the-art CPU decoder, and the best performance among the workload balancing schemes depends on the available CPU and GPU computing resources. In particular, with an NVIDIA Titan X Maxwell GPU and an Intel Xeon E5-2699v3 CPU, the proposed decoder delivers 167 frames per second (fps) for Ultra HD 4K videos, when four CPU cores are used. Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of 2.2×. When decoding performance is bounded by the CPU, a system wise energy reduction up to 36% is achieved by using fixed (and lower) GPU clocks, compared to the default dynamic clock settings on the GPU.

Among the different scientific domains where metaheuristics find applicability, bioinformatics represents a particularly challenging field due to the multiple complexity factors involved in the processing of biological data. In this context, the exploration of protein sequence data is remarkably increasing the temporal demands of such biological problems, thus motivating the interest in investigating new approaches that effectively combine bioinspired metaheuristics and parallelism. This paper addresses the reconstruction of ancestral relationships from amino acid sequences by using a multiobjective approach based on the shuffled frog-leaping optimization technique. Due to the inherent parallel nature of this approach, we define different parallel schemes aimed at exploiting the computing capabilities of modern cluster platforms. The experiments performed in five real datasets give account of the relevance of using parallelism-aware metaheuristic designs, as well as the need to consider both parallel performance and solution quality when tackling such difficult optimization scenarios.

Optimization, portability and development of GPGPU applications are not trivial tasks, since the capabilities and organization of GPU processing elements and memory subsystem greatly differ from the traditional CPU concepts, as well as among different GPU architectures. This work goes a step further in aiding this process by delivering a set of visual models that can be used by GPU programmers to analyze and improve application performance and energy-efficiency across a range of different GPU devices. For the first time in this paper, the state-of-the-art Cache-aware Roofline Modeling principles are applied for insightful modeling of GPU upper-bounds for performance, power consumption and energy-efficiency. The proposed models are developed by relying on extensive GPU micro-benchmarking aimed at fully exercising the capabilities of GPU functional units and memory hierarchy levels. The models are experimentally validated across 8 GPU devices from 3 different NVIDIA generations, and their benefits are explored when characterizing the behavior of 23 real-world applications from 5 different benchmark suites. Furthermore, the DVFS effects on GPU performance upper-bounds are also analyzed by scaling both core and memory frequencies.

Energy efficiency has become a primary concern in the design of multimedia digital systems, particularly when targeting mobile devices. Approximate computing is a highly promising approach to address this challenge. This paper presents an architectural exploration in a variable block size motion estimation (VBSME) architecture using imprecise Lower-Part-OR Adders (LOA). These adders were applied to Sum of Absolute Differences units (SAD) in order to reduce the energy consumption while introducing a minimum impact on the coding efficiency. Three VBSME architectures with LOA operators were developed by considering different imprecision levels. The conducted evaluations, performed using the High-Efficiency Video Coding standard (HEVC) reference software, showed that this technique introduces a negligible impact on the coding efficiency (between 0.6% and 2.5% increase of the BD-Rate). Nevertheless, when the designed architectures were synthesized for a 45nm standard cells technology, significant power savings were observed (between 7% and 11.5%, depending on the used LOA version), demonstrating the viability and significant gains of the proposed approach.

Summary In this paper, we propose an energy‐aware task management mechanism designed for the forward‐in‐time algorithms running on multicore central processing units (CPUs), where the multidimensional positive definite advection transport algorithm stencil‐based algorithm is one of the representative examples. This mechanism is based on the dynamic voltage and frequency scaling technique and allows the reduction of energy consumption for an existing algorithm (or application) such that the predefined execution time is respected, without requiring any modifications in the algorithm itself. This paper also provides the formulation of a method for minimizing the energy consumption with time constraints, which is based on the adaptive scheduling with online modeling. Finally, using the autotuning technique, we provide the automation of the process for creation and determination of the best energy profile at runtime, even in the presence of additional CPU workloads. The experimental results on a 6‐core computing platform show that the proposed mechanism provides the energy savings of up to 1.43x when compared to the default Linux scaling governor. Also, we confirm the effectiveness of the self‐adaptive feature of the proposed mechanism, by showing its ability to maintain the requested execution time in spite of additional CPU workloads imposed by other applications.

Summary The availability of heterogeneous CPU+GPU systems has opened the door to new opportunities for the development of parallel solutions to tackle complex biological problems. The reconstruction of evolutionary histories among species represents a grand computational challenge, which can be addressed by exploiting this kind of hardware designs. In this research, we study the application of heterogeneous computing with OpenCL to accelerate one of the most well‐known objective functions for inferring phylogenies, the phylogenetic parsimony function. For this purpose, we undertake the design of CPU and GPU kernel implementations of this relevant function, proposing a heterogeneous CPU+GPU multidevice approach that distributes multiple parsimony evaluations among processing devices. Experiments on 6 real nucleotide data sets and comparisons with other parallel implementations give account of the benefits of the proposal in this paper, obtaining significant parallel results by combining CPU and GPU capabilities in accordance with the characteristics of the input data.

To foster the energy-efficiency in current and future multi-core processors, the benefits and trade-offs of a large set of optimization solutions must be evaluated. For this purpose, it is often crucial to consider how key micro-architecture aspects, such as accessing different memory levels and functional units, affect the attainable power and energy consumption. To ease this process, we propose a set of insightful cache-aware models to characterize the upper-bounds for power, energy and energy-efficiency of modern multi-cores in three different domains of the processor chip: cores, uncore and package. The practical importance of the proposed models is illustrated when optimizing matrix multiplication and deriving a set of power envelopes and energy-efficiency ranges of the micro-architecture for different operating frequencies. The proposed models are experimentally validated on a computing platform with a quad-core Intel 3770K processor by using hardware counters, on-chip power monitoring facilities and assembly micro-benchmarks.

With Lattice-based cryptography (LBC), ciphertexts are represented as points near a lattice, and Babai's round-off algorithm allows to decrypt them when one knows the secret-key. Recently, an accelerated variant of the round-off, based on Residue Number Systems (RNSs), has been proposed. Herein, we combine this technique with the use of lattices of Optimal Hermite Normal Form (OHNF) and propose further refinements, so as to reduce the decryption complexity. This approach lends itself largely to data-level parallelism, allowing for low latency decryption operations on multi-core CPUs with Single Instruction Multiple Data (SIMD) extensions, and achieves high-throughput on GPUs. Finally, we are able to perform decryptions up to 20 times faster than the most efficient implementation in related art, which exploits the Mixed-Radix System (MRS), in an Intel i7 6700K CPU, and we are able to decrypt up to 11,832 messages/s in a Titan X GPU.

The high compression efficiency that is provided by the high efficiency video coding (HEVC) standard comes at the cost of a significant increase of the computational load at the decoder. Such an increased burden is a limiting factor to accomplish real-time decoding, specially for high definition video sequences (e.g., Ultra HD 4K). In this scenario, a highly parallel HEVC decoder for the state-of-the-art graphics processor units (GPUs) is presented, i.e., GHEVC. Contrasting to our previous contributions, the data-parallel GHEVC decoder integrates the whole decompression pipeline (except for the entropy decoding), both for intra- and interframes. Furthermore, its processing efficiency was highly optimized by keeping the decompressed frames in the GPU memory for subsequent inter frame prediction. The proposed GHEVC decoder is fully compliant with the HEVC standard, where explicit synchronization points ensure the correct HEVC module execution order. Moreover, the GPU-based HEVC decoder is experimentally evaluated for different GPU devices, an extensive range of recommended HEVC configurations and video sequences, where an average frame rate of 145, 318, and 605 frames per second for Ultra HD 4K, WQXGA, and Full HD, respectively, was obtained in the Random Access configuration with the NVIDIA GeForce GTX TITAN X GPU.

The application of residue number system (RNS) to digital signal processing lies in the ability to operate on signed numbers. However, the available RNS-to-binary (reverse) converters have been designed for unsigned numbers, which means that they do not produce signed outputs. Usually, some additional circuits are introduced at the output of the reverse converter to map the unsigned generated output into a signed number representation. This paper proposes a novel method to design reverse converters with signed output for a class of RNS moduli sets of composite form {2k, 2P-1}. The structure of the modulo adder used in the last stage of the proposed converters is modified in order to reuse the internal circuits to produce the signed output. This adder component is especially designed for achieving reverse converters with signed output, imposing very low area and delay overheads compared with unsigned converters. The proposed approach is applied to design reverse converters for different moduli sets and to implement application specific integrated circuits. Experimental results show that for a 4-moduli converter, the proposed design can outperform the traditional method to obtain signed outputs by improving the delay, chip-area, and energy consumption by up to 9%, 21%, and 35%, respectively.

The High Efficiency Video Coding (HEVC) standard provides higher compression efficiency than other video coding standards but at the cost of increased computational load, which makes it hard to achieve real-time encoding/decoding of high-resolution, high-quality video sequences. In this paper, we investigate how Graphics Processing Units (GPUs) can be employed to accelerate HEVC decoding. GPUs are known to provide massive processing capability for throughput computing kernels, but the HEVC entropy decoding kernel cannot be executed efficiently on GPUs. We therefore propose a complete HEVC decoding solution for heterogeneous CPU+GPU systems, in which the entropy decoder is executed on the CPU and the remaining kernels on the GPU. Furthermore, the decoder is pipelined such that the CPU and the GPU can decode different frames in parallel. The proposed CPU+GPU decoder achieves an average frame rate of 150 frames per second for Ultra HD 4K video sequences when four CPU cores are used with an NVIDIA GeForce Titan X GPU.

In this article, we propose a general framework for fine-grain application-aware task management in heterogeneous embedded platforms, which allows integration of different mechanisms for an efficient resource utilization, frequency scaling, and task migration. The proposed framework incorporates several components for accurate runtime monitoring by relying on the OS facilities and performance self-reporting for parallel and iterative applications. The framework efficiency is experimentally evaluated on a real hardware platform, where significant power and energy savings are attained for SPEC CPU2006 and PARSEC benchmarks, by guiding frequency scaling and intercluster migrations according to the runtime application behavior and predefined performance targets.

To challenge real-time encoding of high-definition video sequences on heterogeneous desktop systems, a collaborative central processing units (CPU) + graphics processing unit (GPU) framework for interloop video encoding is proposed herein. The proposed framework considers the overall complexity of the collaborative interloop encoding as a unified optimization problem. Several functional blocks are integrated for simultaneous execution control, automatic data access management, performance characterization, and adaptive scheduling and load balancing. These blocks aim at fully exploiting the performance of heterogeneous devices, asymmetric bandwidth of communication links, and several levels of concurrency between computation and communication. To support a wide range of CPU and GPU architectures, a specific encoding library is developed with highly optimized algorithms for all interloop modules. The experimental results show that the proposed framework allows achieving a real-time encoding of full high-definition sequences in several CPU + GPU systems. It also delivers performance improvements of up to 61.2% over the state-of-the-art solution, while outperforming individual GPU and quad-core CPU executions by more than 2 and 5 times, respectively.

Should quantum computing become viable, current public-key cryptographic schemes will no longer be valid. Since cryptosystems take many years to mature, research on post-quantum cryptography is now more important than ever. Herein, lattice-based cryptography is focused on, as an alternative post-quantum cryptosystem, to improve its efficiency. We put together several theoretical developments so as to produce an efficient implementation that solves the Closest Vector Problem (CVP) on Goldreich-Goldwasser-Halevi (GGH)-like cryptosystems based on the Residue Number System (RNS). We were able to produce speed-ups of up to 5.9 and 11.2 on the GTX 780 Ti and i7 4770K devices, respectively, when compared to a single-core optimized implementation. Finally, we show that the proposed implementation is a competitive alternative to the Rivest-Shamir-Adleman (RSA).

To satisfy the growing demands on real-time video decoders for high frame resolutions, novel GPU parallel algorithms are proposed herein for fully compliant HEVC de-quantization, inverse transform and intra prediction. The proposed algorithms are designed to fully exploit and leverage the fine grain parallelism within these computationally demanding and highly data dependent modules. Moreover, the proposed approaches allow the efficient utilization of the GPU computational resources, while carefully managing the data accesses in the complex GPU memory hierarchy. The experimental results show that the real-time processing is achieved for all tested sequences and the most demanding QP, while delivering average fps of 118.6, 89.2 and 49.7 for Full HD, 2160p and Ultra HD 4K sequences, respectively.

A new class of quantization architectures suitable for the realization of high performance and hardware efficient forward, inverse and unified quantizers for HEVC is presented. The proposed structures are based on a highly flexible and optimized integer datapath that can be configured to provide several pipelined and non-pipelined implementations, offering distinct trade-offs between performance and hardware cost, which makes them highly suitable for most video coding application domains. The experimental results obtained using a 90 nm CMOS process show that the proposed class of quantization architectures is able to process 4k UHDTV video sequences in real-time (3840 × 2160 @ 30fps), with a power consumption as low as 3.9 mW when the unified architecture is operated at 374 MHz.

In the last years, research on residue number systems (RNS) has targeted larger dynamic ranges in order to further explore the inherent parallelism of these systems. In this paper, a performance analysis is presented for RNS-to-binary architectures based on New Chinese Remainder Theorem I (New CRT-I). Four different approaches are explored, each of them focused on the area or delay reduction of one specific stage of the converter. In addition, a selection of the constants associated to these algorithm approaches is proposed, which results into significant area reductions. Experimental results show that the use of an appropriate parameter selection can achieve a reduction of area and delay around 21% in comparison with the best solutions existing in the state-of-the-art using the New CRT-I technique and conventional parameter selection.

The use of Voice over Internet Protocol (VoIP) is becoming ubiquitous due to the multiple shortcomings of traditional Public Switched Telephone Network (PSTN) systems. As a result, the development of secure key establishment protocols is becoming increasingly important. The Communications-Electronics Security Group (CESG), in response to this demand, has published new key agreement protocols for the Multimedia Internet KEYing (MIKEY) protocol to provide low-cost secure VoIP communications, supported on Identity-based Public-Key Cryptography (IDPKC). In the context of IDPKC, the identity of users is used to derive their public-keys, which eliminates the expenses of maintaining a Public-Key Infrastructure (PKI). However, IDPKC systems suffer from inefficient user revocation and key renewal. In this paper, we take advantage of the fact that users need to be connected to the Internet to communicate, for introducing a SEcurity Mediator (SEM), who possesses a share of the users' private-keys, and with whom the users must cooperate, to sign and decrypt cryptograms. By taking advantage of this sharing, we introduce mechanisms to provide immediate user revocation and key renewal.

A novel fast Coding Tree Unit partitioning for HEVC/H.265 encoder is proposed in this paper. This method relies on run-time trained neural networks for fast Coding Units splitting decisions. Contrasting to state-of-the-art solutions, this method does not require any pre-training and provides a high adaptivity to the dynamic changes in video contents. By an efficient sampling strategy and a multi-thread implementation, the presented technique successfully mitigates the computational overhead inherent to the training process on both the overall processing performance and on the initial encoding delay. The experiments show that the proposed method successfully reduces the HEVC/H.265 encoding time for up to 65% with negligible rate-distortion penalties.

Scaling is a key important arithmetic operation and is difficult to perform in Residue Number Systems (RNS). This paper proposes a comprehensive approach for designing efficient and accurate 2nRNS scalers for important classes of moduli sets that have large dynamic ranges. These classes include the traditional 3-moduli set, but the exponent of the power of two modulo is augmented by a variable value x ({2n- 1; 2n+x, 2n+ 1}), and any extended set with an additional modulo m4({2n- 1, 2n+x, 2n+ 1[, m4]}). The proposed approach embeds scaling into the formulation of the Chinese remainder theorem and the mixed radix system, and it exploits the properties of the target moduli sets to perform scaling explicitly in the RNS domain. This is accomplished by operating hierarchically on each channel without requiring reverse and forward conversions. Simple memoryless VLSI architectures are proposed based on the obtained formulations. The relative assessment indicates that not only are these architectures comprehensive and suitable for configurable systems, but they are also more efficient than the related state of the art in terms of both performance and energy. The experimental results obtained for a 90 nm CMOS ASIC technology show improvements in the area-delay product, normalized with respect to the dynamic range, of up to 57 and 146 percent with the proposed scalers for the augmented 3-moduli set (dynamic range of 4n - 1 bits) and an extended 4-moduli set (dynamic range of 6n bits), respectively. These improvements increase to 64:9 and 263 percent when the energy required per scaling is measured. The proposed scalers are not only flexible and cost-effective, but they are also suitable for designing and implementing energy-constrained devices, particularly mobile systems.

In this brief, a read-only-memoryless structure for binaryto-residue number system (RNS) conversion modulo (2n±k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing (2n± k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the (2n± k} moduli is performed.

In this brief, the implementation of residue number system reverse converters based on well-known regular and modular parallel-prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in nowadays systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix-based adder components that provide better tradeoff between delay and power consumption are herein presented to design reverse converters. A methodology is also described to design reverse converters based on different kinds of prefix adders. This methodology helps the designer to adjust the performance of the reverse converter based on the target application and existing constraints.

Power and flexibility are important constraints in the design of new chips. The efficiency extracted from a design is increasingly becoming a dominant question, and several techniques and technological advances can be used to optimize efficiency in its energy and functionality domains. These two characteristics are critical in digital communication systems that must work accordingly with multiple communication standards at different power, throughput and latency requirements. In this work, we focus on the physical layer Forward Error Correcting (FEC) system, due to the tight throughput and latency constraints they are required to meet, and develop specialized processing engines for Low-Density Parity-Check (LDPC) codes decoding, a class of widely standardized codes. The engines were developed for execution on Field-Programmable Gate Array (FPGA) devices by exploring dataflow and wide-pipeline design approaches, and have the design flexibility to target different LDPC codes, since they were implemented using recent High-Level Synthesis (HLS) tools. The generated engines and architectures allow achieving highly efficient decoders with decoding throughputs ranging from 16 Mbit/s to 1.2 Gbit/s at energy efficiencies of 42 to 908 Mbit/Joule/iteration, while the achieved clock frequencies of operation vary from 80 to 300 MHz. Furthermore, our bandwidth analysis shows that workload boundaries do not impose limitations on a system bus.

Heterogeneous platforms integrating several CPU cores and GPU accelerators have established in several application domains, from desktop, server and mobile. To take full advantage of such platforms, video encoders/decoders have to exploit a broader design space, by cooperatively executing in all the available CPU and GPU cores. To attain such objective, three novel contributions that aim the exploitation of the maximum parallelism level in an HEVC deblocking filter are presented: i) a highly optimized CPU parallel implementation, which outperforms the current state of the art; ii) the first known GPU implementation of the HEVC deblocking filter; and iii) an hybrid and load-balanced CPU+GPU implementation, where all the available resources cooperatively execute, in order to maximize the attained performance. The obtained experimental results demonstrated the ability to achieve processing times as low as 0.8 ms and 0.5 ms to filter 1080p I-type and B-type frames, respectively, corresponding to speedup factors as high as 17 and 9.

High Efficiency Video Coding (HEVC) standard achieves enhanced compression efficiency in comparison to previous standards, at the cost of a dramatic increase of the computational load. In order to cope with such computational requirements, and to challenge the real-time encoding of High Definition (HD) video sequences with the HEVC standard, we propose herein a reconfigurable architecture design for the most computationally demanding motion estimation module, considering highly efficient Full-Search Block-Matching algorithm. The proposed architecture supports Prediction Blocks (PBs) sizes ranging from 8×8 to 64×64 pixels (also considering non-square shapes), and search areas as large as 256×256 pixels. Furthermore, this reconfigurable approach leverages the trade-off between maximum performance and minimum resource usage. Experimental results show that the proposed architecture is able of achieving real-time motion estimation with more than 26.9 fps, for 1080p video formats, a 64×64 pixels search area and 1 reference frame, by relying on a Xilinx Virtex 5 FPGA implementation. Moreover, a performance superior to the NVIDIA Fermi-based GPU implementation, for up to 25%, was achieved.

In this paper we propose an efficient method for collaborative H.264/AVC inter-prediction in heterogeneous CPU+GPU systems. In order to minimize the overall encoding time, the proposed method provides stable and balanced load distribution of the most computationally demanding video encoding modules, by relying on accurate and dynamically built functional performance models. In an extensive RD analysis, an efficient temporary dependent prediction of the search area center is proposed, which allows dependency-aware workload partitioning and efficient GPU parallelization, while preserving high compression efficiency. The proposed method also introduces efficient communication-aware techniques, which maximize data reusing, and decrease the overhead of expensive data transfers in collaborative video encoding. The experimental results show that the proposed method is able of achieving real-time video encoding for very demanding video coding parameters, i.e. full HD video format, 64×64 pixels search area and the exhaustive motion estimation.

Lead by high performance computing potential of modern heterogeneous desktop systems and predominance of video content in general applications, we propose herein an autonomous unified video encoding framework for hybrid multi-core CPU and multi-GPU platforms. To fully exploit the capabilities of these platforms, the proposed framework integrates simultaneous execution control, automatic data access management, and adaptive scheduling and load balancing strategies to deal with the overall complexity of the video encoding procedure. These strategies consider the collaborative inter-loop encoding as a unified optimization problem to efficiently exploit several levels of concurrency between computation and communication. To support a wide range of CPU and GPU architectures, a specific encoding library is developed with highly optimized algorithms for all inter-loop modules. The obtained experimental results show that the proposed framework allows achieving a real-time encoding of full high-definition sequences in the state-of-the-art CPU+GPU systems, by outperforming individual GPU and quad-core CPU executions for more than 2 and 5 times, respectively.

Power analysis attacks are one of the most common Side-Channel Attacks (SCAs), proven to be extremely successful even on protected embedded devices. This paper proposes the use of a Residue Number System (RNS) architecture with randomly permuted moduli sets to implement the Double-and-Add computation, which is proven as the most susceptible operation in Elliptic Curve Cryptography (ECC). The proposed solution randomly permutes the moduli sets, allowing randomized power traces, significantly removing the correlation between the power dissipation and the secret key and eliminating the need for the intermediate conversion to binary required in the state-of-the-art. Architectures obtained for a 90nm standard cell technology suggest that a significant power analysis resistance is achieved for the Double-and-Add circuitry, incurring an extra performance cost of 3 times compared to the related state-of-the-art.

Due to the dissemination of smartphones and tablets, a constant complexity growth can be observed for both embedded systems and mobile applications. However, this results in an increase in energy consumption. To guarantee longer battery life cycles, it is fundamental to develop system level strategies that allow guaranteeing the applications' required quality of service by managing the available system resources. In this paper a new task management framework is proposed that controls, in real-time, the execution of multi-threaded applications in order to meet their performance targets. For this, we amend the Linux CFS scheduler decisions to efficiently control the shared resource utilization of parallel applications. The proposed framework relies on runtime performance modelling of both the underlying architecture and the running applications to scale the system resource allocation and frequency. As a result, efficient application execution is achieved not only in terms of performance, but also in energy consumption. Experimental results show that the proposed approach satisfies the applications required performance level by decreasing the relative performance error from 2.801 to 0.168, while achieving 49 % energy savings.

The high computational demands and overall encoding complexity make the processing of high definition video sequences hard to be achieved in real-time. In this manuscript, we target an efficient parallelization and RD performance analysis of H.264/AVC inter-loop modules and their collaborative execution in hybrid multi-core CPU and multi-GPU systems. The proposed dynamic load balancing algorithm allows efficient and concurrent video encoding across several heterogeneous devices by relying on realistic run-time performance modeling and module-device execution affinities when distributing the computations. Due to an online adjustment of load balancing decisions, this approach is also self-adaptable to different execution scenarios. Experimental results show the proposed algorithm's ability to achieve real-time encoding for different resolutions of high-definition sequences in various heterogeneous platforms. Speed-up values of up to 2.6 were obtained when compared to the video inter-loop encoding on a single GPU device, and up to 8.5 when compared to a highly optimized multi-core CPU execution. Moreover, the proposed algorithm also provides an automatic tuning of the encoding parameters, in order to meet strict encoding constraints.

This paper proposes a unified architecture for designing Residue Number System (RNS) based processors for moduli sets with an arbitrary number of channels. Recently, new RNS moduli sets have been proposed in order to increase the dynamic range and reduce the width of the channels. The proposed architecture allows designing forward and reverse RNS converters, as well as the arithmetic operators of each modulo channel. The forward and reverse conversions are implemented using channel arithmetic units, resulting in a very compact architecture. Moreover, the arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. The presented results suggest that the proposed RNS architecture leads to compact and scalable implementations, with competitive, or even better, performance when compared with the related state of the art, considering fixed moduli sets. Experimental results suggest gains of 17% in the delay of arithmetic operations, with an area reduction of 23% regarding the state of the art.

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks in Elliptic Curve Cryptography (ECC), mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect the ECC from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelization capability in Multi-modulo Residue Number Systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, while still providing all the benefits of RNS. In this paper, we show that Differential Power Analysis is thwarted, as well as correlation analysis.

In Molecular Mechanics simulations, the treatment of electrostatics is the most computational intensive task. Modern force fields, such as the AMOEBA, which include explicit polarization effects, are particularly computationally demanding. We propose a static dataflow architecture for accelerating polarizable force fields. Results, obtained with Maxeler's MaxCompiler, show a speed-up factor of about 14x on a Maxeler 1U MaxNode, when compared to a 12-core CPU node while using half of the dataflow engine capacity. Projections for a full chip implementation indicate that speed-up results of up to 29x per node can be reached. Moreover, our implementation on the Maxeler system shows improvements between 2.5x and 4x compared to NVIDIA Fermibased GPUs. The current work shows the potential of dataflow engines in accelerating this field of applications.

This paper proposes and discusses an architecture with scalability features for the parallel implementation of algorithms relying on modular arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular arithmetic algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular arithmetic algorithms. An implementation with the Xilinx FPGA Virtex 4 technology (xc4vsx55) of modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and EC cryptographic algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.

This article proposes the Computing with the ResidueNumber System (CRNS) framework, which aims at the design automation of accelerators for Modular Arithmetic (MA). The framework provides a comprehensive set of tools ranging from a programming language and respective compiler to back-ends targeting parallel computation platforms such as Graphical Processing Units (GPUs) and reconfigurable hardware. Given an input algorithm described with a high-level programming language, the CRNS can be used to obtain in a few seconds the corresponding optimized Parallel Thread Execution (PTX) program ready to be run on GPUs or the Hardware Description Language (HDL) specification of a fully functional accelerator suitable for reconfigurable hardware and embedded systems. The resulting framework's implementations benefit from the Residue Number System (RNS) arithmetic's parallelization properties in a fully automated way. Designers do not need to be familiar with the mathematical details concerning the employed arithmetic, namely the RNS representation. In order to thoroughly describe and evaluate the proposed framework, experimental results obtained for the supported back-ends (GPU and HDL) are presented targeting the implementation of the modular exponentiation used in the Rivest-Shamir-Adleman (RSA) algorithm and Elliptic Curve (EC) point multiplication. Results suggest competitive latency and throughput with minimum design effort and overcoming all the development issues that arise in the specification and verification of dedicated solutions.

In this brief, we propose a method to design efficient adder-based converters for the four-moduli set {2n+1, 2n-1, 2n, 2n+1+1} with n odd, which provides a dynamic range of 4n+1 bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo 2k-1 additions are required, fully avoiding the usage of modulo 2k+1 arithmetic operations, which is a significant advantage over the currently available RNS reverse converters for this type of moduli set. Experimental results show that the delay of the proposed converters is significantly reduced when compared with the related state of the art; for example, for a 65-nm CMOS ASIC technology and a dynamic range of 21 bits, the conversion time and the circuit area are reduced by about 44% and 30%, respectively, while the conversion time is reduced by 34% for a dynamic range of 37 bits with the circuit area increasing only by 25%. Moreover, the proposed reverse converters outperform the related state of the art for any value of n by up to 70%, according to the figure-of-merit energy per conversion.

This paper presents a novel approach to improve the existing Binary-to-RNS multi-moduli architectures. These architectures reduce the complexity by sharing common intermediate results among various RNS moduli channels. Two types of multi-moduli architectures are distinguished depending on whether the functionality is implemented serially or in parallel. A novel choice of the weights associated to the inputs provides huge improvement when applied to the most efficient topology known to date. Experimental results suggest that the proposed memoryless multi-moduli architectures achieve speedups of 2.02 and 1.79 for parallel and serial implementations, respectively, in comparison with the most efficient state-of-the-art structures. Furthermore, such implementations herein proposed have demonstrated that area reductions of 5.02% and 44.02% are achieved for parallel and serial structures, respectively.

A new high-performance and reduced hardware architecture for the computation of the H.264/AVC forward and inverse quantization operations is presented in this paper. This architecture is based on a highly flexible processing structure that is suitable for very efficient implementations using both FPGA and ASIC technologies. Moreover, it offers several different configurations, in order to provide different trade-offs in terms of performance and hardware cost. Experimental results concerning implementations using a Xilinx Virtex-5 FPGA and a 90 nm CMOS process from UMC demonstrated that the proposed architecture can be used to compute, in real-time, the forward and inverse quantization operations for videos with resolutions up to the Digital Cinema format (4096x2048 @ 30fps).

Recently new Residue Number Systems (RNS) moduli sets have been proposed in order to increase the dynamic range and reduce the width of channels, therefore, reducing the processing time and further exploiting the carry-free characteristic of the modular arithmetic. In this paper we propose improved units for addition, subtraction, and multiplication in RNS for modulo {2n±k}. With this work, the somewhat disregarded field of RNS unit design is covered, encouraging the development of moduli sets with channels other than the traditional {2n}, {2n±1} modulo. In order to evaluate the performance of the proposed structures, they are compared with the well known units for modulo {2n}, {2n±1}, and {2n±3}. These structures allow to implement generic units for modulo {2n±k}, in the case of modular multiplication it is achieved the same critical path delay and merely 4% of increase on area resources, when compared with the dedicated structure presented in the state-of-art for modulo {2n±3}.

The {2n+ 1, 2n- 1, 2(2n+1)- 3, 2(2n)- 2} moduli set and the respective reverse converter have been recently proposed for supporting Residue Number Systems (RNSs). The reverse converter originally proposed was based on the Chinese Remainder Theorems (CRTs), in particular the commonly called new CRTs, and requires at the end a 6nbit carry propagate adder to compute the binary value. In this paper we propose a more efficient Very-Large-Scale Integration (VLSI) reverse converter for the referred moduli set following a similar approach based on the Mixed-Radix Conversion (MRC). Experimental results show a reduction in the conversion delay of 22% and 17% without impact in the circuit area regarding the related art for a 90 nm ASIC and FPGA technology, respectively.

In this paper, we propose an algorithm for efficient divisible load balancing across all processing devices available in a heterogeneous desktop system. The proposed algorithm allows to achieve simultaneous load balancing at different execution levels, namely between execution subdomains defined with several processing devices, and between devices in each subdomain. Moreover, the algorithm builds partial performance models for each execution subdomain, using the minimal set of approximation points determined during the algorithm run, while converging towards the optimal multi level load distributions. The proposed approach was experimentally evaluated in a real desktop system with a quad core CPU and two GPUs, for matrix multiplication. Experimental results show the ability of the algorithm to provide significant performance improvements with very low scheduling overhead when compared to similar scheduling approaches.

This paper investigates the problem of scheduling discretely divisible applications in highly heterogeneous distributed platforms which deploy modern desktop systems with limited memory as computing nodes. We propose an algorithm for hierarchical load balancing at both inter- and intra-node platform levels which relies on realistic performance models of computation and communication resources. An iterative procedure, based on the proposed algorithm, is also presented for building accurate performance models during the application run-time. The presented approach was evaluated for a 2D FFT batch application executed on a distributed system with four CPU+GPU nodes. The experimental results show the advantages of using the proposed approach by outperforming the "optimal" implementation by at least 4 times on GPU devices.

Acceleration of cryptographic applications on massive parallel computing platforms, such as Graphic Processing Units (GPUs), becomes a real challenge concerning practical implementations. In this paper, we propose a parallel algorithm for Elliptic Curve (EC) point multiplication in order to compute EC cryptography on these platforms. The proposed approach relies on the usage of the Residue Number System (RNS) to extract parallelism on high-precision integer arithmetic. Results suggest a maximum throughput of 9827 EC multiplications per second and minimum latency of 29.2 ms for a 224-bit underlying field, in a commercial Nvidia 285 GTX GPU. Performances up to an order of magnitude better in latency and 122% in throughput are achieved regarding other approaches reported in the related art. An experimental analysis of the scalability, based on OpenCL descriptions of the proposed algorithms, suggest that further advantage can be obtained from the proposed RNS approach for GPUs and EC curves supported by underlying finite fields of smaller size, regarding implementations on general purpose multi-cores.

In this paper Residue Number Systems (RNS) conversion structures from Binary to RNS modulo {2n± 3} are proposed. These structures are based on arithmetic calculations without the need for Lookup Tables as in the related art. Additionally, the required 4:2 and 3:2 Carry-Save Adders (CSA) modulo {2n± 3} are also proposed. Experimental results obtained for an ASIC technology suggest that the presented CSAs, needed in the conversion, improve the related art by reducing the required area resources by 33% and achieving a 1.49× speedup. Experimental results for the proposed conversion units suggest that improvements in performance up to 3 times can be achieved, while reducing the required area resources by 85%.

It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize. Beyond data dependencies that restrict the decoding of a single word, it requires a large number of memory accesses. In this paper we propose parallel algorithms for performing in CPUs the most demanding case of irregular and long length LDPC codes adopted in the Digital Video Broadcasting Satellite 2 (DVB-S2) standard used in data communications. By performing simultaneous multicodeword decoding and adopting special data structures, experimental results show that throughputs superior to 90 Mbps can be achieved when LDPC decoders for the DVB-S2 are implemented in the current CPUs.

Unlike usual VLSI approaches necessary for the computation of intensive Low-Density Parity-Check (LDPC) code decoders, this paper presents flexible software-based LDPC decoders. Algorithms and data structures suitable for parallel computing are proposed in this paper to perform LDPC decoding on multicore architectures. To evaluate the efficiency of the proposed parallel algorithms, LDPC decoders were developed on recent multicores, such as off-the-shelf general-purpose x86 processors, Graphics Processing Units (GPUs), and the CELL Broadband Engine (CELL/B.E.). Challenging restrictions, such as memory access conflicts, latency, coalescence, or unknown behavior of thread and block schedulers, were unraveled and worked out. Experimental results for different code lengths show throughputs in the order of 1 \sim 2 Mbps on the general-purpose multicores, and ranging from 40 Mbps on the GPU to nearly 70 Mbps on the CELL/B.E. The analysis of the obtained results allows to conclude that the CELL/B.E. performs better for short to medium length codes, while the GPU achieves superior throughputs with larger codes. They achieve throughputs that in some cases approach very well those obtained with VLSI decoders. From the analysis of the results, we can predict a throughput increase with the rise of the number of cores.

Acceleration of cryptographic applications on Graphical Processing Units (GPUs) platforms is a research topic with practical interest, because these platforms provide huge computational power for this type of applications. In this paper, we propose a parallel algorithm for Elliptic Curve (EC) point multiplication in order to compute EC cryptography on GPUs. The proposed approach relies in using the Residue Number System (RNS) to extract parallelism on high precision integer arithmetic. Results suggest a maximum throughput of 9990 EC multiplications per second and minimum latency of 24.3 ms for a 224-bit underlying field, for an Nvidia 285 GTX GPU. We present performances up to an order of magnitude better in latency and 122 % in throughput regarding other approaches reported in the related art.

A new moduli set {2n- 1, 2n+ 3, 2n+ 1, 2n- 3} has recently been proposed to represent numbers in Residue Number Systems (RNS), increasing the number of channels. With this, the processing time can be reduced by simultaneously exploiting the carry-free characteristic of the modular arithmetic and improving the parallelism. In this paper, hardware structures for addition and multiplication operation in RNS for the moduli {2n- 3} and {2n+ 3} are proposed and analyzed. In order to evaluate the performance of the proposed units they were implemented on an ASIC technology. The obtained experimental results suggest that the performance of the moduli {2n± 3} are acceptable but demand more area resource and impose a larger delay than the typically used {2n± 1} arithmetic units. Addition units require at least 42% more area for a performance identical to the {2n+ 1} modulo adder. The multiplication units require up to 37% more area and impose a delay 25% higher. This paper also suggests that more balanced moduli sets should be developed in order to achieve more efficient RNS.

The OpenCL framework supports SIMD capabilities available in general purpose processors, which have been used to prospect performance improvements in several applications. In this paper we propose efficient algorithms for linear image processing by exploring the provided SIMD extensions on AMD and Intel processors. The efficiency of the SIMD based computation inferred by the OpenCL compiler is also experimentally evaluated. Starting from a reference algorithm and implementation, several optimizations are proposed that lead to increasingly higher performance figures. Experimental results suggest an average 4-fold performance improvement when the vectorization of the operations is tuned. Furthermore, more than 10 times speedup is suggested by applying efficient data organization. The experimental work and achieved results also suggest that the SIMD based OpenCL implementations provide an average of 1.8 times lower performance than equivalent implementations that directly employ the SIMD intrinsics supported by the Intel Compiler. Moreover, it is shown that real time image processing is achieved when SIMD instructions are used.

In this paper, we propose a novel high speed memoryless reverse converter for the moduli set {22n+1-1, 2n, 2n-1}. First, we simplify the traditional Chinese Remainder Theorem in order to obtain a reverse converter that only requires arithmetic mod-(22n+l-1). Second, we further improve the resulting architecture to obtain a purely adder based reverse converter. The proposed converter has a critical path delay of (7n + 7) Full Adders (FA) while the best state of the art converter for this moduli set requires (10n + 5) FA on the critical path. To validate these results, the converters are implemented in a Standard Cell 0.18-μm CMOS technology and the results assert that, on average, the proposed converter achieves about 19% delay reduction at the expense of less than 3% area increase.

A highly modular and configurable platform for designing parallel H.264 video encoders on multi-core processors is presented. Departing from the H.264/AVC reference software, preliminary optimizations were conducted and new data structures were developed, in order to support the encoder's parallelization and to confer the developed platform with a flexible, user configurable and highly scalable characteristics in what concerns the number of available cores to be used in the target concretization. After a careful assessment using different instantiations of the platform, the experimental results have shown that significant and close to linear speedups in what concerns the achieved frame-rate can be obtained, by simultaneously exploiting the several different parallelization models that are made available by this platform.

To facilitate the design of hardware accelerators we have proposed the adoption of the stream-based computing model and the usage of Graphics Processing Units (GPUs) as prototyping platforms. This model exposes the maximum data parallelism available in the applications and decouples computation from memory accesses. In this paper we go a step further in showing how to use the proposed methodology to accelerate a widely used MrBayes bioinformatics application. In particular, we provide design and implementation procedures and details. We analyze problems faced during the implementation such as the connectivity between the CPU and the FPGA and we provide possible solutions. Experimental results show that our mapping of the stream-based program for the GPU into hardware structures leads to real improvements in performance, scalability and cost. The hardware accelerator allows to reduce the respective processing time up to more that two hundred times while the whole bioinformatics application can run 1.44 faster than by using only the host.

This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo 2n± k. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70% faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date.

This paper presents a very compact and flexible processor to support Elliptic Curve (EC) cryptosystems based on GF(2^m) finite fields. This processor can be customized with a two-level microinstruction hierarchy that allows for customization of both field operations and EC algorithms. It was specially designed to benefit from reconfiguration capabilities to scale arithmetic units for different sizes and to replicate processing units to enhance performance. The flexibility resulting from these characteristics was not found in the related art. The proposed processor was implemented and thoroughly tested in a Xilinx Virtex XC4VSX35, supporting a real EC algorithm for point multiplication for a GF(2^163) field, requiring 1.35ms, and using up to 15 times less area than related implementations.

In this paper we propose to show how signal processing algorithm designers can understand the nuances of multicore computing engines in order to conveniently exploit these powerful devices. This is illustrated by presenting source and channel coding, two fundamental operations in multimedia signal processing. We describe methods and principles to develop parallel signal processing algorithms to compute motion estimation for advanced video coding, and low-density parity-check code decoding for forward error correction in the channel coding context. The paper will consider general purpose multi-core architectures and accelerators such as the Cell/B.E. and graphics processing units. Experimental evaluation of the multi-core systems allows their performance for signal processing applications to be compared side by side with previous hardware dedicated solutions.

We are currently faced with the situation where applications have increasing computational demands and there is a wide selection of parallel processor systems. In this paper we focus on exploiting fine-grain parallelism for a demanding bioinformatics application - MrBayes - and its phylogenetic likelihood functions (PLF) using different architectures. Our experiments compare side-by-side the scalability and performance achieved using general-purpose multi-core processors, the cell/BE, and graphics processor units (GPU). The results indicate that all processors scale well for larger computation and data sets. Also, GPU and Cell/BE processors achieve the best improvement for the parallel code section. Nevertheless, data transfers and the execution of the serial portion of the code are the reasons for their poor overall performance. The general-purpose multi-core processors prove to be simpler to program and provide the best balance between an efficient parallel and serial execution, resulting in the largest speedup.

Due to huge computational requirements, powerful Low-Density Parity-Check (LDPC) error correcting codes, discovered in the early 1960s, have only recently been adopted by emerging communication standards. LDPC decoders are supported by VLSI technology, which delivers good parallel computational power with excellent throughputs, but at the expense of significant costs.

A parallel computer architecture and a distributed software platform for automation and control of general anesthesia is proposed in this paper. The system is a prototype research platform, intended to help on the development, simulation and test of new control algorithms for general anesthesia. It must be safe when used in real tests and flexible enough to allow the integration of new software modules. The system is composed by two computers, with the specific tasks of anesthesia control and process supervision. The platform makes use of TANGO, a specialized framework for distributed control systems, which provides software mechanisms useful to fulfill the project requirements. The architecture and the set of mechanisms proposed in this paper provide a high degree of flexibility to research on control algorithms, while ensuring the safeness of the whole procedure.

With the ever increasing demand for high quality 3D image processing on markets such as cinema and gaming, graphics processing units (GPUs) capabilities have shown tremendous advances. Although GPU-based cluster computing, which uses GPUs as the processing units, is one of the most promising high performance parallel computing platforms, currently there is no programming environment, interface or library designed to use these multiple computing resources to compute tasks in parallel. This paper proposes the CaravelaMPI, a new message passing interface targeted for GPU cluster computing, providing a unified and transparent interface to manage both communication and GPU execution. Experimental results show that the transparent interface of CaravelaMPI allows to efficiently program GPU-based clusters, not only decreasing the required programming effort but also increasing the performance of GPU-based cluster computing platforms.

The new advanced video coding (AVC) standards further exploit temporal correlation between images on a sequence by considering multiple reference frames and variable block sizes. It improves the compression efficiency at the cost of a significant computational load increasing. Specialized hardware processors have been proposed to perform real time motion estimation on AVC, but the non-recurring engineering cost of these solutions is too high. This paper describes a parallel algorithm that exploits the capacity of the current multi-core processors to implement real time motion estimation for AVC. In particular, by using the computational capacity and the fast memory system of the heterogeneous multicore CELL processor, synergistic processors can be used to speedup motion estimation while the main processor execute in parallel the other parts of the AVC system. Experimental results show that motion estimation can be performed in less than 40 ms per frame, for CIF video format, up to 5 reference frames, and variable block size, by programming the proposed parallel algorithm to the CELL processor.

This paper presents an improved hardware structure for the computation of the Whirlpool hash function. By merging the round key computation with the data compression and by using embedded memories to perform part of the Galois Field (2s) multiplication, a core can be implemented in just 43% of the area of the best current related art while achieving a 12% higher throughput. The proposed core improves the Throughput per Slice compared to the state of the art by 160%, achieving a throughput of 5.47 Gbit/s with 2110 slices and 32 BRAMs on a VIRTEX II Pro FPGA. Results for a real application are also presented by considering a polymorphic computational approach.

The sum of absolute differences (SAD) is a distance metric commonly used to determine the similarity between two data sets. A very recent method for directly comparing the magnitude of two numbers represented in residue number systems (RNS) leads to the possibility of using modular arithmetic to compute the SAD. In this paper we propose an efficient hardware SAD unit that computes this Manhattan distance independently of each RNS channel. Therefore, the processing time can be reduced by simultaneously exploiting the carry-free characteristic of the modular arithmetic and the new method proposed by the authors of this paper to compare the magnitude of numbers in RNS. The proposed architecture is suitable to implement SAD units in application specific integrated circuit (ASIC) and in field programmable gate array (FPGA). In order to evaluate the performance of the proposed structures a hardware processor for computing the minimum SAD was implemented in a FPGA and ASIC. From the experimental results it was possible to obtain operating frequencies above 200 MHz for XILINX FPGAs XC2VP50-7 and XC4VLX80-12, and 300 MHz for the ASIC implementation. These results allow the implementation of real-time motion estimators for high resolution images according to the most recent standards for video coding.

The implementation of a recently proposed IP core of an efficient motion estimation co-processor is considered. Some significant functional improvements to the base architecture are proposed, as well as the presentation of a detailed description of the interfacing between the co-processor and the main processing unit of the video encoding system. Then, a performance analysis of two distinct implementations of this IP core is presented, considering two different target technologies: a high performance FPGA device, from the Xilinx Virtex-II Pro family, and an ASIC based implementation, using a 0.18um CMOS StdCell library. Experimental results have shown that the two alternative implementations have quite similar performance levels and allow the estimation of motion vectors in real-time.

This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfigurable device is described by a binary bitstream, the hash value of this bitstream can be calculated to validate the hardware structure. To optimize this attestation, the hash value computation is implemented in hardware on the FPGA itself. To guarantee the integrity of the existing computation architecture, the proposed hardware module also enforces region delimitation. With the region delimitation, only the regions intended to be reconfigured can be modified. Implementation results suggest that this bitstream attestation can be performed without imposing an extra delay to the reconfigurable process and at an area cost of less that 10% of a Virtex II Pro 30 FPGA device.

In this paper a processor that supports elliptic curve cryptographic applications over GF (2m) is proposed. The proposed structure is capable of calculating point multiplication and addition using a single coordinate to contain the point information. This compression allows for a better usage of the bandwidth resources. For the point multiplication procedure, all coordinate pre-calculations are completely avoided. This design was successful prototyped on a reconfigurable device for the field GF (2163). Experimental results suggest that point multiplication can be performed in 144 mus and point affine addition in 1.02 mus. Comparing with the related work, a 5 times speedup is obtained for point addition and multiplication. The presented design offers a well balanced area-time performance when compared with existent elliptic curve point multiplication specific processors.

The Caravela platform has been designed to develop a parallel and distributed stream-based computing paradigm, namely supported on the pipeline processing approach herein designated by meta-pipeline. This paper is focused on the design and implementation of a modeling tool for the meta-pipeline, namely to tackle the deadlock problem due to uninitialized input data stream in a pipeline-model. A new efficient algorithm is proposed to prevent deadlock situations by detecting uninitialized edges in a pipeline graph. The algorithm identifies the cyclic paths in a pipeline-graph and builds a reduced list with only the true cyclic paths that have to be really initialized. Further optimization techniques are also proposed to reduce the computation time and the required amount of memory. Moreover, this paper also presents a Graphical User Interface (GUI) for easy programming meta-pipeline applications, which provides an automatic validation procedure based on the proposed algorithm. Experimental results presented in this paper show the effectiveness of both the proposed algorithm and the developed GUI.

Computer architecture simulation and modeling require a huge amount of time and resources, not only for the simulation itself but also regarding the configuration and submission procedures. A quite common simulation toolset (SimpleScalar) has been used to model a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies. In this paper we propose a platform for automatically executing a massive number of simulations in parallel, by exploiting a distributed computing approach. We developed a Web-based simulation system consisting in a front-end user interface and a back-end part supported on a grid system. The front-end is responsible for configuring the simulation and parsing the results, while the back-end distributes the workload by using Condor scheduler. Experimental results show that it is very easy to use the system, even when dealing with a huge number of simulations, and also it provides results in a very suitable format. Moreover, it has been concluded that a significant speedup can be achieved, by exploiting parallelism at the benchmark levels or also by sampling each benchmark with the SimPoint tool.

Due to the demand of high definition graphics presentation in gaming and video market, graphics processing units (GPUs) have drastically increased their computational capacities. General-purpose computation on GPUs uses the fragment shader multicore of these processing units to concurrently process data streams. However, the I/O overheads in recursive GPGPU applications have a negative impact in the performance of those systems. This paper proposes the remap method to improve the performance of general purpose recursive applications on GPUs, by decreasing the I/O overheads imposed by the VRAM/GPU interface. It is shown that significant performance improvements are achieved by applying the remap method to realistic recursive applications.

Low-Density Parity-Check (LDPC) codes are among the best error correcting codes known and have been adopted by data transmission standards, such as DVB-S2 or WiMax. They are based on binary sparse parity check matrices and usually represented by Tanner graphs. LDPC decoders require very intensive message-passing algorithms, also known as belief propagation. This paper proposes a very compact stream-based data structure to represent such a bipartite Tanner graph, which supports both regular and irregular codes. This compact data structure not only reduces the memory required to represent the graph but also puts it in an appropriate format to gather data into streams. This representation also allows to map the irregular processing behavior of the Sum Product Algorithm (SPA) used in LDPC decoding into the stream-based computing model. Stream programs were developed for LDPC decoding and the results show significant speedups obtained either using general purpose processors, or graphics processing units. The simultaneous decoding of several codewords was performed using the SIMD capabilities of modern stream-based architectures available on recent processing units.

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes (ECC). They have recently been adopted by several data communication standards such as DVB-S2 and WiMax. LDPCs are represented by bipartite graphs, also called Tanner graphs, and their decoding demands very intensive computation. For that reason, VLSI dedicated architectures have been investigated and developed over the last few years. This paper proposes a new approach for LDPC decoding on graphics processing units (GPUs). Efficient data structures and an new algorithm are proposed to represent the Tanner graph and to perform LDPC decoding according to the stream-based computing model. GPUs were programmed to efficiently implement the proposed algorithms by applying data-parallel intensive computing. Experimental results show that GPUs perform LDPC decoding nearly three orders of magnitude faster than modern CPUs. Moreover, they lead to the conclusion that GPUs with their tremendous processing power can be considered as a consistent alternative to state-of-the-art hardware LDPC decoders.

Several spike train metrics have been proposed in the last years for the evaluation of neural responses. In this letter, we perform deep statistical analysis on an important metric. This metric evaluates the dissimilarity between spike trains by applying a linear filter on the trains and then integrating the squared difference of the result. The statistical analysis is made when the metric is used to evaluate spike trains originated from nonhomogenous Poisson processes. Contrary to previous works, the analytical results have been obtained for the general case and not only for particular limiting conditions. By computing the expected value of the metric, insightful information is retrieved; it allows for the proposal of a normalization factor which addresses several deficiencies when comparing neural responses.

This paper presents a new set of techniques for hardware implementations of secure hash algorithm (SHA) hash functions. These techniques consist mostly in operation rescheduling and hardware reutilization, therefore, significantly decreasing the critical path and required area. Throughputs from 1.3 Gbit/s to 1.8 Gbit/s were obtained for the SHA implementations on a Xilinx VIRTEX II Pro. Compared to commercial cores and previously published research, these figures correspond to an improvement in throughput/slice in the range of 29% to 59% for SHA-1 and 54% to 100% for SHA-2. Experimental results on hybrid hardware/software implementations of the SHA cores, have shown speedups up to 150 times for the proposed cores, compared to pure software implementations.

The non-positional nature of residue number systems (RNS) is very useful to achieve carry free arithmetic. However it makes the comparison of numbers more difficult than in the traditional weighted number systems: there is no any efficient general method for magnitude comparison in RNS. Moreover, magnitude comparison for RNS that rely on pairs of conjugate moduli, which are not relatively prime moduli sets recently proposed because of the large dynamic ranges and the simplicity of the arithmetic units, is a new unsolved problem. In this paper an efficient method and a VLSI architecture is proposed for magnitude comparison in RNS based on sets formed by two pairs of conjugate moduli. This proposed method is much more efficient than the other known ones and is the only one valid for moduli sets not formed by relatively prime integers. The method has been applied to design a very fast Sum-of-Absolute Differences (SAD) unit for motion estimation in video sequences that performs the function entirely within the RNS channels. Experimental results show that this new SAD unit, implemented in the internal memory blocks of the xc2vp50-7 FPGA, is capable of achieving the high throughput required to perform real-time motion estimation in high resolution images.

Motion estimation is the central operation and simultaneously the most computational intensive step in video encoding. Fast block matching motion estimation search algorithms iteratively use different search patterns, making their implementation in hardware difficult. This paper proposes a new mechanism and a new architecture, in order to implement an hardware motion estimation processor that supports most of the existing fast search algorithms. Experimental results in FPGAs show that the proposed motion estimator is able to reconfigure itself between two consecutive blocks, allowing the search algorithm to adapt according to the features of frames and perform motion estimation in real time on CIF images.

The accurate modelling of the human visual system, particularly of the retina, would be a great achievement and a big step in the development of visual prostheses. Several methods and algorithms have been proposed to accomplish such a difficult task, mainly to what concerns the adaptation and nonlinear mechanisms of the retina. This paper presents the results obtained by the employment of additive logistic regression techniques to model the nonlinear block of a canonical Linear-Nonlinear-Poisson retina model, considering the spike triggering process from a statistical point of view, complemented with the PCA of the stimuli covariance matrix. The displayed results were obtained by modelling real retina data using different forms for the nonlinear block and are assessed with different error measures.

This paper presents a recently developed handheld biochip-based microsystem. The microsystem is based on a magneto-resistive array biochip composed of a number of sensing sites with magnetic tunneling junctions (MTJ) and diodes. To drive the MTJ, different techniques are addressed with different types of signals. Filtering strategies are also presented, which allow the recovery of bio signals from the noise without increasing too much nor the time required to access all the sensors, nor the power consumption of the board. In conclusion, experiments with the system in a setup to detect actual bio signals are presented with encouraging results.

The Caravela platform has been proposed by the authors of this paper to perform distributed stream-based computing on general purpose computation. This platform uses a secured execution unit called flow-model that prevents remote users to touch local information in a computer. The flow-model is assigned to local or remote processing units that execute its program. This paper is focused on a new execution mechanism that defines a pipeline composed by flow-models, called meta-pipeline, and is designed as a set of additional functions of the Caravela platform. The pipeline is executed automatically by the meta-pipeline runtime environment. This paper describes the execution mechanism and also presents an application example.

Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. With the proliferation of portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application specific instruction set processor (ASIP) to implement data-adaptive motion estimation algorithms, that is characterized by a specialized data-path and minimum and optimized instruction set. Due to its low-power nature, this architecture is specially adequate to develop motion estimators for portable, mobile and battery supplied devices. A cycle-based accurate simulator was also developed for the proposed ASIP and fast and data-adaptive search algorithms have been implemented, namely, the four-step search and the motion vector field adaptive search algorithms. Based on the proposed ASIP and the considered adaptive algorithms, several motion estimators were synthesized in 0.13mum CMOS technology. Experimental results show that very-low power adaptive motion estimators have been achieved to encode QCIF video sequences

We consider the AES encryption/decryption algorithm and propose a memory based hardware design to support it. The proposed implementation is mapped on the Xilinx Virtex II Pro technology. Both the byte substitution and the polynomial multiplication of the AES algorithm are implemented in a single dual port on-chip memory block (BRAM). Two AES encryption/decryption cores have been designed and implemented on a prototyping XC2VP20-7 FPGA: a completely unrolled loop structure capable of achieving a throughput above 34 Gbits/s, with an implementation cost of 3513 slices and 80 BRAMs; and a fully folded structure, requiring only 515 slices and 12 BRAMs, capable of a throughput above 2 Gbits/s. To evaluate the proposed AES design, it has been embedded in a polymorphic processor organization, as a reconfigurable co-processor. Comparisons to state-of-the-art AES cores indicate that the proposed unfolded core outperforms the most recent works by 34% in throughput and requires 68% less reconfigurable area. Experimental results of both folded and unfolded AES cores suggest over 560% improvement in the throughput/slice metric when compared to the recent AES related art

Task scheduling is an important aspect of parallel programming. Most of the heuristics for this NP-hard problem are based on a very simple system model of the target parallel system. Experiments revealed the inappropriateness of this classic model to obtain accurate and efficient schedules for real-systems. In order to overcome this shortcoming, a new scheduling model was proposed that considers the contention for communication resources. Even though the accuracy and efficiency improved with the consideration of contention, the new contention model is still not good enough. The crucial aspect is the involvement of the processor in communication. This paper investigates the involvement of the processor in communication and its impact on task scheduling. A new system model is proposed based on the contention model that is aware of the processor involvement. The challenges for the scheduling techniques are analyzed and two scheduling algorithms are proposed. Experiments on real parallel systems show the significantly improved accuracy and efficiency of the new model and algorithms.

We introduce the midlfekicker metric for evaluating microarchitectures mostly during the design process. We assume a microarchitecture designed at a time T-1 and estimate if a new microarchitecture projected for time T has advantages over the microarchitecture designed at T-1 and remapped on the same technology at time T. We consider that microarchitects minimize the product cycles per instruction (CPI) x cycle time and estimate performance based on CPI with a soft-threshold to include cycle time product effects. Some measurements are also reported.

A new compressed domain motion estimation algorithm that makes use of the DCT coefficients directly obtained from the H.26x or MPEG-x video stream is presented. The proposed algorithm is based on an iterative scheme that computes the new motion vectors by applying a least squares estimation technique. To reduce its computational effort, the algorithm may consider only an arbitrary subset of non-null DCT coefficients. The performance of the algorithm was assessed in a DCT domain H.263 video transcoder, where the obtained motion vectors provided the means to significantly enhance the quality of the temporal prediction scheme with a consequent reduction of the required bit-rate.

The support on cluster environments of "legacy protocols" is important to avoid rewriting the code of applications, but this support should not prevent to achieve the maximum communication performance. This paper addresses this issue by implementing the Berkeley sockets interface over the MMP message passing protocol, which is the lower layer of the Maestro2 cluster communication network. Experimental results show that MMP-Sockets offers a minimum latency of 25ìs and a maximum throughput of 1250Mbps. These values correspond to a relative increase of 80% for the latency and a decrease of about 30% for the throughput, regarding to a communication based only on MMP. However, MMP-Sockets increases the compatibility and portability of developed applications.

Task scheduling is an essential aspect of parallel programming. Most heuristics for this NP-hard problem are based on a simple system model that assumes fully connected processors and concurrent interprocessor communication. Hence, contention for communication resources is not considered in task scheduling, yet it has a strong influence on the execution time of a parallel program. This paper investigates the incorporation of contention awareness into task scheduling. A new system model for task scheduling is proposed, allowing us to capture both end-point and network contention. To achieve this, the communication network is reflected by a topology graph for the representation of arbitrary static and dynamic networks. The contention awareness is accomplished by scheduling the communications, represented by the edges in the task graph, onto the links of the topology graph. Edge scheduling is theoretically analyzed, including aspects like heterogeneity, routing, and causality. The proposed contention-aware scheduling preserves the theoretical basis of task scheduling. It is shown how classic list scheduling is easily extended to this more accurate system model. Experimental results show the significantly improved accuracy and efficiency of the produced schedules.

The increasing usage of residual number system (RNS) in signal processing applications demands the development of new and more adaptable RNS moduli sets and arithmetic units. This paper presents a new adaptable moduli set extension for the traditional moduli set {2/sup n/ + 1, 2/sup n/, 2/sup n/ - 1}. As it will be shown, this new moduli set extension ({2/sup n/ + 1, 2/sup n+k/, 2/sup n/ - 1}) allows the balancing of the binary channel (2/sup n+k/) in relation to the other two channels. Moreover, it does not require the development of new addition and multiplication units, since it is possible to reuse the already developed and well studied units for these moduli operations.

Cluster computers have become the vehicle of choice to build high performance computing environments. To fully exploit the computing power of these environments, one must utilize high performance network and protocol technologies, since the communication patterns of parallel applications running on clusters require low latency and high throughput, not achievable by using off-the-shell network technologies. We have developed a technology to build high performance network equipment, called MaestroS. This paper describes the novel techniques used by Maestro2 to extract maximum performance from the physical medium and studies the impact of software-level parameters. The results obtained clearly show that Maestro2 is a promising technology, presenting very good results both in terms of latency and throughput. The results also show the large impact of software overhead in the overall performance of the system and validate the need for optimized communication libraries for high performance computing.

This paper is focused on low power programmable fast digital signal processors (DSP) design based on a configurable 5-stage RISC core architecture and on residue number systems (RNS). Several innovative aspects are introduced at the control and datapath architecture levels, which support both the binary system and the RNS. A new moduli set {2/sup n/-1, 2/sup 2n/, 2/sup n/+1} is also proposed for balancing the processing time in the different RNS channels. Experimental results, obtained trough RDSP implementation on FPGA and ASIC, show that not only a significant reduction in circuit area and power consumption but also a speedup may be achieved with RNS when compared with a binary DSP.

Efficient VLSI architectures for motion estimation using the full-search block-matching algorithm are proposed in this paper. These structures are based on an improved and more efficient two-dimensional single-array architecture with minimum latency, maximum throughput, and full utilization of the hardware resources. This optimized architecture is extended to a class of fully parameterizable multiple array architectures that combine both pipelining and parallel processing techniques and provide the ability to configure the processors according to the setup parameters, the processing time and the circuit area specified limits. The development of a single-array processor in a single-chip based on a 0.25-/spl mu/m CMOS technology process proves the practical interest of the proposed architecture for implementing real-time motion estimators.

In this paper we introduce the concept of conditional processing and discuss its application to the development of low-power systolic architectures for full search-block matching (FS-BM) motion estimation. We prove that the intermediate results sequentially generated with FS-BM systolic algorithms can be used to design efficient low-power array architectures based on conditional processing. Simulation results on benchmark video sequences show that the power consumption of FS-BM processors is significantly reduced with the proposed architectures.

This paper proposes new efficient low-power systolic architectures for full search-block matching (FS-BM) motion estimation. These architectures allow one to eliminate unnecessary computations, reducing the power consumption while preserving the optimal solution and the throughput. The new and traditional systolic architectures for motion estimation are compared with respect to required hardware and power consumption.

The authors propose a new orthogonal partially shared memory architecture for the design of multiprocessor systems. The architecture allows processors to partially share a 2-D array of memory modules in an orthogonal way with fewer limitations than those imposed by the traditional orthogonal (OMP) architecture. Processors have direct access to large neighborhoods of memory modules which can be used to improve processing efficiency, namely with respect to local processing. The main characteristics of the new architecture are described and compared with the traditional orthogonal architecture. Image processing algorithms have been mapped onto the new architecture, in order to evaluate its efficiency for local processing. The fault tolerant characteristics of the system are also discussed.