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Mark Smotherman

dblp:s/MarkSmotherman · also John Mark Smotherman · DBLP profile ↗
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10ranked-venue papers
6as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 4 first-authorHuman-computer interaction and ubiquitous computing · 3 · 2 first-authorTheory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Processor architecture and microarchitecture · 74% Memory systems · 17% Hardware reliability and fault tolerance · 6%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%

Topics — the 14 heaviest of 16, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache design
fill unit
0.021995
Improving CISC instruction decoding performance using a fill unit · MICRO 1995
A fill-unit approach to multiple instruction issue · MICRO 1994
Processor architecture and microarchitecture
instruction-level parallelism
0.021994
A fill-unit approach to multiple instruction issue · MICRO 1994
Instruction scheduling for the Motorola 88110 · MICRO 1993
Compilers and program optimization
instruction scheduling
0.021993
Instruction scheduling for the Motorola 88110 · MICRO 1993
Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling · MICRO 1991
Processor architecture and microarchitecture › instruction fetch
decoded instruction cache
0.011995
Improving CISC instruction decoding performance using a fill unit · MICRO 1995
Processor architecture and microarchitecture › front-end
instruction decoding
0.011995
Improving CISC instruction decoding performance using a fill unit · MICRO 1995
Processor architecture and microarchitecture › front-end
instruction fetch and decode
0.011995
Improving CISC instruction decoding performance using a fill unit · MICRO 1995
Processor architecture and microarchitecture
branch prediction
0.011994
A fill-unit approach to multiple instruction issue · MICRO 1994
Processor architecture and microarchitecture › instruction-level parallelism
multiple instruction issue
0.011994
A fill-unit approach to multiple instruction issue · MICRO 1994
Processor architecture and microarchitecture
speculative execution
0.011994
A fill-unit approach to multiple instruction issue · MICRO 1994
Hardware reliability and fault tolerance
reliability modeling
0.021986
Provably Conservative Approximations to Complex Reliability Models · IEEE Trans. Computers 1986
The Conservativeness of Reliability Estimates Based on Instantaneous Coverage · IEEE Trans. Computers 1985
Processor architecture and microarchitecture › out-of-order execution
register renaming
0.011995
Improving CISC instruction decoding performance using a fill unit · MICRO 1995
Processor architecture and microarchitecture
instruction set architecture
0.011994
A fill-unit approach to multiple instruction issue · MICRO 1994
Processor architecture and microarchitecture › instruction-level parallelism
VLIW
0.011994
A fill-unit approach to multiple instruction issue · MICRO 1994
Performance modeling and evaluation › statistical analysis
sensitivity analysis
0.011986
Provably Conservative Approximations to Complex Reliability Models · IEEE Trans. Computers 1986

Methods — techniques the papers use, named apart from their topics

table lookup · 0.0deterministic finite automaton · 0.0trace compaction · 0.0dynamic instruction scheduling · 0.0state space reduction · 0.0markov reliability modeling · 0.0coverage probability estimation · 0.0
YearPublicationVenuePosition
1995 Improving CISC instruction decoding performance using a fill unit
abstract
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions can sometimes provide reduced fetch bandwidth requirements, they are correspondingly more difficult to decode. A hardware assist, called a fill unit, can dynamically collect decoded microoperations into a decoded instruction cache. Future code fetches to those locations can be satisfied out of this cache and thus bypass the decoding logic. This approach is investigated using the Intel x86 architecture, and a speedup of approximately a factor of two over a P6-like decoding structure is seen for the three SPEC benchmarks investigated. This design is accompanied by a microengine-register allocation and renaming scheme that prevents the increased supply of microoperations from placing excessive demands on the normal register renaming hardware.
Mark Smotherman, Manoj Franklin
MICRO1
1994 A fill-unit approach to multiple instruction issue
abstract
Multiple issue of instructions occurs in superscalar and VLIW machines. The paper investigates a third type of machine design, which combines the advantages of code compatibility as in superscalars and the absence of complex dependency-checking logic from the decoder as in VLIW. In this design, a stream of scalar instructions is executed by the hardware and is simultaneously compacted into VLIW-type instructions, which are then stored in a structure called a shadow cache. When a shadow cache line contains the instructions requested by the fetch unit, the scalar instruction stream is preempted and all operations in the shadow cache line are simultaneously issued and executed. The mechanism that compacts instructions is called a fill unit, and was first proposed for dynamically compacting macrooperations into large executable units by Melvin, Shebanow, and Patt in 1988. We have extended their approach to directly handle data dependencies, delayed branches, and speculative execution (using branch prediction). This approach is evaluated using the MIPS architecture, and a six-functional-unit machine is found to be 52 to 108% faster than a single-issue processor for unrecompiled SPECint92 benchmarks.
Manoj Franklin, Mark Smotherman
MICRO2
1993 Instruction scheduling for the Motorola 88110
abstract
Static instruction scheduling is an important optimization to exploit instruction level parallelism. If the scheduler has to consider resource constraints to prevent structural hazards, usually the processor timing is simulated by overlaying binary matrices representing the resource usage of instructions. This technique is rather time consuming. It is shown that the timing can be simulated by a deterministic finite automaton and the matrix operations for a simulation step are replaced by two table lookups. A prototype implementation shows that about an eighteenfold speedup of the simulation can be expected. This performance gain can be used either to speed up existing scheduling algorithms or to use more complex algorithms to improve scheduling results.>
Mark Smotherman, Shuchi Chawla 0002, Stan Cox, Brian A. Malloy
MICRO1
1991 Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling
Mark Smotherman, Sanjay Krishnamurthy, P. S. Aravind, David Hunnicutt
MICRO1
1989 Examining compiled code
abstract
The use of annotated listings of compiler-generated code has the potential to make teaching more effective in several different courses.We consider the production of such listings for several popular compilers and computer systems, including Turbo Pascal on MS-DOS machines and Pascal on Ultrix and VMS systems.The usefulness of these listings in assembly language, computer organization/architecture, and compiler courses, as well as in introductory courses, is also considered.
Mark Smotherman
SIGCSE1
1988 Assembly language courses in transition
abstract
Although the CS 3 course of the ACM Curriculum '78 was defined almost a decade ago, the broader perspectives that are desired for that course have not been present in many undergraduate programs. Only recently has the pivotal role of this course begun to attract the attention of computer science faculties. This development is prompted by the increasing awareness in our profession of the need to convey basic principles along with programming skills in introductory courses, and is accompanied by the increasing availability of more well-rounded textbooks. This paper describes the transition at Clemson University from a skills-oriented “assembly language course” to a principles-oriented “introduction to computer systems” course. The course that has resulted will better prepare students for subsequent studies in languages, operating systems, and applications support software.
R. Rainey Little, Mark Smotherman
SIGCSE2
1987 On the use of naming and binding in early courses
abstract
In most computer science curricula, the concepts of naming and binding are explicitly treated only in a small number of the later courses, such as operating systems and programming language foundations. However, these concepts are fundamental and underlie the whole of computer science. In this paper, a proposal is made to explicitly introduce these concepts in the second or third course so that they may be used in the analysis of ideas encountered throughout a student's program of study. The benefit of this earlier introduction is demonstrated by detailing how a computer organization course can explicitly incorporate these concepts. These concepts can also be used to advantage in other early courses, such as data structures.
Mark Smotherman
SIGCSE1
1986 The Reliability of Life-Critical Computer Systems
Robert Geist, Mark Smotherman, Kishor S. Trivedi, Joanne Bechta Dugan
Acta Informatica2
1986 Provably Conservative Approximations to Complex Reliability Models
abstract
Provably conservative (and optimistic) reliability models can be systematically derived from more complex models. These derived models incorporate a reduced state space and fewer transitions, and, therefore, have solutions that are more cost- effective than those of the original complex models. The designer can extensively explore the design space without incurring the expense of solving multiple complex models. A conservative- optimistic pair of derived models produces a band that includes the solution to the complex model. Sensitivity analysis can be performed on this pair of models to determine those parameters of the original model that are most sensitive to change (i.e., uncertainty) and hence warrant further expense in obtaining tighter specifications.
Mark Smotherman, Robert Geist, Kishor S. Trivedi
IEEE Trans. Computers1
1985 The Conservativeness of Reliability Estimates Based on Instantaneous Coverage
abstract
In order to remain tractable, mhany reliability models do not include the states and transitions necessary to represent fault/error-handling details. Instead, the effectiveness of fault/ error-handling mechanisms is represented by the use of instantaneous coverage probabilities. This paper investigates the effect of the error introduced by the assumption of instantaneous coverage probabilities on the predictions of the reliability model, and it shows that the reliability estimates thus obtained are lower bounds on the reliability estimates of the composite model with embedded fault/error-handling states and transitions. The paper also discusses the choice of the calculation method for the instantaneous coverage probabilities and defines a near-coincident-fault coverage model that yields conservative instantaneous coverage probabilities.
John McGough, Mark Smotherman, Kishor S. Trivedi
IEEE Trans. Computers2