Although wake-up power-supply noise (PSN) leaves a more profound mark on IC performance than run-time PSN, it has received little attention in contemporary studies. This article addresses this gap by presenting a comprehensive mathematical model of wake-up PSN and introducing a novel strategy to temporally spread its impact via frequency modulation during the IC's sleep-to-active transition. Bringing this concept to reality, a framework of Sweeping Variable-Frequency Clock (SVFC) synthesis was realized in SCL 180 nm CMOS. Rigorous postlayout simulations on Cadence Virtuoso at a supply of 1.8 Volt reveal its finesse-achieving sub-10ps jitter and nearly 50% consistent pulse width across all frequencies and all process corners. Finally, benchmark analyses under DIP-40 package model substantiate the effectiveness of the approach with an average 63.6% improvement in wake-up PSN and 65.7% current and power savings across circuits under test, demonstrating a pathway to mitigate wake-up PSN and enhance IC reliability.

This research presents a novel approach for implementing an artificial neural network using an analog hardware architecture. The core components of this architecture consist of current-mode circuits, which represent the class, and a voltage-mode comparator. All current-mode circuits are designed to operate with minimal bias current. For the voltage comparator, which handles the final decision-making process, a low-voltage amplifier is utilized. The operational principles of the architecture are thoroughly detailed and applied in a power-efficient configuration, operating at sub-microWatt levels with low power supply rails (0.6 V). The proposed design is validated on real-world biomedical classification tasks, achieving impressive classification accuracy exceeding 93%. The implementation is realized using a 90nm CMOS process and developed within the Cadence IC Suite for both schematic and layout design. To ensure the robustness of the proposed classifier, Monte Carlo analysis, covering both process variations and mismatches, as well as corner analysis, are conducted. A comparative analysis of the post-layout simulation results with an equivalent software-based classifier and relevant literature confirms the effective performance of the proposed architecture.

In this article, a framework for the analog implementation of a deep convolutional neural network (CNN) is introduced and used to derive a new circuit architecture which is composed of an improved analog multiplier and circuit blocks implementing the ReLU activation function and the argmax operator. The operating principles of the individual blocks, as well as those of the complete architecture, are analyzed and used to realize a low-power analog classifier, consuming less than$1.8~\mu \text {W}$. The proper operation of the classifier is verified via a comparison with a software equivalent implementation and its performance is evaluated against existing circuit architectures. The proposed architecture is implemented in a TSMC 90-nm CMOS process and simulated using Cadence IC Suite for both schematic and layout design. Corner and Monte Carlo mismatch simulations of the schematic and the physical circuit (postlayout) were conducted to evaluate the effect of transistor mismatches and process voltage temperature (PVT) variations and to showcase a proposed systematic method for offsetting their effect.

BACKGROUND: Antimicrobial resistance is a major public health threat, and new agents are needed. Computational approaches have been proposed to reduce the cost and time needed for compound screening. AIMS: A machine learning (ML) model was developed for the in silico screening of low molecular weight molecules. METHODS: We used the results of a high-throughput Caenorhabditis elegans methicillin-resistant Staphylococcus aureus (MRSA) liquid infection assay to develop ML models for compound prioritization and quality control. RESULTS: The compound prioritization model achieved an AUC of 0.795 with a sensitivity of 81% and a specificity of 70%. When applied to a validation set of 22,768 compounds, the model identified 81% of the active compounds identified by high-throughput screening (HTS) among only 30.6% of the total 22,768 compounds, resulting in a 2.67-fold increase in hit rate. When we retrained the model on all the compounds of the HTS dataset, it further identified 45 discordant molecules classified as non-hits by the HTS, with 42/45 (93%) having known antimicrobial activity. CONCLUSION: Our ML approach can be used to increase HTS efficiency by reducing the number of compounds that need to be physically screened and identifying potential missed hits, making HTS more accessible and reducing barriers to entry.

This study introduces a design methodology pertaining to analog hardware architecture for the implementation of the learning vector quantization (LVQ) algorithm. It consists of three main approaches that are separated based on the distance calculation circuit (DCC) and, more specifically; Euclidean distance, Sigmoid function, and Squarer circuits. The main building blocks of each approach are the DCC and the current comparator (CC). The operational principles of the architecture are extensively elucidated and put into practice through a power-efficient configuration (operating less than 650 nW) within a low-voltage setup (0.6 V). Each specific implementation is tested on a brain tumor classification task achieving more than 96.00% classification accuracy. The designs are realized using a 90-nm CMOS process and developed utilizing the Cadence IC Suite for both schematic and physical design. Through a comparative analysis of postlayout simulation outcomes with an equivalent software-based classifier and related works, the accuracy of the applied modeling and design methodologies is validated.

The so far dominant Von Neumann architecture is being challenged by the energy demanding communication bottle-neck between processing and memory units. To address this issue, in-memory computing is employed for their co-location, with memristive crossbar arrays playing an important role towards this goal. Motivated by the above, this work introduces a timing-based programming of a memristor crossbar array for sequence generation in Stochastic Computing (SC). Its operation principle is based on the stochastic nature of the memristor devices forming the crossbar array, where their programming is regulated by the switching probability that follows the Poisson distribution, controlled by pulse amplitude and duration. The timing-based programming of the proposed crossbar array increases the discretization levels of the output probability values, thereby offering more accurate control when compared to programming schemes that consider only the pulse amplitude. The memristor's stochasticity along with the crossbar's inherent parallelism opens the in-memory design space allowing SC elements to be used as sequences are generated efficiently. Simulation results on different programming pulse-width precisions highlight the proposed crossbar's effectiveness in sequence generation, supported by mean absolute error (MAE) results in a standard SC arithmetic operation. Process variations stemming from the crossbar array affecting the sequence generation in SC are investigated.

A general methodology to derive analytically the statistical properties of stochastic computing finite-state machines (SFSMs) is introduced. The SFSMs, expressed as Moore ones, are modeled using Markov Chains (MCs), enabling the derivation in closed form of their output sequences’ statistical properties, including their expected value, their auto- and cross-correlation, their auto- and cross-covariance, their variance and standard deviation as well as their mean squared error. An MC overflow/underflow probability model accompanies the methodology, allowing to calculate analytically the expected number of steps before overflows/underflows, setting the guidelines to select the register’s size that reduces erroneous bits originating from them. In the proposed methodology both the input sequence length and the number of the SFSMs’ states are considered as parameters, accelerating the overall design procedure as the necessity for multiple time-consuming numerical simulations is eliminated. The proposed methodology’s accurate modeling capabilities are demonstrated with its application in two SFSMs selected from the stochastic computing literature, while comparisons with the numerical experiments justify its correctness.

Electrical Impedance Tomography (EIT) is a developing medical imaging technique which derives the conductivity distribution of a subject with significant temporal resolution. Despite the recent advances in both EIT reconstruction algorithms and hardware, the limited spatial resolution, i.e. low distinguishability between the inclusions, and the presence of artifacts remain the main issues. To address them, block sparse Bayesian learning (BSBL) frameworks have been adopted in EIT, based on the assumption of block-structured inclusions and using minimization of a Bayesian-form cost function in an unsupervised learning manner. To further improve the imaging quality and to enhance convergence speed we combine a Bound-Optimization (BO) and a weighted BSBL approach, introducing priorily estimated weights obtained by a single-step approach, to each block's hyperparameter estimation. Simulations based on 2D circular domains and evaluation using experimental and in-vivo data verify the proposed method's performance compared to traditional regularization and BSBL approaches.

A local constrained multiobjective Bayesian optimization (LoCoMOBO) method is introduced to address automatic sizing and tradeoff exploration for analog and RF integrated circuits (ICs). LoCoMOBO applies to constrained optimization problems utilizing multiple Gaussian process (GP) models that approximate the objective and constraint functions locally in the search space. It searches for potential pareto optimal solutions within trust regions of the search space using only a few time-consuming simulations. The trust regions are adaptively updated during the optimization process based on feasibility and hypervolume metrics. In contrast to mainstream Bayesian optimization approaches, LoCoMOBO uses a new acquisition function that can provide multiple query points, therefore allowing for parallel execution of costly simulations. GP inference is also enhanced by using GPU acceleration in order to handle highly constrained problems that require large sample budgets. Combined with a framework for schematic parametrization and simulator calls, LoCoMOBO provides improved performance tradeoffs and sizing results on three real-world circuit examples, while reducing the total runtime up to$\times 43$times compared to state-of-the-art methods.

This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate Gaussian Process (GP) models approximating the objective and constraint functions locally in the search space. Unlike mainstream BO approaches, it is able to traverse high dimensional problems with ease and provide multiple query points for parallel evaluation. To extend the method to large sample budgets, GP regression and sampling are enhanced by using kernel approximations and GPU acceleration. Experimental results demonstrate that the proposed method finds better solutions within given budgets of total evaluations compared to state-of-the-art approaches.

This article presents a general, time-domain harmonic distortion estimation method, applicable to linear CMOS circuits characterized by weakly nonlinear behavior, ranging from amplifiers, and transconductors to filters, with any number of stages. It offers a compact, fast, and systematic way to model circuits as a structure of interconnected Gm-stages, and estimates the harmonic distortion at every circuit node, providing insight into the distortion contribution of every stage. The method uses a more involved model for each Gm-stage that also accounts for the dependence of its output current on cross-products of its input and output voltages, improving significantly the distortion estimation accuracy. The proposed method is easily implemented in MATLAB, and intends to be integrated as a tool in EDA suites to speed-up distortion estimation. A number of examples are presented, illustrating the application of the method and validating its accuracy via comparison with Cadence Spectre simulation.

Detailed state-space modeling and analysis of a class of RF switched-capacitor power amplifiers achieving high efficiency, output power, and linearity are presented. Time-domain voltage and current waveforms are analytically obtained via the steady-state solution of the amplifier's model equations. The output power of the fundamental and that of the harmonics, as well as the drain efficiency of the switched-capacitor power amplifier (SCPA) are derived. The state-space model is implemented in MATLAB and all theoretical results are compared to Cadence Spectre simulation of the SCPA and are found to be in good agreement.

This work presents adder and subtracter architectures for stochastic computing (SC). In contrast to standard approaches, the result of their operation is nonscaling, i.e., X ± Y, and this is achieved via a deterministic operation based on a counting process. These properties result in an improved tradeoff between accuracy and stochastic sequence length, fast convergence, and the potential for cascaded, scale-dependent (e.g., nonlinear) stochastic computations providing with flexibility on the design level. The architectures are modeled using Markov chains (MCs) allowing for detailed understanding of their proper operation supported with analytical derivations. Using modified MC models, the adder and subtracter's internal register size is analytically calculated providing guidelines for its optimal size selection based on accuracy requirements and stochastic input sequences lengths. Both architectures are simulated in MATLAB and are designed in Synopsys to compare their performance to that of existing ones in terms of computational accuracy and hardware resources. Finally, to demonstrate the adder's efficacy, we use it as a building block to realize a 3×3 convolution kernel and then perform a standard digital image processing task. The results are compared to those achieved using adder architectures from the SC literature.

Max & min architectures for stochastic computing (SC) are introduced. Their key characteristic is the utilization of an accumulator to store the signed difference between the two inputs, without randomizing sources. This property results in fast-converging and highly accurate computations using short sequence lengths, improving on the latency–accuracy tradeoff of existing SC max–min architectures. The operation of the proposed architectures is modeled using Markov Chains, resulting in in-depth analysis, the derivation of their statistical properties, and guidelines for selecting the register’s size to achieve overall design optimization. The computational accuracy and the hardware requirements of the proposed architectures are compared to those of existing ones in the SC literature, using MATLAB and Synopsys Tools. The efficacy of the proposed architectures is demonstrated by realizing a$3 \times 3$median filter and using it in an image processing application.

A time-dependent, flexible, 2-dimensional fine thoracic Finite-Element model for continuous lung Electrical Impedance Tomography (EIT) imaging is presented. It can be used as a tool to identify lung EIT hardware specifications, such as minimum frame rate, number of electrodes and noise requirements, as well as for prior evaluation of EIT reconstruction algorithms, before applying in-vivo data. The model is parameterized with respect to electrodes' characteristics, the measuring protocol, structural and temporal properties of the thoracic tissues. It is implemented in FEMM using a script generated by MATLAB code, while the measurements are acquired also by MATLAB. The electrodes' contact impedances, as well as the changes in electrical and geometric properties of the thoracic tissues due to breathing and perfusion, during each particular measuring frame, are taken into account.

This work presents a fast and flexible harmonic distortion estimation approach, applicable to linear CMOS circuits. It offers improved accuracy by using a Gm-stage model that includes the dependence of a stage's output current on cross-products of its input and output voltages. The application of the approach is demonstrated in a realistic circuit, and the accuracy of the obtained results is verified by comparison with Cadence Spectre simulation.

In this work, we explore the importance of sensors' calibration in inertial navigation applications. We focus on the case of low-cost systems, typically using MEMS inertial sensors, where the extra calibration cost is a critical parameter. We highlight the importance of calibration by deriving a bound of the evolution of the attitude and velocity error as a function of the calibration parameters' error. Then, we use low-cost 3-axis accelerometer and 3-axis gyroscope along with a popular pedestrian inertial navigation algorithm to experimentally confirm that raw sensor's data can be highly inappropriate for navigation purposes. Finally, we use the MAG.I.C.AL. methodology for joint calibration and axes alignment of inertial and magnetic sensors to achieve high accuracy measurements resulting in a reliable inertial navigation system.

Stochastic computing has been successfully applied in a plethora of applications, including machine learning, computer vision and soft coding/decoding, due to its low complexity, chip area, and power consumption advantages, as well as its tolerance to soft errors. Among the four fundamental numerical operations, addition, subtraction and multiplication are simple to realize stochastically. Division however is significantly more challenging and complex. This work introduces a new architecture for stochastic division in unipolar format using a deterministic finite state machine. In contrast to the existing architectures, the proposed divider does not require any internal stochastic number generator, which makes it more versatile, compact and easy to implement. The divider's accuracy is defined based on mean absolute error metrics and it is estimated using MATLAB simulation. Applications of the proposed divider in image processing are presented demonstrating its accuracy and efficiency in realistic systems.

Internet of Things growth requires the development of low power and low cost wireless transceivers. Here, we present three recently developed all-digital frequency synthesizer architectures which can be used as transmitters for Internet of Things applications. These all-digital transmitters are based on different sigma-delta modulator architectures, varying in performance and hardware complexity. The operation principles of the three proposed architectures are described. Then, proof-of-concept FPGA implementations of these architectures are presented and compared in terms of hardware resources and speed. Their performance is tested using 32-QAM modulated signals. Finally, conclusions are drawn to help the reader select the most suitable architecture for a given application.

A hardware architecture for the implementation of Multi-Step Look-Ahead Sigma-Delta Modulators (MSLA SDMs) is presented. MSLA SDMs offer superior performance than conventional single-bit SDMs for a multitude of applications relying on single-bit signal representation. However, traditional look-ahead SDMs have very high algorithmic complexity and their hardware implementation does not allow for real-time operation. MSLA SDMs overcome this problem by transforming the minimization problem associated with traditional look-ahead SDMs. A proof-of-concept FPGA implementation of a specific MSLA SDM is discussed and compared to a conventional single-bit SDM in terms of performance and hardware complexity. It is demonstrated that MSLA SDMs are a viable alternative to conventional single-bit SDMs when better performance with moderate additional hardware complexity are required.

All-digital frequency synthesis architectures with direct modulation capability, based on single-bit sigma-delta modulation loop with an innovative homodyne band-pass filter topology are presented focusing on wireless Internet of Things (IoT) applications. A hardware-efficient multiplier-free variation of the homodyne filter is also proposed. MATLAB simulation results for 16-QAM modulation demonstrate the capabilities of the proposed architectures.

Fully-digital single-bit-output (DAC-less) frequency synthesizers with imbedded modulation capability are considered as the foundation for building fully-digital RF transmitters. The paper presents an overview of recent results and introduces a new architecture based on sigma-delta like feedback noise shaping.

All-digital frequency synthesizers are favored by modern nano-scale CMOS technologies but suffer from strong frequency spurs and timing irregularities. This paper reviews the time-domain-correction and spurs-suppression techniques for all-digital frequency synthesizers, identifies their strengths and weaknesses and provides new research directions.

Modern nano-scale CMOS technologies favor all-digital architectures for frequency synthesizers in wireless and other mixed-signal applications. This paper is a short introduction to the topic presenting contemporary approaches from a signal and systems perspective as well as directions for future research.

This work introduces an optimization method to minimize the noise and the power consumption of active filters driven by bang-bang signals taking into account the hard voltage-range constraints of the amplifiers and guaranteeing their full-range operation without saturation.

We propose a nearly all-digital, broadband frequency mixer which synthesizes a sinewave at the frequency difference of two periodic input square waves. The mixer has high output spurious free dynamic range by cancelling the dominant intermodulation products in the sinewave generation process. Due to its use of almost exclusively digital circuitry, it can easily be integrated with CMOS digital circuits. A programmable logic implementation and spectral measurements demonstrate its feasibility and performance.

This work concerns with the behavior and characterization of continuous-time signal processing structures involving time-variant delays. Both loop-less and looped structures are considered. Their cascades, invertibility and uniqueness of representation are studied along with their similarity transformations leading to the concept of externally time-invariant internally time-variant delay structures.

This paper considers an additive noise channel where the time-A; noise variance is a weighted sum of the squared magnitudes of the previous channel inputs plus a constant. This channel model accounts for the dependence of the intrinsic thermal noise on the data due to the heat dissipation associated with the transmission of data in electronic circuits: the data determine the transmitted signal, which in turn heats up the circuit and thus influences the power of the thermal noise. The capacity of this channel (both with and without feedback) is studied at low transmit powers and at high transmit powers. At low transmit powers, the slope of the capacity-versus-power curve at zero is computed and it is shown that the heating-up effect is beneficial. At high transmit powers, conditions are determined under which the capacity is bounded, i.e., under which the capacity does not grow to infinity as the allowed average power tends to infinity.

We demonstrate dynamic power maximization and synchronization of a wireless RF communication link through adaptation of the radiation pattern of a phased array at the transmitter. Adaptation is performed through a multi-dithering, coherent detection gradient descent analog controller chip, and compensates for phase variations in the communication link. The chip, located at the transmitter, controls the phase of each element in the array so that all transmitted signals combine coherently in phase at the receiver. The control objective is the downconverted RF signal at the receiver, which is fed back to the input of the chip through a reverse, lower bandwidth analog RF link. Measurements on the demonstrated prototype, consisting of a 4-element phased array at the transmitter and an omnidirectional receiver, indicate microsecond scale continuous-time optimization of the system.

Recently, a delay-insensitive architecture for gradient descent adaptive control, based on parallel synchronous detection for model-free gradient estimation was presented. The key to delay insensitivity in the gradient estimation is careful selection of the phase of the local oscillator in the mixer of synchronous detection, amounting to a single parameter to be estimated per control channel. In this contribution we present a practical adaptive phase selection algorithm for delay compensation in the adaptive control architecture, and present experimental results from a SiGe BiCMOS implementation of the architecture demonstrating sub-microsecond response time in closed-loop adaptive control.

A fully differential translinear 3-phase sinusoidal oscillator architecture is presented. The architecture is meant for BiCMOS implementation and uses only NPN devices, typically of higher performance than their PNP counterparts in most technologies. The architecture features both frequency and amplitude control and expressions are derived showing the dependence of these controls to external current biases. Measurements on a 0.5 mum SiGe BiCMOS implementation of the architecture demonstrate frequency control from below 80 Hz to above 800 MHz, general agreement between theory and actual data for the amplitude of oscillation, as well as low distortion. Power consumption scales with the frequency of operation and amounts to ~2 muW/MHz.

Temperature sensing using microwave radiometry has proven value for non-invasively measuring the absolute temperature of tissues inside the human body. However, current clinical radiometers operate in GHz or infrared frequency ranges; this limits their depth of penetration since the human body is not "transparent" at these frequencies. To address this problem, we have designed and built an advanced, near-field radiometer operating at VHF frequencies (64MHz) with a ~100 KHz bandwidth. In the core of the radiometer lie an embedded impedance analyzer and an automatic antenna matching network; they compensate in-real time for any load variation that may occur due to near-field antenna coupling and movements of the human body. The radiometer has performed accurate temperature measurements to within plusmn0.1degC, over a tested physiological range of 28-40degC in saline phantoms whose electric properties match those of human tissue. The current method has the potential of being integrated on magnetic resonance imaging (MRI) modalities.

A mixed-signal architecture for continuous-time multidimensional model-free optimization is presented. It is based on multi-channel coherent modulation and detection that reliably estimates the objective function's gradient, with respect to the system parameters, in the presence of time delays. The narrowband nature of the excitation signals reduces the unknown dynamics of the objective function to a single parameter per control channel, the phase delay. An efficient implementation of the adaptive control architecture is presented; it incorporates parallel control channels with individually selectable 6-level phase delay adjustment. Initial experimental results indicate wide operating range covering almost 7 decades of excitation frequencies.

Power-optimal traffic routing in bus-networks is studied from an information theoretic perspective. Power consumption in bus-networks is mathematically related to traffic patterns leading to theoretically optimal routing strategies and ultimate performance limits. Networks-on-chip depending strongly on efficient communication schemes motivate this work.

Diophantine Frequency Synthesis1 is a new approach to fine-step and fast-hopping frequency synthesis that is based on mathematical properties of integer numbers and Diophantine equations. Diophantine Frequency Synthesis overcomes the constraining relationship between frequency step and phase-comparator frequency inherent in conventional phase-locked loops. It leads to fine-step, fast-hopping, modular-structured frequency synthesizers with potentially very low spurs, especially near the carrier.

Motivated by on-chip communication, a channel model is proposed where the variance of the additive noise depends on the weighted sum of the past channel input powers. For this channel, an expression for the capacity per unit cost is derived, and it is shown that the expression holds also in the presence of feedback.

State-space modeling of fully differential Gm-C filters with weak nonlinearities is used to develop a fast algorithm for intermodulation distortion estimation. It results in simple analytic formulas that apply directly to Gm-C filters of any order and any fully balanced topology. The algorithm has been verified using SpectreS (SPICE) and Simulink simulation. Theory and simulation results are found in good agreement.

A Gm-C architecture for a quadrature, sinusoidal oscillator with instantaneous, phase-preserving, linear frequency control and independent, static amplitude control is presented. The architecture is analyzed and closed-form expressions are given for both frequency and amplitude. An implementation of the architecture using general purpose discrete bipolar transistors has been tested. Simulation results and measurements are demonstrated and compared to theory. The wide frequency range of tunability and the low total harmonic distortion observed, as well as the inherent phase preservation make the architecture appropriate for use in analog communication schemes

A robust system architecture to achieve optical coherency in multiple-beam free-space laser communication links with adaptive optics is introduced. It is based on deterministic multi-dithering and gradient descent flows and accounts for phase delays in the dither signal, during propagation in the atmosphere, as well as saturation of the optical phase shifters. The architecture has been mathematically analyzed and simulation results of a VLSI implementation of the architecture are presented and found in agreement with the theoretical model

In this paper, we present a fast algorithm to derive the harmonic distortion in fully balanced Gm-C filters. It is based on state-space modeling and decomposition of the filter into a cascade of an input stage, a core stage and an output stage. This approach results in compact expressions for the distortion that involve explicitly the structural matrices of the filter and the values of the circuit elements. The algorithm was verified using a third-order low pass Butterworth filter designed in a 0.5mum CMOS process. The theoretical results are found to be in good agreement with CADENCE and MATLAB simulations

Crossbar switching networks formed by nanowires are promising future data storage devices. This work addresses the fundamental question: What is the information storage capacity of a crossbar switching network? The two major classes of nanowire crossbar switching networks are considered, those with ohmic and those with semiconductive switches. The focus is on the first class which is in the center of current nanotechnology research. Exact, simple approximate, and asymptotic expressions of the information storage capacity are provided as functions of the network size. The derivations indicate technological and geometrical considerations in the design of efficient nanowire devices.

In this work we ask the fundamental question: How many bits of information can be stored in a crossbar switching network? The answer is trivial when the switches of the network are in series with diodes (semi-conductive) but it is complicated when the switches are regular contacts. Exact explicit expressions and sim-ple asymptotic bounds of the storage capacity (in bits) are derived for the general crossbar switching network with regular contact switches.

We consider the problem of reduction of computation cost by introducing redundancy in the number of ports as well as in the input and output sequences of computation modules. Using our formulation, the classical "communication scenario" is the case when a computation module has to recompute the input sequence at a different location or time with high fidelity and low bit-error rates. We then consider communication with different computational cost objective than that given by bit-error rate. An example is communication over deep submicrometer very-large scale integration (VLSI) buses where the expected energy consumption per communicated information bit is the cost of computation. We treat this scenario using tools from information theory and establish fundamental bounds on the achievable expected energy consumption per bit in deep submicrometer VLSI buses as a function of their utilization. Some of our results also shed light on coding schemes that achieve these bounds. We then prove that the best tradeoff between the expected energy consumption per bit and bus utilization can be achieved using codes constructed from typical sequences of Markov stationary ergodic processes. We use this observation to give a closed-form expression for the best tradeoff between the expected energy consumption per bit and the utilization of the bus. This expression, in principle, can be computed using standard numerical methods. The methodology developed here naturally extends to more general computation scenarios.

We present a comprehensive mathematical analysis of the energy dissipation in deep submicron technology buses. The energy estimation is based on an elaborate bus model that includes distributed and lumped parasitic elements that appear as technology scales. The energy drawn from the power supply during the transition of the bus is evaluated in a closed form. The notion of the transition activity of an individual line is generalized to that of the transition activity matrix of the bus. The transition activity matrix is used for statistical estimation of the power dissipation in deep submicron technology buses.

In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.

Article Share on Analysis and implementation of charge recycling for deep sub-micron buses Authors: Paul Sotiriadis Department of EECS, Massachusetts Inst. of Technology Department of EECS, Massachusetts Inst. of TechnologyView Profile , Theodoros Konstantakopoulos Department of EECS, Massachusetts Inst. of Technology Department of EECS, Massachusetts Inst. of TechnologyView Profile , Anantha Chandrakasan Department of EECS, Massachusetts Inst. of Technology Department of EECS, Massachusetts Inst. of TechnologyView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 364–369https://doi.org/10.1145/383082.383184Online:06 August 2001Publication History 7citation204DownloadsMetricsTotal Citations7Total Downloads204Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The energy dissipation associated with driving long wires accounts for a significant fraction of the overall system energy. This is particularly the case with the increasing importance of the inter-wire parasitic capacitance in deep sub-micron technology. A closed form solution for estimating the energy dissipation of a data bus is presented that uses an elaborate parasitic wire model. This includes the distributed RLC effects of wires as well as the coupling between wires. We also propose a general class of coding techniques to reduce energy dissipation for data transmission by trading-off between computation and communication costs. An algorithm is presented to design efficient coding strategies to minimize energy. When the effects of interwire capacitance are taken into account, the best coding strategy is not to simply minimize transitions - an approach followed by previous research. Instead, Transition Pattern Coding (TPC) modifies the transition profile to minimize energy, and in many cases higher transition activity can result in lower energy. Results show that up to a factor of 2 reduction in energy.