This paper presents a DSP-based SerDes reα that utilizes a hybrid speculative/successive-approxims register (SAR) analog-to-digital converter (ADC) to digitize data at the receiver's analog front-end. The proposed digitize technique addresses the high-power drawback of conventi flash-based ADCs used in sampling-based wireline recei' while allowing for digital equalization and data recover; 10 Gb/s through five time-interleaved channels. The receiver is designed and laid out in a 65 nm CMOS process. The occupies 1.53 mm2, and based on simulation results, it consu 263 mW from a 1 V core supply.

Synchronous clock distribution continues to be the dominant timing methodology for VLSI circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter budgets. Process, voltage, and temperature variations, especially those that are intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. As a result, active clock deskewing systems are becoming necessary to tune out unwanted clock skew after chip fabrication. This paper first defines the operation of a specially designed phase detector, referred to as an up/down detector (UDD). Next, four of these UDDs are used as links to construct a stable, autonomously locking quadrantal ring tuning (QRT) configuration that effectively joins together four distributed delay-locked loops (DLLs) without the need for any system-level controller. This cyclic, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simplistic two-level QRT system is presented for a generic H-tree clock distribution network, demonstrating stable locking behavior and more than 50% average reduction in overall clock skew.

In this paper, we propose a novel approach to voltage-island formation, for the energy optimization of many-core architectures, which mitigates the impact of process, voltage, and temperature (PVT) variations. The islands are created by balancing their shape constraints imposed by intra and inter-island communication with the desire to limit the spatial extent of each island to minimize PVT impact. In addition, to reduce the number of voltage levels in the design, we propose an efficient voltage selection approach that provides near optimal results, for a set of 33 examined cases, with more than a ten times speedup compared to the best-known previous methods. This run-time improvement is important, especially for large many-core platforms. Finally, we present an evaluation platform considering pre-fabrication and post-fabrication PVT scenarios where multiple applications with hundreds to thousands of tasks are mapped onto many-core platforms with hundreds to thousands of cores to evaluate the proposed techniques. Results show that the average energy savings for 33 test cases using the proposed methods are 37% compared to 16% obtained using previous methods.

Among the different methods of reducing power for core-based system-on-chip (SoC) designs, thevoltage-islandtechniquehas gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are two important steps in the design process. We propose a new application-driven approach to voltage partitioning and island creation with the objective of reducing overall SoC power, area, and floorplanner runtime. Given an application power-state machine (PSM), we first identify the suitable range of supply voltages for each core. Then, we generate the discrete voltage assignment table using a heuristic technique. Next, we describe a methodology of reducing the large number of available choices from the voltage assignment table down to a useful set using the application PSM. We partition the cores into islands, using a cost function that gradually shifts from a power-based assignment to a connectivity-based one. Compared with previously reported techniques, a 9.4% reduction in power and 8.7% reduction in area are achieved using our approach, with an average runtime improvement of 2.4 times.

Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the voltage island technique has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are the two important steps in the design process. We propose a new application-driven, floorplan-aware approach to voltage partitioning and island creation with the objective of reducing overall SoC power, area and runtime. Previous approaches used the voltage assignment table as the starting point for voltage island creation. In this paper, we present a technique to generate a voltage assignment table using dynamic programming. Next, we partition the cores into islands, based on the Power State Model (PSM) of the application, and connectivity information used in floorplanning. Finally, solutions are sent to the floorplanner in sequence until a valid solution is reached. Compared to previously reported techniques, a 10% reduction in power and 8% reduction in area are achieved using our approach, with an average runtime improvement of 2.3X.

We propose a macromodel for delay estimation at the RTL level. The macromodel is useful for approximating the delay through the critical path of an RTL block as a function of Vddand Vt. It is specifically designed for delay estimation at the early phase of the design flow and based on detailed HSPICE analysis of NAND chains to extract the parameter values. This macromodel has two fitting parameters which make the macromodel simple but accurate. The steps needed to extract the two parameters are described. The validation of the model is demonstrated by comparison with HSPICE. According to our experiments, this macromodel is able to predict the delay variation due to Vddand Vtwith accuracy of ±3% at the logic level and ±5% for RTL blocks.

The configuration of an application-specific instruction-set processor through an exhaustive search of the design space is computationally prohibitive. Consequently, we propose a novel algorithm that models the design space using local regression statistics. With only a small subset of the design space sampled, our model uses statistical inference to estimate all remaining points. This technique enables existing design space exploration approaches to make longer strides toward the optimal point while evaluating fewer points in the design space. We tested our approach on two important aspects of processor architecture. Initially, we optimized the pattern history table (PHT) of a GSelect branch predictor to minimize the total energy of an embedded processor. Our approach was able to find the optimal configuration for the majority of benchmarks tested. By configuring the PHT size using our approach, the total processor energy was reduced by 17.2% on average, which is close to the possible percentage of 17.6% using optimal configurations. We then extended our approach to a multidimensional cache tuning problem where we configured a two-level cache hierarchy with 19 278 possible configurations. In this case, only 1% of the design space was simulated, resulting in a 100 times speedup. In doing so, we were able to identify near optimal configurations for most benchmarks and reduce the overall energy of the processor by 13.9% on average, with one benchmark by as much as 53%.

On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise. This paper provides guidelines for standard cell layouts of decaps for use within Intellectual Property (IP) blocks in application-specific integrated circuit (ASIC) designs. At 90-nm CMOS technology and below, a tradeoff exists between high-frequency effects and electrostatic discharge (ESD) reliability when designing the layout of such decaps. In this paper, the high-frequency effects are modeled using simple equations. A metric is developed to determine the optimal number of fingers based on the frequency response. Then, a cross-coupled design is described that has been recently introduced by cell library developers to handle ESD problems. Unfortunately, it suffers from poor response times due the large resistance inherent in its design. Improved cross-coupled designs are presented that properly balance issues of frequency response with ESD performance, while greatly reducing thin-oxide gate leakage.

Configuration of an application-specific instruction-set processor (ASIP) through an exhaustive search of the design space is computationally prohibitive. We propose a novel algorithm that models the design space using local regressions. With only a small subset of the design space sampled, our model uses statistical inference to estimate all remaining points. We used our approach to tune a two-level cache with 19,278 legal configurations. Only 1% of the design space was simulated resulting in a 100x speedup over a brute-force approach. In doing so, we were able to identify near optimal configurations for most benchmarks and reduce the overall power of the processor by 13.9% on average, with one benchmark as high as 53%.

Fault-tolerant design of network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction - these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, constrained with tight system performance specifications and other requirements In this paper, we provide a top-down view of fault-tolerance methods for NoC infrastructures, and present a range of metrics used for estimating their quality. We illustrate the use of these metrics by simulating a few simple but realistic fault-tolerant scenarios.

On-chip serial links to replace standard buses for global communication have been the subject of a number of recent investigations. The main reason for considering serial links is to reduce routing congestion and design complexity. However, the serialization of parallel data may actually increase the power dissipation due to increased switching activity. This paper describes a new bit ordering technique to reduce switching activity on serial links, assuming that the statistical data of the parallel bus traces are known in advance. The method reduces the switching activity by an average of 40% 50% compared to random bit ordering.

On-chip decoupling capacitors (decaps) are generally used to reduce power supply noise. Passive decap designs are reaching their limits in 90nm CMOS technology due to higher operating frequency, lower supply voltage, increased concerns on electrostatic discharge (ESD) reliability and thin-oxide gate leakage. In this paper, a novel active decap design is proposed to provide better noise reduction than the passive decaps. The active decap is analyzed for ESD reliability and process/temperature variation adaptability. It is implemented in a 1.0V-core 90nm process with a total area of 0.168mm2and standby power of 3.0mW.

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation.

Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90-nm technology with higher leakage currents, it is appropriate to revisit existing design metrics. In this paper, a reevaluation of the metrics is carried out, and a generalized set of metrics is proposed. Supply voltage (VDD) and threshold voltage (VT) scaling are two popular approaches to power reduction. As such, the effects on power and frequency are analyzed, and the feasible region of operation is identified in the VDDversus VTplane. A fundamental relationship is established between the optimal operating points and the generalized design metrics. The initial findings also indicate that some designs may have a higher percentage of leakage than expected to achieve overall power reduction, running somewhat counter to conventional wisdom

A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant performance parameters - power, latency, and throughput. Experiments show that our approach is effective and requires minimal modifications of the existing design methods for NoC interconnects.

Deep submicron technology is forcing designers away from traditional ASIC design styles toward structured arrays for the implementation of logic circuits. Structured arrays have many inherent benefits in terms of CAD tool design, testability and reliable fabrication. FPGAs and structured ASIC fabrics are two examples, but their speed, area and power overheads are high due to their programmability features. If programmability is removed, it is possible to reduce the overhead. Perhaps it is time to revisit the use of structured logic for fixed-function blocks, such as ROMs and PLAs, to determine if they are better-suited for this purpose. In particular, this paper investigates the PLA from the self-test and self-repair perspectives. ASIC blocks are known to have limitations in terms of self-test, but have little or no hope of providing self-repair. In contrast, this paper proposes straight-forward solutions for self-test and self-repair of PLAs. We find that it can provide 100% self-test coverage, and a very high probability of self-repair at the cost of area overhead

Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic arrays must be able to compete with standard ASIC designs. This paper proposes a CMOS PLA based on a dynamic NOR architecture that uses an input-isolation technique along with a latch-based sense amplifier to achieve both high operating speed and low-energy consumption. The proposed architecture is designed and simulated in a 0.18mum CMOS technology. It improves the delay by 10% compared with the fastest reported PLA. It also achieves the lowest power-delay product of all other reported dynamic PLAs

In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

Multi-Processor (MP-SoC) platforms are emerging as the latest trend in SoC design. Monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these high performance SoCs. Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature. By adopting a more structured network-based design paradigm, specific clock cycle requirements can easily be met. The precise focus of this paper is to show how the butterfly fat tree (BFT) can meet this objective when used as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.

The complexity of today's chips is such that relying solely upon external ATE resources is insufficient for scan test. In this work, we develop the concept of dedicated autonomous scan-based testing (DAST) by proposing a scheme that introduces hierarchy and separates the functionality of ATE resources into two distinctive classes: a) test data communication, and b) test data control and observation. To simplify the ATE for embedded digital core testing, we propose transferring ATE test data control/observation functions to one or more Embedded Autonomous Sequencers (EAS) dedicated to single or multiple embedded cores of an SoC We present implementation results of our DAST methodology when applied to a number of SoC benchmarks.

Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

This tutorial describes the problems encountered in typical ultra-deep submicron (UDSM) designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems before tape-out. We first illustrate that UDSM verification must go well beyond simple geometric and circuit comparison checks to address increasingly important issues such as timing, power integrity, signal integrity, and reliability. The key issues of IR drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described. We present real-world examples of such problems and how to find these problems using full-chip verification.

Frequency domain analysis of switched-capacitor and other clocked circuits including nonlinearities is a difficult problem requiring special attention. Conventional nonlinear frequency response methods are computationally intensive and time consuming for circuits with large transient components. In this paper, we present a novel technique for the rapid estimation of the nonlinear frequency response of switched-capacitor circuits. The analysis technique is formulated using a multifrequency sinusoidal excitation to drive the circuit into its steady-state condition. Then, the fundamental components are extracted using a frequency-directed Discrete Fourier Transform (DFT) in order to construct the frequency response. The key steps of this approach include the selection of noninterfering input frequencies and the determination of properly scaled input amplitudes. In addition, a method is proposed to reach steady-state quickly and to detect the steady-state condition for use in conjunction with the multifrequency approach described here.

Integrated circuit design has evolved to the stage where large, complex, analog and digital functionalities are implemented on a single chip or as an integrated chip set. Besides the mixed signal nature of the designs, the analog sections also include continuous-time and discrete-time components. Thus, for analysis of these integrated modules, all encompassing simulation capabilities are required that address, not only transient analysis of mixed analog-digital circuits, but frequency domain analysis as well. In this paper, we present mechanisms for multilevel and mixed-domain simulation of analog systems tied in with mixed analog-digital simulation. We then describe the implementation in the form of an open-ended and expandable simulation framework, iMACSIM. A simulation backplane is used to provide a general event-processing and scheduling framework that ties together the various algorithms necessary for simulation of various classes of circuits in different analysis regimes.

Waveform relaxation (WR) has been shown to be an effective algorithm to simulate large digital circuits. In this paper, we explore parallel WR methods to further improve the performance. The parallel processing issues under investigation include partitioning, task granularity, scheduling and allocation. The difficulty of addressing these issues is that circuit simulation problems tend to have highly irregular computational structures. The use of high-level waveforms generated from logic or timing simulators is introduced as a way of improving speed. The speed improvements for circuit partitioning, window selection and task allocation using high-level information are presented.

Describes methods of increasing parallelism, thereby improving the performance, of waveform relaxation-based parallel circuit simulators. The key contribution is the use of parallel nonlinear relaxation and parallel model evaluation to solve large subcircuits that may lead to load balancing problems. These large subcircuits are further partitioned and solved on clusters of tightly-coupled multiprocessors. This paper describes a general hybrid/hierarchical approach for waveform relaxation, and then focuses on the implementation issues regarding parallel nonlinear relaxation and parallel model evaluation. A number of benchmark circuits are used to demonstrate the improved performance of this approach and its range of applicability in parallel circuit simulation.>

The parallelization of the waveform-relaxation-Newton (WRN) method for circuit simulation is described. The techniques are applied at three levels of granularity: subcircuits are processed in parallel for large-grain parallelism, time points are processed in parallel for medium-grain parallelism, and devices are processed in parallel for fine-grain parallelism. The effectiveness of each of these approaches is demonstrated with the PSPLAX program (which is a parallel version of a WRN program called SPLAX) using a number of industrial examples. Currently, PSPLAX is implemented on an Alliant FX/80 with eight processors. The results indicate that the combination of these approaches should be effective on larger systems.>

This paper describes new algorithms for finding the K-most critical paths, checking static sensitizability of these paths, and performing incremental timing verification on combinational circuits. The static sensitization method uses binary decision diagrams to avoid costly backtracking operation used in other path analysis programs. The speed and efficiency of the techniques are demonstrated individually using the ISCAS benchmark circuits, and then together in a timing optimization loop.

The authors describe a new program called iMACSIM which allows multi-level, mixed-domain simulation of analog integrated circuits. The program performs the simulation of different subcircuits at the behavioral, functional, and electrical levels concurrently. It also enables some parts of the circuit to be simulated using discrete-time algorithms while other portions are processed by continuous-time techniques. Simulations are presented to demonstrate the functionality of the program.>

An efficient algorithm for the indentification of viable paths in a combinational logic circuit using binary decision diagrams is described. The viable paths are justified by generating and resolving logic and delay constraints along the critical path based on the stable times and stable values of the side inputs. Results of the analysis, using the ISCAS combinational benchmark circuits, indicate that most of the circuits can be analyzed in a few CPU-seconds.>

The implementation of asynchronous waveform relaxation on parallel processors is discussed. Three different approaches, all based on event-driven scheduling techniques, are compared to the standard data-flow scheme. Issues involving the use of priority queues and preemptive scheduling are described. Circuit examples are used to demonstrate that good speedup can be achieved by using the event-driven method. The results indicate that the combination of data-flow and event-driven scheduling, together with a suitable preemptive scheme, provides a speed improvement of 1.5 to 2.5 over standard data-flow scheduling on eight processors.>

A systematic methodology for automatic consistency checking and optimization of parameterized macromodels is described. An overview of the entire macromodel verification system. iMAVERICK, is provided. An efficient stochastic algorithm to optimize the parameters of a given macromodel is described, and a number of characteristics of the algorithm are examined. A heuristic measure of the likelihood that a cost evaluation will provide useful information or a better solution that is used in the algorithm is based on the information accumulated from the previous cost evaluations. This heuristic measure is used to reject poor sample points without sacrificing the quality of solutions. A waveform comparison technique for evaluating the performance of the proposed configuration in the optimization process is described. It is sensitive to phase errors between waveforms and has the capability of filtering out glitches and high-frequency noise. Several examples of macromodel optimization using the iMAVERICK system are presented.>

This paper describes a class of parallel algorithms for circuit simulation based on hierarchical relaxation that has been implemented on the Cedar multiprocessor. The Cedar machine is a reconfigurable, general-purpose supercomputer that was designed and implemented at the University of Illinois. A hierarchical circuit simulation scheme was developed to exploit the hierarchical organization of Cedar. The new algorithm and a number of key issues, such as multilevel circuit partitioning, data partitioning, cluster algorithm selection, and cluster algorithm implementation are described in this paper. Performance results on a variety of different configurations of Cedar are also presented that illustrate the benefits of the hierarchical approach over the non-hierarchical approach.

A description is presented of efforts applying mixed-mode simulation techniques to two other areas of research. In incremental simulation, techniques are presented to perform fast incremental circuit simulation based on a modified incremental-in-space approach and event-driven techniques. In fault simulation, a mixed-mode fault simulator is presented that allows the user to specify any type of electrical level fault at the transistor level, as opposed to one of the simple stuck-at faults used in logic simulators. The program performs fault simulation, using mixed-mode techniques, and provides the fault coverage of a set of input patterns. To improve efficiency, concurrent fault simulation with a table look-up scheme is used. The merits of both algorithms are demonstrated with simulation results that show significant speed-ups over standard approaches.>

A new relaxation algorithm for circuit simulation that combines the advantages of iterated timing analysis (ITA) and waveform relaxation (WR) is described. The method is based on using an iterative stepsize refinement strategy with a waveform-relaxation-newton (WRN) algorithm. All three relaxation techniques, ITA, WR, and WRN, are compared, and experimental results that indicate the strengths and weaknesses of the methods are presented. In addition, a new convergence proof for the waveform-Newton (WN) method for systems with nonlinear capacitors is provided. Finally, it is shown that the step-refined WRN algorithm can be implemented on a parallel processor in such a way that different subsystems can be processed in parallel and the solution at different timepoints of the same subsystem can also be computed in parallel.>

The speedups derived from the exploitation of the waveform properties are discussed and simple procedures are provided to compute empirical upper bounds on the speed improvement when these properties are exploited. These upper bounds are used to explain the reasons for the variations in the speedups and to evaluate the performance of two circuit simulation algorithms based on nonlinear relaxation that are implemented in the SPLICE3 program. The first algorithm is an advanced version of the iterated timing analysis (ITA) algorithm that exploits the latency property. The second algorithm is a new event-driven multirate integration scheme, based on ITA, that exploits multirate behavior of circuits. It also uses a novel event-driven approach to handle step rejections called selective-backup.>

Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.>