Inspired by the design patterns of object-oriented software architecture, we offer an initial set of “privacy patterns”. Our intent is to describe the most important ways in which software systems can offer privacy to their stakeholders. We express our privacy patterns as class diagrams in the UML (Universal Modelling Language), because this is a commonly-used language for expressing the high-level architecture of an object-oriented system. In this initial set of privacy patterns, we sketch how each of Westin's four states of privacy can be implemented in a software system. In addition to Westin's states of Solitude, Intimacy, Anonymity, and Reserve, we develop a privacy pattern for an institutionalised form of Intimacy which we call Confidence.

SUMMARY Cloud computing has recently attracted great attention, both commercially and academically. MapReduce is a popular programming model for distributed storage and computation in the cloud. In this paper, we survey cloud‐based multimedia applications, identifying the open issues and challenges which arise when MapReduce is used for cloud computing. Copyright © 2011 John Wiley & Sons, Ltd.

SUMMARY With the rapid development of cloud computing, software applications are shifting onto cloud storage rather than remaining within local networks. Software distributions within the cloud are subject to security breaches, privacy abuses, and access control violations. In this paper, we identify an insider threat to access control which is not completely eliminated by the usual techniques of encryption, cryptographic hashes, and access‐control labels. We address this threat using software watermarking. We evaluate our access‐control scheme within the context of a Collaboration‐oriented Architecture, as defined by The Jericho Forum. Copyright © 2011 John Wiley & Sons, Ltd.

We proposed a definition of transparency in software development to improve communication among stakeholders. The notion of transparency is important, because it enables stakeholders to identify and understand the information exchanged during communication. We designed a survey to gather evidence to support or refute our beliefs about transparency in software development. We discovered a superiority bias in our respondents when answering questions regarding communication problems. In this paper, we present our survey design and preliminary results of our survey.

Software protection and security has been a more and more important issue. In order to prevent software from unauthorized use and modification, a great many techniques have been proposed and developed. In this paper, we address this issue through a prevention technique called software watermarking, and we propose a novel software watermarking scheme, which can embed multiple non-interfering watermarks into the same program. Unlike published schemes, this scheme encodes the watermark into mapping functions and then embeds the mapping codes, which are generated from these functions, into the program at the articulation points of its control flow graph. The extraction in this scheme, which is based on dynamically loading a reconstructed program to recover the watermark, is also a novel approach to the software watermarking field. Experimental results indicate that the size and performance overheads caused by this scheme can keep steady.

An obfuscation aims to transform a program, without affecting its functionality, so that some secret data within the program can be hidden for as long as possible from an adversary armed with reverse engineering tools. Slicing is a reverse engineering technique which produces a subset of a program that is dependent on a particular program point and is used to aid in program comprehension. Thus slicing could be used as a way of attacking obfuscated programs. In this contribution, we highlight a few obfuscating transforms that were proposed in an earlier publication for making attacks difficult to mount using slicers and then illustrate an experimental design to evaluate the strength of these transforms with respect to well defined slicing metrics.

The goal of obfuscation is to transform a program, without affecting its functionality, such that some secret information within the program can be hidden for as long as possible from an adversary armed with reverse engineering tools. Slicing is a form of reverse engineering which aims to abstract away a subset of program code based on a particular program point and is considered to be a potent program comprehension technique. Thus, slicing could be used as a way of attacking obfuscated programs. It is challenging to manufacture obfuscating transforms that are provably resilient to slicing attacks.We show in this paper how we can utilise the information gained from slicing a program to aid us in designing obfuscations that are more resistant to slicing. We extend a previously proposed technique and provide proofs of correctness for our transforms. Finally, we illustrate our approach with a number of obfuscating transforms and provide empirical results using software engineering metrics.

Fingerprinting embeds a secret message into a cover message. In media fingerprinting, the secret is usually a copyright notice and the cover a digital image. Fingerprinting an object discourages intellectual property theft, or when such theft has occurred, allows us to prove ownership. The Software Fingerprinting problem can be described as follows. Embed a structure W into a program P such that: W can be reliably located and extracted from P even after P has been subjected to code transformations such as translation, optimization and obfuscation; W is stealthy; W has a high data rate; embedding W into P does not adversely affect the performance of P ; and W has a mathematical property that allows us to argue that its presence in P is the result of deliberate actions. In this article, we describe a software fingerprinting technique in which a dynamic graph fingerprint is stored in the execution state of a program. Because of the hardness of pointer alias analysis such fingerprints are difficult to attack automatically.

We discuss two secure operating system frameworks built upon the Trusted Computing Group's Trusted Platform Module intended to assure remote execution. The security implications of the respective design decisions are discussed, as well as highlighting vulnerabilities in protocol and system design. A novel theoretical attack on the TPM is proposed, which makes use of the lack of curtained memory in the TPM specification

Many program analysis techniques used by compilers are applicable only to programs whose control flow graphs are reducible. Node-splitting is a technique that can be used to convert any control flow graph to a reducible one. However, as has been observed for various node-splitting algorithms, there can be an exponential blowup in the size of the graph.We prove that exponential blowup is unavoidable. In particular, we show that any reducible graph that is equivalent to the complete graph on n nodes (or to related bounded-degree control flow graphs) must have at least 2n-1 nodes. While this result is not a surprise, it may be relevant to the quest for finding methods of obfuscation for software protection.

We identify three types of attack on the intellectual property contained in software and three corresponding technical defenses. A defense against reverse engineering is obfuscation, a process that renders software unintelligible but still functional. A defense against software piracy is watermarking, a process that makes it possible to determine the origin of software. A defense against tampering is tamper-proofing, so that unauthorized modifications to software (for example, to remove a watermark) will result in nonfunctional code. We briefly survey the available technology for each type of defense.

Watermarking embeds a secret message into a cover message. In media watermarking the secret is usually a copyright notice and the cover a digital image. Watermarking an object discourages intellectual property theft, or when such theft has occurred, allows us to prove ownership.The Software Watermarking problem can be described as follows. Embed a structure W into a program P such that: W can be reliably located and extracted from P even after P has been subjected to code transformations such as translation, optimization and obfuscation; W is stealthy; W has a high data rate; embedding W into P does not adversely affect the performance of P; and W has a mathematical property that allows us to argue that its presence in P is the result of deliberate actions.In the first part of the paper we construct an informal taxonomy of software watermarking techniques. In the second part we formalize these results. Finally, we propose a new software watermarking technique in which a dynamic graphic watermark is stored in the execution state of a program.

We extend prior research by Saavedra and Smith on designing microbenchmarks to measure data cache parameters. Unlike Saavedra and Smith, we measure the parameters by characterizing read accesses separately from write accesses; and we do not assume that the address mapping function is a bit-selection. We can measure the cache capacity C, block size b, and associativity a; we can measure the cache-hit access time and penalty for read and write; we can determine whether a cache allocates on write; we can detect write-back and write-through policies. We present experimental results for two CPU/cache structures, a 200 MHz Pentium with MMX and a 180 MHz Pentium Pro.

It has become common to distribute software in forms that are isomorphic to the original source code. An important example is Java bytecode. Since such codes are easy to decompile, they increase the risk of malicious reverse engineering attacks.In this paper we describe the design of a Java code obfuscator, a tool which - through the application of code transformations - converts a Java program into an equivalent one that is more difficult to reverse engineer.We describe a number of transformations which obfuscate control-flow. Transformations are evaluated with respect to potency (To what degree is a human reader confused?), resilience (How well are automatic deobfuscation attacks resisted?), cost (How much time/space overhead is added?), and stealth (How well does obfuscated code blend in with the original code?).The resilience of many control-altering transformations rely on the resilience of opaque predicates. These are boolean valued expressions whose values are known to the obfuscator but difficult to determine for an automatic deobfuscator. We show how to construct resilient, cheap, and stealthy opaque predicates based on the intractability of certain static analysis problems such as alias analysis.

The authors present a practical method for constructing optimal carry lookahead adders, of width n>

The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions.>

The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the proposed delay model, critical path delay is calculated taking into account not only the intrinsic gate delays but also the fanin and fanout contributions.>

The computational power of 2-D and 3-D processor arrays that contain a potentially large number of faults is analyzed. Both a random and a worst-case fault model are considered, and it is proved that in either scenario low-dimensional arrays are surprisingly fault tolerant. It is also shown how to route, sort, and perform systolic algorithms for problems such as matrix multiplication in optimal time on faulty arrays. In many cases, the running time is the same as if there were no faults in the array (up to constant factors). On the negative side, it is shown that any constant congestion embedding of an n*n fault-free array on an n*n array with Theta (n/sup 2/) random faults (or Theta (log n) worst-case faults) requires dilation Theta (log n). For 3-D arrays, knot theory is used to prove that the required dilation is Omega ( square root log n).>

A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS.>

A description is given of several modifications to the Ziv-Lempel data compression scheme that improve its compression ratio at a moderate cost in run time (J. Ziv, A. Lempel, 1976, 1977, 1978). The best algorithm reduces the length of a typical compressed text file by about 25%. The enhanced coder compresses approximately 2000 bytes of text every second before optimization, making it fast enough for regular use.>

Article Free Access Share on Systolic implementations of a move-to-front text compressor Authors: C. D. Thomborson Computer Science Department, University of Minnesota, 10 University Drive, Duluth, Minnesota Computer Science Department, University of Minnesota, 10 University Drive, Duluth, MinnesotaView Profile , B. W.-Y. Wei Department of Electrical Engineering, San Jose State University, 1 Washington Square, San Jose, California Department of Electrical Engineering, San Jose State University, 1 Washington Square, San Jose, CaliforniaView Profile Authors Info & Claims SPAA '89: Proceedings of the first annual ACM symposium on Parallel algorithms and architecturesMarch 1989 Pages 283–290https://doi.org/10.1145/72935.72965Published:01 March 1989Publication History 5citation274DownloadsMetricsTotal Citations5Total Downloads274Last 12 Months8Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We propose a language that can be used to describe configuration of rectilinear Steiner trees. Given a set of points in a plane indexed by integer coordinates, the execution of a pattern-description in our language will list a number of Steiner trees spanning the points. The Steiner trees that are produced will be used as input to a linear-program type global router for VLSI gate-arrays [10]. Other applications for our language include routing printed circuit boards and generating Steiner tree configurations for simulated-annealing type global routers [11].

We examine the problem of routing wires on a VLSI chip where the nodes to be connected are arranged in a two-dimensional array. We develop provably good algorithms that find a solution close to the optimal one with high probability. Our approximation algorithms solve the relevant 0-1 integer optimization problems by solving their relaxed versions and then rounding by an interesting probabilistic technique. One of our algorithms, using multicommodity flow, has applications to routing in circuit switching networks.

A scheme for maintaining a balanced search tree on γlg N + 1γparallel processors is described. The scheme is almost fully pipelined: γlg N + 1γ/2 search, insert, and delete operations may run concurrently. Each processor executes 0(1) instructions of a top-down 2-3-4 tree manipulation algorithm before passing the operation along to the next processor in the pipeline. Thus, the total delay per tree operation is O(lg N), and one tree operation completes every 0(1) time units.

We examine the problem of routing wires on a VLSI chip, where the pins to be connected are arranged in a regular rectangular array. We obtain tight bounds for the worst-case "channel-width" needed to route an n × n array, and develop provably good heuristics for the general case. An interesting "rounding algorithm" for obtaining integral approximations to solutions of linear equations is used to show the near-optimality of single-turn routings in the worst-case.

This paper surveys nine designs for VLSI circuits that compute N-element Fourier transforms. The largest of the designs requires O(N2 log N) units of silicon area; it can start a new Fourier transform every O(log N) time units. The smallest designs have about 1/Nth of this throughput, but they require only 1/Nth as much area.

The area-time complexity of sorting is analyzed under an updated model of VLSI computation. The new model makes a distinction between "processing" circuits and "memory" circuits; the latter are less important since they are denser and consume less power. Other adjustments to the model make it possible to compare pipelined and nonpipelined designs.

The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points (N) in the DFT: AT2≥ N2/16. This inequality holds for any chip design based on any algorithm, and is nearly tight when T = θ(N1/2) or T = θ(log N). A more general lower bound is also derived: ATx = Ω(N1+x/2), for 0≤×≤2.

A maximal vector of a set ~s one which is not less than any other vector m all components We derive a recurrence relation for computing the average number of maxunal vectors m a set of n vectors m d-space under the assumpUon that all (nl) a relative ordermgs are equally probable.Solving the recurrence shows that the average number of maxmaa is O((ln n) a-~) for fixed d We use this result to construct an algorithm for finding all the maxima that have expected running tmae hnear m n (for sets of vectors drawn under our assumptions) We then use the result to find an upper bound on the expected number of convex hull points m a random point set KE~ WORDS AND eHRASES maxtma of a set of vectors, average number of maxtma, expected-tsme algorithms, analysts of algorithms, convex hulls, dynamtc programming CR CATEGORIES" 5 25, 5.39, 5.42 Permtsston to copy without fee all or part of this material ts granted provtded that the copies are not made or distributed for direct commercial advantage, the ACM copyrtght notice and the tRle of the pubhcatlon and its date appear, and notice ts gtven that copying ts by permission of the Assoctatton for Computmg Machinery To copy otherwtse, or to repubhsh, reqmres a fee and/or specific permtsslon This research was supported m part by the Nattonal Soence Foundation under Grant MCS 75-222-55 and the Office of Naval Research under

A generalized connection network (GCN) is a switching network with N inputs and N outputs that can be set to pass any of the NNmappings of inputs onto outputs. This paper demonstrates an intimate connection between the problems of GCN construction, message routing on SIMD computers, and "resource partitioning." A GCN due to Ofman [7] is here improved to use less than 7.6N log N contact pairs, making it the minimal known construction.

Two algorithms for sorting n2 elements on an n×n mesh-connected processor array that require 0(n) routing and comparison steps are presented. The best previous algorithms take time 0(n log n). Our algorithms are shown to be optimal in time within small constant factors.