Yih-Kuen Tsay

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24ranked-venue papers
12as first author
1since 2021 · last 2021
0000-0002-5960-1615ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 14 · 6 first-author · 1 since 2021Theory of computation · 11 · 3 first-author · 1 since 2021Systems, architecture and hardware · 3 · 3 first-author
YearPublicationVenuePosition
2021 Congruence Relations for Büchi Automata
Yong Li 0031, Yih-Kuen Tsay, Andrea Turrini, Moshe Y. Vardi, Lijun Zhang 0001
FM2
2013 GOAL for Games, Omega-Automata, and Logics
Ming-Hsien Tsai 0001, Yih-Kuen Tsay, Yu-Shiang Hwang
CAV2
2013 Büchi Store: an open repository of ω-automata
Yih-Kuen Tsay, Ming-Hsien Tsai 0001, Jinn-Shu Chang, Yi-Wen Chang, Chi-Shiang Liu
Int. J. Softw. Tools Technol. Transf.1
2011 Büchi Store: An Open Repository of Büchi Automata
Yih-Kuen Tsay, Ming-Hsien Tsai 0001, Jinn-Shu Chang, Yi-Wen Chang
TACAS1
2010 Automated Assume-Guarantee Reasoning through Implicit Learning
Yu-Fang Chen 0001, Edmund M. Clarke, Azadeh Farzan, Ming-Hsien Tsai 0001, Yih-Kuen Tsay, Bow-Yaw Wang
CAV5
2010 Comparing Learning Algorithms in Automated Assume-Guarantee Reasoning
Yu-Fang Chen 0001, Edmund M. Clarke, Azadeh Farzan, Fei He 0001, Ming-Hsien Tsai 0001, Yih-Kuen Tsay, Bow-Yaw Wang
ISoLA (1)6
2010 Automatic numeric abstractions for heap-manipulating programs
abstract
We present a logic for relating heap-manipulating programs to numeric abstractions. These numeric abstractions are expressed as simple imperative programs over integer variables and have the property that termination and safety of the numeric program ensures termination and safety of the original, heap-manipulating program. We have implemented an automated version of this abstraction process and present experimental results for programs involving a variety of data structures.
Stephen Magill, Ming-Hsien Tsai 0001, Peter Lee 0001, Yih-Kuen Tsay
POPL4
2010 State of Büchi Complementation
Ming-Hsien Tsai 0001, Seth Fogarty, Moshe Y. Vardi, Yih-Kuen Tsay
CIAA4
2009 Learning Minimal Separating DFA's for Compositional Verification
Yu-Fang Chen 0001, Azadeh Farzan, Edmund M. Clarke, Yih-Kuen Tsay, Bow-Yaw Wang
TACAS4
2009 Tool support for learning Büchi automata and linear temporal logic
abstract
Abstract We introduce a graphical interactive tool, named GOAL, that can assist the user in understanding Büchi automata, linear temporal logic, and their relation. Büchi automata and linear temporal logic are closely related and have long served as fundamental building blocks of linear-time model checking. Understanding their relation is instrumental in discovering algorithmic solutions to model checking problems or simply in using those solutions, e.g., specifying a temporal property directly by an automaton rather than a temporal formula so that the property can be verified by an algorithm that operates on automata. One main function of the GOAL tool is translation of a temporal formula into an equivalent Büchi automaton that can be further manipulated visually. The user may edit the resulting automaton, attempting to optimize it, or simply run the automaton on some inputs to get a basic understanding of how it operates. GOAL includes a large number of translation algorithms, most of which support past temporal operators. With the option of viewing the intermediate steps of a translation, the user can quickly grasp how a translation algorithm works. The tool also provides various standard operations and tests on Büchi automata, in particular the equivalence test which is essential for checking if a hand-drawn automaton is correct in the sense that it is equivalent to some intended temporal formula or reference automaton. Several use cases are elaborated to show how these GOAL functions may be combined to facilitate the learning and teaching of Büchi automata and linear temporal logic.
Yih-Kuen Tsay, Yu-Fang Chen 0001, Ming-Hsien Tsai 0001, Kang-Nien Wu, Wen-Chin Chan, Chi-Jian Luo, Jinn-Shu Chang
Formal Aspects Comput.1
2008 THOR: A Tool for Reasoning about Shape and Arithmetic
Stephen Magill, Ming-Hsien Tsai 0001, Peter Lee 0001, Yih-Kuen Tsay
CAV4
2008 Extending Automated Compositional Verification to the Full Class of Omega-Regular Languages
Azadeh Farzan, Yu-Fang Chen 0001, Edmund M. Clarke, Yih-Kuen Tsay, Bow-Yaw Wang
TACAS4
2008 GOAL Extended: Towards a Research Tool for Omega Automata and Temporal Logic
Yih-Kuen Tsay, Yu-Fang Chen 0001, Ming-Hsien Tsai 0001, Wen-Chin Chan, Chi-Jian Luo
TACAS1
2008 Automated Compositional Reasoning of Intuitionistically Closed Regular Properties
Yih-Kuen Tsay, Bow-Yaw Wang
CIAA1
2007 GOAL: A Graphical Tool for Manipulating Büchi Automata and Temporal Formulae
Yih-Kuen Tsay, Yu-Fang Chen 0001, Ming-Hsien Tsai 0001, Kang-Nien Wu, Wen-Chin Chan
TACAS1
2000 Compositional Verification in Linear-Time Temporal Logic
Yih-Kuen Tsay
FoSSaCS1
2000 Algorithmic Analysis of Programs with Well Quasi-ordered Domains
Parosh Aziz Abdulla, Karlis Cerans, Bengt Jonsson 0001, Yih-Kuen Tsay
Inf. Comput.4
1998 Deriving a Scalable Algorithm for Mutual Exclusion
Yih-Kuen Tsay
DISC1
1996 General Decidability Theorems for Infinite-State Systems
abstract
Over the last few years there has been an increasing research effort directed towards the automatic verification of infinite state systems. This paper is concerned with identifying general mathematical structures which can serve as sufficient conditions for achieving decidability. We present decidability results for a class of systems (called well-structured systems), which consist of a finite control part operating on an infinite data domain. The results assume that the data domain is equipped with a well-ordered and well-founded preorder such that the transition relation is "monotonic" (is a simulation) with respect to the preorder. We show that the following properties are decidable for well-structured systems: reachability; eventuality; and simulation. We also describe how these general principles subsume several decidability results from the literature about timed automata, relational automata, Petri nets, and lossy channel systems.
Parosh Aziz Abdulla, Karlis Cerans, Bengt Jonsson 0001, Yih-Kuen Tsay
LICS4
1996 Assumption/Guarantee Specifications in Linear-Time Temporal Logic
Bengt Jonsson 0001, Yih-Kuen Tsay
Theor. Comput. Sci.2
1995 Deducing Fairness Properties in UNITY Logic - A New Completeness Result
abstract
We explore the use of UNITY logic in specifying and verifying fairness properties of UNITY and UNITY-like programs whose semantics can be modeled by weakly fair transition systems. For such programs, strong fairness properties in the form of “if p holds infinitely often then q also holds infinitely often □◊p⇒□◊q, can be expressed as conditional UNITY properties of the form of “Hypothesis: true→p Conclusion:true→q”. We show that UNITY logic is relatively complete for proving such properties; in the process, a simple inference rule is derived. Specification and verification of weak fairness properties are also discussed.
Yih-Kuen Tsay, Rajive L. Bagrodia
ACM Trans. Program. Lang. Syst.1
1994 Fault-Tolerant Algorithms for Fair Interprocess Synchronization
abstract
The implementation of nondeterministic pairwise synchronous communication among a set of asynchronous processes is modeled as the binary interaction problem. The paper describes an algorithm for this problem that satisfies a strong fairness property that guarantees freedom from process starvation. This is the first algorithm for binary interactions with strong fairness whose message cost and response time are independent of the total number of processes in the system. The paper also describes how the fair algorithm may be extended to tolerate detectable fail-stop failures. Finally, we show how any solution to the dining philosophers problem can be embedded to design a fair algorithm for binary interactions. In particular, this embedding is used to derive a fair algorithm that can cope with undetectable fail-stop failures.>
Yih-Kuen Tsay, Rajive L. Bagrodia
IEEE Trans. Parallel Distributed Syst.1
1993 Some Impossibility Results in Interprocess Synchronization
Yih-Kuen Tsay, Rajive L. Bagrodia
Distributed Comput.1
1992 A Real-Time Algorithm for Fair Interprocess Synchronization
abstract
The implementation of nondeterministic pairwise synchronous communication among a set of asynchronous processes is modeled as a binary interaction problem. An algorithm for this problem, which satisfies a strong fairness property that guarantees freedom from process starvation, is described. The message and time complexities are independent of the total number of processes in the system. The ways in which the algorithm may be extended to cope with fail-stop process failures are discussed.>
Yih-Kuen Tsay, Rajive L. Bagrodia
ICDCS1