VLDB 2026 Research / reviewers in the wild / expert
Hasan Ural
dblp:u/HasanUral
· DBLP profile ↗
72ranked-venue papers
19as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 34 · 11 first-authorSoftware engineering, systems software and programming languages · 26 · 6 first-authorTheory of computation · 9 · 3 first-authorDatabases, data management, data science and information retrieval · 8 · 2 first-authorSystems, architecture and hardware · 7 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 4 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
8 papers |
Software testing · 88% Program verification · 7% Program analysis · 3% | |
| Computer networks
6 papers |
Network management and operations · 85% Internet architecture and protocols · 15% | |
| Theoretical computer science
7 papers |
Automata and formal languages · 79% Automated reasoning and model checking · 13% Computational complexity · 8% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 24 heaviest of 27, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Software testing
model-based testing |
0.1 | 2 | 2006 | Optimizing the Length of Checking Sequences · IEEE Trans. Computers 2006 Reduced Length Checking Sequences · IEEE Trans. Computers 2002 |
Network management and operations › network testing
protocol conformance testing |
0.0 | 5 | 1995 | Synchronizable test sequences based on multiple UIO sequences · IEEE/ACM Trans. Netw. 1995 Optimal length test sequence generation using distinguishing sequences · IEEE/ACM Trans. Netw. 1993 Minimum-Cost Synchronizable Test Sequence Generation via the DuplexU Digraph · INFOCOM 1993 |
Software testing › structural testing
data flow testing |
0.0 | 1 | 2003 | Data Flow Testing as Model Checking · ICSE 2003 |
Software testing › model-based testing › model-based test generation
model checking-based test generation |
0.0 | 1 | 2003 | Data Flow Testing as Model Checking · ICSE 2003 |
Network management and operations › network testing › protocol conformance testing
test sequence generation |
0.0 | 4 | 1995 | Synchronizable test sequences based on multiple UIO sequences · IEEE/ACM Trans. Netw. 1995 Optimal length test sequence generation using distinguishing sequences · IEEE/ACM Trans. Netw. 1993 Minimum-Cost Synchronizable Test Sequence Generation via the DuplexU Digraph · INFOCOM 1993 |
Software testing › model-based testing › finite state machine testing › state identification
distinguishing sequence |
0.0 | 2 | 2006 | Optimizing the Length of Checking Sequences · IEEE Trans. Computers 2006 Reduced Length Checking Sequences · IEEE Trans. Computers 2002 |
Software testing › model-based testing
finite state machine testing |
0.0 | 2 | 2006 | Optimizing the Length of Checking Sequences · IEEE Trans. Computers 2006 Reduced Length Checking Sequences · IEEE Trans. Computers 2002 |
Automata and formal languages
finite automata |
0.0 | 2 | 1995 | Synchronizable test sequences based on multiple UIO sequences · IEEE/ACM Trans. Netw. 1995 Optimal length test sequence generation using distinguishing sequences · IEEE/ACM Trans. Netw. 1993 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1997 | On Minimizing the Lengths of Checking Sequences · IEEE Trans. Computers 1997 |
Software testing › specification-based testing › conformance testing
protocol conformance testing |
0.0 | 2 | 1991 | On the Complexity of Generating Optimal Test Sequences · IEEE Trans. Software Eng. 1991 A test sequence selection method for protocol testing · IEEE Trans. Commun. 1991 |
Automata and formal languages › petri nets
fair reachability analysis |
0.0 | 1 | 1995 | Generalizing Fair Reachability Analysis to Protocols with Arbitrary Topology (Abstract) · PODC 1995 |
Automated reasoning and model checking
reachability |
0.0 | 1 | 1995 | Generalizing Fair Reachability Analysis to Protocols with Arbitrary Topology (Abstract) · PODC 1995 |
Automata and formal languages › finite automata › sequential machines › state identification
unique input output sequences |
0.0 | 1 | 1995 | Synchronizable test sequences based on multiple UIO sequences · IEEE/ACM Trans. Netw. 1995 |
Program verification
model checking |
0.0 | 1 | 2003 | Data Flow Testing as Model Checking · ICSE 2003 |
Software testing › test generation
test sequence generation |
0.0 | 2 | 1991 | On the Complexity of Generating Optimal Test Sequences · IEEE Trans. Software Eng. 1991 An interactive test sequence generator · SIGCOMM 1986 |
Internet architecture and protocols › protocol engineering
protocol testing |
0.0 | 1 | 1993 | Optimal length test sequence generation using distinguishing sequences · IEEE/ACM Trans. Netw. 1993 |
Program analysis
data flow analysis |
0.0 | 1 | 1993 | Modeling Software for Accurate Data Flow Representation · ICSE 1993 |
Program verification › model checking › state space exploration
reachability analysis |
0.0 | 1 | 1993 | Language-based analysis of communicating finite state machines · ICNP 1993 |
Automata and formal languages › infinite-state systems › channel systems
communicating finite state machines |
0.0 | 1 | 1993 | Language-based analysis of communicating finite state machines · ICNP 1993 |
Automata and formal languages › finite automata
distinguishing sequences |
0.0 | 1 | 1993 | Optimal length test sequence generation using distinguishing sequences · IEEE/ACM Trans. Netw. 1993 |
Automata and formal languages › finite automata
finite state machine testing |
0.0 | 1 | 1997 | On Minimizing the Lengths of Checking Sequences · IEEE Trans. Computers 1997 |
Network management and operations
protocol verification |
0.0 | 1 | 1995 | Generalizing Fair Reachability Analysis to Protocols with Arbitrary Topology (Abstract) · PODC 1995 |
Requirements engineering and software design
software modeling |
0.0 | 1 | 1993 | Modeling Software for Accurate Data Flow Representation · ICSE 1993 |
Automata and formal languages
protocol specification |
0.0 | 1 | 1993 | Language-based analysis of communicating finite state machines · ICNP 1993 |
Methods — techniques the papers use, named apart from their topics
combinatorial optimization · 0.1heuristic algorithm · 0.0temporal logic · 0.0model checking · 0.0CTL · 0.0rural postman tour · 0.0state recognition sequences · 0.0optimization of state recognition sequences · 0.0graph transformation · 0.0parallel reachability analysis · 0.0overlapping test segments · 0.0d-method · 0.0distinguishing sequences · 0.0distinguishing sequence · 0.0UIO sequences · 0.0automatic test generation · 0.0flowgraph modeling · 0.0finite-state machine · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Reduced checking sequences using unreliable reset
Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün |
Inf. Process. Lett. | 2 |
| 2013 | Regression test suite selection using dependence analysisabstractSUMMARY Dependence analysis on an Extended Finite State Machine representation of the requirements of a system under test identifies various types of control and data dependencies between transitions caused by a set of modifications on the requirements. These particular types of dependencies capture the effects of the modifications, that is, their direct effects on the changed parts of the system and their side effects on the unchanged parts of the system. Recent work on model‐based regression testing shows that dependencies capturing direct effects and side effects of the changes made on the requirements can be used for regression test suite (RTS) reduction (reducing the size of a given test suite by eliminating redundancies), for RTS prioritization (ordering test cases in a given test suite for early fault detection), or for RTS generation (designing a test suite covering the identified dependencies). This paper proposes an additional use of such dependencies, namely, RTS selection, which is the process of selecting a subset of a given test suite to form an RTS by considering the coverage of dependencies related to the effects of the modifications. The dependencies marked during this process as uncovered provide a basis for augmenting an (incomplete) RTS with test cases covering uncovered dependencies. Copyright © 2012 John Wiley & Sons, Ltd. Hasan Ural, Hüsnü Yenigün |
J. Softw. Evol. Process. | 1 |
| 2012 | On Capturing Effects of Modifications as Data DependenciesabstractDependence analysis on an Extended Finite State Machine (EFSM) representation of the requirements of a system under test has been used in requirements-based regression testing for regression test suite (RTS) reduction (reducing the size of a given test suite by eliminating redundancies), for RTS prioritization (ordering test cases in a given test suite for early fault detection) or for RTS selection (selecting a subset of a test suite covering the identified dependencies). These particular uses of dependence analysis are based on definitions of various types of control and data dependencies (between transitions in an EFSM) caused by a given set of modifications on the requirements. This abstract considers the definitions of data dependencies, gives examples of incompleteness of existing definitions, and presents insights on completing these definitions. Hasan Ural, Hüsnü Yenigün |
COMPSAC | 1 |
| 2012 | Regression test suite prioritization using system modelsabstractSUMMARY During regression testing, a modified system is often retested using an existing test suite. Since the size of the test suite may be very large, testers are interested in detecting faults in the modified system as early as possible during this retesting process. Test prioritization attempts to order tests for execution so that the chances of early detection of faults during retesting are increased. The existing prioritization methods are based on the source code of the system under test. In this paper, we present and evaluate two model‐based selective methods and a dependence‐based method of test prioritization utilizing the state‐based model of the system under test. These methods assume that the modifications are made both on the system under test and its model. The existing test suite is executed on the system model and information about this execution is used to prioritize tests. Execution of the model is inexpensive as compared with execution of the system under test; therefore, the overhead associated with test prioritization is relatively small. In addition, we present an analytical framework for evaluation of test prioritization methods. This framework may reduce the cost of evaluation as compared with the framework that is based on observation. We have performed an empirical study in which we compared different test prioritization methods. The results of the empirical study suggest that system models may improve the effectiveness of test prioritization with respect to early fault detection. Copyright © 2011 John Wiley & Sons, Ltd. Luay Ho Tahat, Bogdan Korel, Mark Harman, Hasan Ural |
Softw. Test. Verification Reliab. | 4 |
| 2010 | Generating a checking sequence with a minimum number of reset transitions
Robert M. Hierons, Hasan Ural |
Autom. Softw. Eng. | 2 |
| 2010 | Lower bounds on lengths of checking sequencesabstractAbstract Lower bounds on the lengths of checking sequences constructed for testing from Finite State Machine-based specifications are established. These bounds consider the case where a distinguishing sequence is used in forming state recognition and transition verification subsequences and identify the effects of overlapping among such subsequences. Empirical results show that the existing methods for construction of checking sequences provide checking sequences with lengths that are within acceptable distance to these lower bounds. Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün, Ji Chao Zhang |
Formal Aspects Comput. | 2 |
| 2009 | Checking Sequence Construction Using Adaptive and Preset Distinguishing SequencesabstractMethods for testing from finite state machine-based specifications often require the existence of a preset distinguishing sequence for constructing checking sequences. It has been shown that an adaptive distinguishing sequence is sufficient for these methods. This result is significant because adaptive distinguishing sequences are strictly more common and up to exponentially shorter than preset ones. However, there has been no study on the actual effect of using adaptive distinguishing sequences on the length of checking sequences. This paper describes experiments that show that checking sequences constructed using adaptive distinguishing sequences are almost consistently shorter than those based on preset distinguishing sequences. This is investigated for three different checking sequence generation methods and the results obtained from an extensive experimental study are given. Robert M. Hierons, Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün |
SEFM | 3 |
| 2009 | Overcoming controllability problems with fewest channels between testers
Robert M. Hierons, Hasan Ural |
Comput. Networks | 2 |
| 2009 | Update Processing in Instance-Mapped P2P Data Sharing SystemsabstractWe consider the problem of update processing in a peer-to-peer (P2P) database network where each peer consists of an independently created relational database. We assume that peers store related data, but data has heterogeneity wrt instances and schemas. The differences in schema and data vocabulary are bridged by value correspondences called mapping tables. Peers build an overlay network called acquaintance network, in which each peer may get acquainted with any other peer that stores related data. In this setting, the updates are free to initiate in any peer and are executed over other peers which are acquainted directly or indirectly with the updates initiator. The execution of an update is achieved by translating, through mapping tables, the update into a set of updates that are executed against the acquainted peers. We consider both the soundness and completeness of update translation. When updates are generated and propagated in the network initiated from a peer, a tree is built dynamically called Update Dependency Tree (UDT). The UDT depicts the relationships among the component updates generated from the initial update. We also discuss the issues of the update propagation when a peer is temporarily unavailable or offline. Our propagation mechanism keeps track of a peer when the peer is not available for a certain period of time and once the peer comes back online the system propagates the updates destined to the returning peer to keep it's database synchronized. Moreover, conflict detection and resolution strategies have been proposed for such a dynamic P2P database network. We have implemented and experimentally tested a prototype of our update processing mechanism on a small P2P database network. We show the results of our experiments. Mehedi Masud, Iluju Kiringa, Hasan Ural |
Int. J. Cooperative Inf. Syst. | 3 |
| 2009 | Regression test suite reduction based on SDL models of system requirementsabstractAbstract This paper proposes a model‐based regression test suite reduction method. The proposed method considers an SDL model representing the requirements of a system under test and a set of modifications on this model, applies dependence analysis to identify interaction patterns related to each type of modifications, i.e., adding, deleting, and changing transitions in the SDL model, and reduces the size of a given regression test suite by examining interaction patterns covered by each test case in the test suite. Results of empirical studies are reported. Copyright © 2009 John Wiley & Sons, Ltd. Yanping Chen 0004, Robert L. Probert, Hasan Ural |
J. Softw. Maintenance Res. Pract. | 3 |
| 2008 | The Effect of the Distributed Test Architecture on the Power of TestingabstractThere has been much interest in testing from finite-state machines (FSMs). If the system under test can be modelled by the (minimal) FSM N then testing from an (minimal) FSM M is testing to check that N is isomorphic to M. In the distributed test architecture, there are multiple interfaces/ports and there is a tester at each port. This can introduce controllability/synchronization and observability problems. This paper shows that the restriction to test sequences that do not cause controllability problems and the inability to observe the global behaviour in the distributed test architecture, and thus relying only on the local behaviour at remote testers, introduces fundamental limitations into testing. There exist minimal FSMs that are not equivalent, and so are not isomorphic, and yet cannot be distinguished by testing in this architecture without introducing controllability problems. Similarly, an FSM may have non-equivalent states that cannot be distinguished in the distributed test architecture without causing controllability problems: these are said to be locally s-equivalent and otherwise they are locally s-distinguishable. This paper introduces the notion of two states or FSMs being locally s-equivalent and formalizes the power of testing in the distributed test architecture in terms of local s-equivalence. It introduces a polynomial time algorithm that, given an FSM M, determines which states of M are locally s-equivalent and produces minimal length input sequences that locally s-distinguish states that are not locally s-equivalent. An FSM is locally s-minimal if it has no pair of locally s-equivalent states. This paper gives an algorithm that takes an FSM M and returns a locally s-minimal FSM M′ that is locally s-equivalent to M. Robert M. Hierons, Hasan Ural |
Comput. J. | 2 |
| 2008 | Checking sequences for distributed test architectures
Robert M. Hierons, Hasan Ural |
Distributed Comput. | 2 |
| 2007 | Recovering Repetitive Sub-functions from Observations
Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün |
FORTE | 2 |
| 2007 | Reducing the cost of applying adaptive test cases
Robert M. Hierons, Hasan Ural |
Comput. Networks | 2 |
| 2006 | Minimizing Coordination Channels in Distributed Testing
Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün |
FORTE | 2 |
| 2006 | Constructing checking sequences for distributed testingabstractAbstract The objective of testing is to determine whether an implementation under test conforms to its specification. In distributed test architectures involving multiple remote testers, this objective can be complicated by the fact that testers may encounter coordination problems relating to controllability (synchronization) and observability during the application of tests. Based on a finite state machine (FSM) specification of the externally observable behaviour of a distributed system and a distinguishing sequence, this paper proposes a method for constructing a checking sequence where there is no potential controllability or observability problems, and where the use of external coordination message exchanges among testers is minimized. The proposed method does not assume a reliable reset feature in the implementations of the given FSM to be tested by the resulting checking sequence. Hasan Ural, Craig Williams |
Formal Aspects Comput. | 1 |
| 2006 | Overcoming observability problems in distributed test architectures
Jessica Chen, Robert M. Hierons, Hasan Ural |
Inf. Process. Lett. | 3 |
| 2006 | Distributed delay constrained multicast routing algorithm with efficient fault recoveryabstractAbstract Existing distributed delay constrained multicast routing algorithms construct a multicast tree in a sequential fashion and need to be restarted when failures occur during the multicast tree construction phase or during an on‐going multicast session. This article proposes an efficient distributed delay constrained multicast routing algorithm that constructs a multicast tree in a concurrent fashion by taking advantage of the concurrency in the underlying distributed computation. The proposed algorithm has a message complexity of O(mn) and time complexity of O(n) in the worst case, wheremis the number of destinations andnis the number of nodes in the network. It constructs multicast trees with the same tree costs as the ones constructed by well‐known algorithms such as DKPP and DSHP while utilizing 409 to 1734 times fewer messages and 56 to 364 times less time than these algorithms under comparable success rate ratios. The proposed algorithm has been augmented with a fault recovery mechanism that efficiently constructs a multicast tree when failures occur during the tree construction phase and recovers from any failure in the multicast tree during an on‐going multicast session without interrupting the running traffic on the unaffected portion of the tree. © 2005 Wiley Periodicals, Inc. NETWORKS, Vol. 47(1), 37–51 2006 Hasan Ural, Keqin Zhu |
Networks | 1 |
| 2006 | Optimizing the Length of Checking SequencesabstractA checking sequence, generated from a finite state machine, is a test sequence that is guaranteed to lead to a failure if the system under test is faulty and has no more states than the specification. The problem of generating a checking sequence for a finite state machine M is simplified if M has a distinguishing sequence: an input sequence D~ with the property that the output sequence produced by M in response to D is different for the different states of M. Previous work has shown that, where a distinguishing sequence is known, an efficient checking sequence can be produced from the elements of a set A of sequences that verify the distinguishing sequence used and the elements of a set /spl gamma/ of subsequences that test the individual transitions by following each transition t by the distinguishing sequence that verifies the final state of t. In this previous work, A is a predefined set and /spl gamma/ is defined in terms of A. The checking sequence is produced by connecting the elements of /spl gamma/ and A to form a single sequence, using a predefined acyclic set E/sub c/ of transitions. An optimization algorithm is used in order to produce the shortest such checking sequence that can be generated on the basis of the given A and E/sub c/. However, this previous work did not state how the sets A and E/sub c/ should be chosen. This paper investigates the problem of finding appropriate A and E/sub c/ to be used in checking sequence generation. We show how a set A may be chosen so that it minimizes the sum of the lengths of the sequences to be combined. Further, we show that the optimization step, in the checking sequence generation algorithm, may be adapted so that it generates the optimal E/sub c/. Experiments are used to evaluate the proposed method. Robert M. Hierons, Hasan Ural |
IEEE Trans. Computers | 2 |
| 2005 | Resolving Observability Problems in Distributed Test Architectures
Jessica Chen, Robert M. Hierons, Hasan Ural |
FORTE | 3 |
| 2005 | Minimizing the number of inputs while applying adaptive test cases
Guy-Vincent Jourdan, Hasan Ural, Nejib Zaguia |
Inf. Process. Lett. | 2 |
| 2004 | Conditions for Resolving Observability Problems in Distributed Testing
Jessica Chen, Robert M. Hierons, Hasan Ural |
FORTE | 3 |
| 2004 | Towards Design Recovery from Observations
Hasan Ural, Hüsnü Yenigün |
FORTE | 1 |
| 2004 | On the testability of SDL specifications
Robert M. Hierons, T.-H. Kim, Hasan Ural |
Comput. Networks | 3 |
| 2003 | Concerning the Ordering of Adaptive Test Sequences
Robert M. Hierons, Hasan Ural |
FORTE | 2 |
| 2003 | Data Flow Testing as Model CheckingabstractThis paper presents a model checking-based approach to dataflow testing. We characterize dataflow oriented coverage criteria in temporal logic such that the problem of test generation is reduced to the problem of finding witnesses for a set of temporal logic formulas. The capability of model checkers to construct witnesses and counterexamples allows test generation to be fully automatic. We discuss complexity issues in minimal cost test generation and describe heuristic test generation algorithms. We illustrate our approach using CTL as temporal logic and SMV as model checker. Hyoung Seok Hong, Sung Deok Cha, Insup Lee 0001, Oleg Sokolsky, Hasan Ural |
ICSE | 5 |
| 2003 | UIO sequence based checking sequences for distributed test architectures
Robert M. Hierons, Hasan Ural |
Inf. Softw. Technol. | 2 |
| 2003 | Distributed testing without encountering controllability and observability problems
Hasan Ural, David Whittier |
Inf. Process. Lett. | 1 |
| 2002 | Expanding an Extended Finite State Machine to aid TestabilityabstractThe problem of testing from an extended finite state machine (EFSM) is complicated by the presence of infeasible paths. This paper considers the problem of expanding an EFSM in order to bypass the infeasible path problem. The approach is developed for the specification language SDL but, in order to aid generality, the rewriting process is broken down into two phases: producing a normal form EFSM (NF-EFSM) from an SDL specification and then expanding this NF-EFSM. Robert M. Hierons, T.-H. Kim, Hasan Ural |
COMPSAC | 3 |
| 2002 | A Temporal Logic Based Theory of Test Coverage and Generation
Hyoung Seok Hong, Insup Lee 0001, Oleg Sokolsky, Hasan Ural |
TACAS | 4 |
| 2002 | Construction of Deadlock-free Designs of Communication Protocols from ObservationabstractReverse engineering in distributed systems is essential to recovering the designs of large and complex distributed systems that evolve often without proper documentation. This paper proposes rules for the automated construction of deadlock-free designs of communication protocols from the execution histories of existing systems, defines the properties of the constructed designs and identifies the conditions for a constructed design to be equivalent to the presumed design implied by the given set of global observations. Xiao Jun Chen, Hasan Ural |
Comput. J. | 2 |
| 2002 | Reduced Length Checking SequencesabstractHere, the method proposed by Ural, Wu and Zhang (1997) for constructing minimal-length checking sequences based on distinguishing sequences is improved. The improvement is based on optimizations of the state recognition sequences and their use in constructing test segments. It is shown that the proposed improvement further reduces the length of checking sequences produced from minimal, completely specified, and deterministic finite state machines. Robert M. Hierons, Hasan Ural |
IEEE Trans. Computers | 2 |
| 2001 | Rapid generation of functional tests using MSCs, SDL and TTCN
Robert L. Probert, Hasan Ural, Alan W. Williams |
Comput. Commun. | 2 |
| 2000 | Test generation based on control and data dependencies within system specifications in SDL
Hasan Ural, Kassem Saleh, Alan W. Williams |
Comput. Commun. | 1 |
| 2000 | A test sequence selection method for statechartsabstractThis paper presents a method for the selection of test sequences from statecharts. It is shown that a statechart can be transformed into a flow graph modelling the flow of both control and data in the statechart. The transformation enables the application of conventional control and data flow analysis techniques to test sequence selection from statecharts. The resulting set of test sequences provides the capability of determining whether an implementation establishes the desired flow of control and data expressed in statecharts. Copyright © 2000 John Wiley & Sons, Ltd. Hyoung Seok Hong, Young Gon Kim, Sung Deok Cha, Doo-Hwan Bae, Hasan Ural |
Softw. Test. Verification Reliab. | 5 |
| 1999 | Submodule construction from concurrent system specifications
Esfandiar Haghverdi, Hasan Ural |
Inf. Softw. Technol. | 2 |
| 1999 | Efficient checking sequences for testing finite state machines
Kemal Inan, Hasan Ural |
Inf. Softw. Technol. | 2 |
| 1998 | On Improving Reachability Analysis for Verifying Progress Properties for Networks of CFSMsabstractState explosion is well-known to be the principle limitation in protocol verification. In this paper, leaping reachability analysis (LRA) is advocated as an incremental improvement of a verification technique called simultaneous reachability analysis (SRA) to tackle state explosion. SRA is a relief strategy for the verification of progress properties of protocols modeled as networks of communicating finite state machines (CFSMs) without any topological or structural constraints. The improvement is a uniform and property-driven relief strategy which proves to be adequate for detecting all deadlocks, all non-executable transitions, all unspecified receptions and all buffer overflows in a protocol specified in the CFSM model. Experiments show that LRA can largely relieve the state explosion problem by reducing the amount of storage space and execution time required for verification. Hans van der Schoot, Hasan Ural |
ICDCS | 2 |
| 1998 | Erratum to 'Protocol validation by simultaneous reachability analysis' : [Computer Communications 20 (1997) 772-788]
Kadir Özdemir, Hasan Ural |
Comput. Commun. | 2 |
| 1998 | Erratum to "Construction of checking sequences based on characterization sets" : [Computer Communications 18 (1995) 911-920]
Ali Rezaki, Hasan Ural |
Comput. Commun. | 2 |
| 1998 | An Improvement of Partial-Order VerificationabstractPartial-order reduction methods form a collection of state exploration techniques set to relieve the state-explosion problem in concurrent program verification. Their use often reduces significantly the memory needed for verifying local and termination properties of concurrent programs and, moreover, for verifying that concurrent programs satisfy their linear-time temporal logic specifications (i.e. for LTL model-checking). One particular such method is implemented in the verification system SPIN, which is considered to be one of the most efficient and most widely used LTL model-checkers. This paper builds on SPIN's partial-order reduction method to yield an approach that enables further space reductions for verifying concurrent programs. © 1998 John Wiley & Sons, Ltd. Hans van der Schoot, Hasan Ural |
Softw. Test. Verification Reliab. | 2 |
| 1997 | Protocol validation by simultaneous reachability analysis
Kadir Özdemir, Hasan Ural |
Comput. Commun. | 2 |
| 1997 | Data Flow Analysis of System Specifications in LotosabstractIn LOTOS, a system is specified as a behaviour expression describing the externally observable behaviour of the system in terms of possible sequences of interactions between the system and its environment. The desired control flow and data flow that must be established by a possible implementation of the system are specified in the behaviour expression as implicit enumerations of allowed sequences of interaction identifiers and relationships among interaction parameters, respectively. A model exposing the desired flow of data within the allowed control flow expressed in a system specification in LOTOS is presented. Based on the explicit information provided by the model, data flow anomaly detection and data flow oriented test selection are facilitated. A comprehensive example, i.e. an alternating bit protocol specification, is used to illustrate both these validation activities. An error in this specification is revealed by the analysis of a data flow anomaly detected within the specification. A set of test paths is derived from the specification by the application of an existing data flow oriented test selection criterion, called all-uses criterion. Hans van der Schoot, Hasan Ural |
Int. J. Softw. Eng. Knowl. Eng. | 2 |
| 1997 | On Minimizing the Lengths of Checking SequencesabstractA general model for constructing minimal length checking sequences employing a distinguishing sequence is proposed. The model is based on characteristics of checking sequences and a set of state recognition sequences. Some existing methods are shown to be special cases of the proposed model and are proven to construct checking sequences. The minimality of the resulting checking sequences is discussed and a heuristic algorithm for the construction of minimal length checking sequences is given. Hasan Ural, Xiaolin Wu 0001, Fan Zhang 0001 |
IEEE Trans. Computers | 1 |
| 1996 | Deadlock Detection by Pair Reachability Analysis: From Cyclic to Multi-Cyclic Protocols (and Beyond?)abstractWe generalize the technique of fair reachability analysis to multi-cyclic protocols modeled as networks of communicating finite state machines, where a number of cyclic protocols are interconnected in such a way that any two component cyclic protocols share at most one process and each channel in the protocol belongs to exactly one component cyclic protocol. By composing the fair reachability relations of the component cyclic protocols, we prove that the set of fair reachable states of a multi-cyclic protocol is exactly the set of reachable states that are of equal channel length with respect to each of its component cyclic protocols. As a result, each deadlock state is fair reachable, and deadlock detection is decidable for the class of multi-cyclic protocols whose fair reachable state spaces are finite. Under the assumption that the underlying communication topology of a protocol is strongly connected, we show that fair reachability analysis is inherently infeasible for logical correctness validation beyond multi-cyclic protocols. Hong Liu 0004, Raymond E. Miller, Hans van der Schoot, Hasan Ural |
ICDCS | 4 |
| 1995 | Generalizing Fair Reachability Analysis to Protocols with Arbitrary Topology (Abstract)abstractNo abstract available. Hans van der Schoot, Hasan Ural |
PODC | 2 |
| 1995 | Data Flow Oriented Test Selection for Lotos
Hans van der Schoot, Hasan Ural |
Comput. Networks ISDN Syst. | 2 |
| 1995 | Construction of checking sequences based on characterization sets
Ali Rezaki, Hasan Ural |
Comput. Commun. | 2 |
| 1995 | Lower bounds for the length of test sequences using UIOsabstractAbstract The optimality of the length of a test sequence for a given finite‐state machine can be determined only with respect to the class of test sequences that employ the same number and type of state identification/verification (SIV) sequences and satisfy the same requirements for the starting and terminating states. Given a certain number and type of SIV sequences, we identify three different types of optimality for test sequences: Type11 requires test sequences to begin and end at the initial state; Type1y requires only that test sequences begin at the initial state; and Typexy imposes no requirements whatsoever on the starting and terminating states. Based on these definitions, we investigate the case where Unique Input Output (UIO) sequences are given as SIV sequences and derive lower bounds for the length of test sequences of Type11, Type1y, and Typexy. Marion Rodrigues, Hasan Ural |
Networks | 2 |
| 1995 | Synchronizable test sequences based on multiple UIO sequencesabstractA test sequence generation method is proposed for testing the conformance of a protocol implementation to its specification in a remote testing system where both external synchronization and input/output operation costs are taken into consideration. The method consists of a set of transformation rules that constructs a duplexU digraph from a given finite state machine (FSM) representation of a protocol specification; and an algorithm that finds a rural postman tour in the duplexU digraph to generate a synchronizable test sequence utilizing multiple UIO sequences. If the protocol satisfies a specific property, namely, the transitions to be tested and the UIO sequences to be employed form a weakly-connected subgraph of the duplexU digraph, the proposed algorithm yields a minimum-cost test sequence. X.25 DTE and ISO Class 0 transport protocols are shown to possess this property. Otherwise, the algorithm yields a test sequence whose cost is within a bound from the cost of the minimum-cost test sequence. The bound for the test sequence generated from the Q.931 network-side protocol is shown to be the cost sum of an input/output operation pair and an external synchronization operation.> Wen-Huei Chen, Hasan Ural |
IEEE/ACM Trans. Netw. | 2 |
| 1994 | Modified distributed snapshots algorithm for protocol stabilization
Kassem Saleh, Hasan Ural, Anjali Agarwal |
Comput. Commun. | 2 |
| 1993 | Test Generation by Exposing Control and Data Dependencies Within System Specifications in SDL
Hasan Ural, Alan W. Williams |
FORTE | 1 |
| 1993 | Language-based analysis of communicating finite state machinesabstractThe authors present an efficient method for extracting a behavior description of a process (communicating finite state machine), as constrained by a given protocol. In the case where the constrained behavior corresponds to the unconstrained behavior depicted by the process specification, the process is said to be effective. The authors call the derived behavior description a process event graph (PEG). By comparing the PEG with the process specification, they determine whether a process in a protocol is effective. Two extensions to the basic algorithm are given, one to introduce parallelism to reachability analysis and one to detect traces that lead to process blockage. The authors focus initially on the two-process case, and then consider implications of more general protocols.> Jan Huus, Hasan Ural |
ICNP | 2 |
| 1993 | Modeling Software for Accurate Data Flow Representation
Hasan Ural |
ICSE | 1 |
| 1993 | Minimum-Cost Synchronizable Test Sequence Generation via the DuplexU DigraphabstractA test sequence generation method is proposed for testing the conformance of a protocol implementation to its specification in a remote testing system, taking both external synchronization and input/output operation costs into consideration. The method consists of a set of transformation rules that constructs a duplexU digraph from a given finite state machine (FSM) representation of a protocol specification and a heuristic algorithm that finds a rural postman tour in the duplexU digraph to generate a synchronizable test sequence utilizing multiple UIO sequences. If the protocol satisfies a specific property, the heuristic algorithm yields a minimum-cost test sequence. The X.25 DTE and ISO Class 0 Transport protocols are proved to possess this specific property. otherwise, the heuristic algorithm yields a test sequence whose cost is within a bound from the cost of the minimum-cost test sequence. The bound for the test sequence generated from the Q.931 Network-side protocol is shown to be the cost sum of an input/output operation and an external synchronization operation.> Wen-Huei Chen, Chuan Yi Tang, Hasan Ural |
INFOCOM | 3 |
| 1993 | Synchronizable test sequence generation using UIO sequences
Hasan Ural |
Comput. Commun. | 1 |
| 1993 | Exact Solutions for the Construction of Optimal Length Test Sequences
Marion Rodrigues, Hasan Ural |
Inf. Process. Lett. | 2 |
| 1993 | Optimal length test sequence generation using distinguishing sequencesabstractThe optimization of the length of test sequences for finite state machine based protocol conformance testing is studied. The study focuses on test generation methods, called D-methods, that utilize distinguishing sequences in the construction of test segments. The extent of the optimization of the length of a test sequence is investigated with respect to two cases. The first case establishes the lower bound for the length of test sequences generated by any D-method that overlaps test segments. The second case establishes the lower bound for the length of test sequences generated by any D-method that does not overlap test segments. It is observed that the reduction in the length of test sequences due to overlapping is significant. An efficient algorithm for the generation of test sequences is proposed. This algorithm utilizes a distinguishing sequence and overlaps test segments. Sufficiency conditions are given both for finding a minimum- length test sequence in polynomial time and for constructing the optimal length test sequences by this algorithm.> Hasan Ural, Keqin Zhu |
IEEE/ACM Trans. Netw. | 1 |
| 1992 | Formal methods for test sequence generation
Hasan Ural |
Comput. Commun. | 1 |
| 1991 | The Synchronization Problem in Protocol Testing and its Complexity
Sylvia C. Boyd, Hasan Ural |
Inf. Process. Lett. | 2 |
| 1991 | A test sequence selection method for protocol testingabstractA method for automated selection of test sequences from a protocol specification given in Estelle for the purpose of testing both control and data flow aspects of a protocol implementation is discussed. First, a flowgraph modeling the flow of both control and data expressed in the given specification is constructed. In the flowgraph, definitions and uses of each context variable, as well as each input and output interaction parameter employed in the specification, are identified. Based on this information, associations between each output and those inputs that influence the output are established. Test sequences are selected to cover each such association at least once. The resulting test sequences are shown to provide the capability of checking whether a protocol implementation under test establishes the desired flow of both control and data expressed in the protocol specification. The proposed method is illustrated by using the class 0 transport protocol as an example.> Hasan Ural |
IEEE Trans. Commun. | 1 |
| 1991 | On the Complexity of Generating Optimal Test SequencesabstractThe authors investigate whether maximal overlapping of protocol test subsequences can be achieved in polynomial time. They review the concepts related to FSM (finite state machine)-based test sequence generation and then define the optimal test sequence generation (OTSG) problem. It is proved that the OTSG problem is NP-complete. Therefore an efficient solution to the problem should not be expected in the general case.> Sylvia C. Boyd, Hasan Ural |
IEEE Trans. Software Eng. | 2 |
| 1990 | Protocol Conformance Test Generation Using Multiple UIO Sequences With OverlappingabstractThis paper describes an optimization method for reducing the length of protocol conformance test sequences by overlapping test subsequences obtained using UIO sequences. It is shown that test sequences generated by this method are substantially shorter than those generated by other methods employing UIO sequences. Hasan Ural |
SIGCOMM | 2 |
| 1990 | Specifications of distributed systems in prolog
Hasan Ural |
J. Syst. Softw. | 1 |
| 1989 | Formalization of ISDN LAPD for Conformance TestingabstractUsefulness of a formalization of the specification of ISDN LAPD is demonstrated for designing and developing a comprehensive set of conformance tests. Since many protocol standards are specified in a natural language (i.e., English), a method for formalizing protocol specifications with a view to a number of validation activities, including conformance testing, is also presented. In particular, it is shown how to utilize the state-transition-oriented approach to automatically generate a major component of standard conformance test suites. The use of formalized specifications is also illustrated for verifying the specification by selective executions, and for validating conformance test cases against the specification.> Teddy Boyce, T. Grenier, Robert L. Probert, Hasan Ural |
INFOCOM | 4 |
| 1989 | A Comprehensive Software Environment for Developing Standardized Conformance Test Suites
Robert L. Probert, Hasan Ural, Marc W. A. Hornbeek |
Comput. Networks ISDN Syst. | 2 |
| 1989 | ASNST: an Abstract Syntax Notation-One support tool
Cheryl Cleghorn, Hasan Ural |
Comput. Commun. | 2 |
| 1988 | A Structural Test Selection Criterion
Hasan Ural |
Inf. Process. Lett. | 1 |
| 1987 | Test sequence selection based on static data flow analysis
Hasan Ural |
Comput. Commun. | 1 |
| 1986 | An interactive test sequence generator
Hasan Ural, R. Short |
SIGCOMM | 1 |
| 1986 | Step-Wise Validation of Communication Protocols and Services
Hasan Ural, Robert L. Probert |
Comput. Networks | 1 |
| 1984 | High-level testing and example-directed development of software specifications
Robert L. Probert, Hasan Ural |
J. Syst. Softw. | 2 |