We introduce a method of partitioning for massively-parallel hardware accelerated functional verification. Our approach augments classical hypergraph partitioning to model temporal dependencies that maximize parallelization within the instruction memories of the machine. Simulation depth is further reduced by optimizing path criticality and cut directionality. Our techniques are demonstrated on an industrial accelerator containing 262,144 parallel processors, and benchmarked across designs containing up to 200 million gates.

Design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. In this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and CAD challenges in 45nm, what CAD challenges still exist and how the CAD community can help.

As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, have proven to be the critical part of a successful timing closure optimization tool.

Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a circuit for optimization, the circuit has to be electrically clean - i.e., slews on each pin have to be within certain limits, a gate cannot drive more than a certain amount of capacitance, etc. Thus far, this requirement has largely been ignored in the literature. Instead, existing methods which optimize delay are used to fix electrical violations. This leads to solutions that are unnecessarily expensive, and still leave violations that remain unfixed. There is therefore a need for an area-efficient strategy that targets the electrical state of a circuit and fixes all violations quickly. This paper explicitly defines "electrical violations" and presents a flexible approach (called EVE, the electrical violation eliminator) for fixing these. Experimental results validate our approach.

Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfortunately, those changes usually lead to wirelength increases; thus another pass of optimizations to further improve wirelength, timing and routing congestion characteristics is required. Simple wirelength-driven detailed placement techniques could be useful in this scenario. While such techniques can help to reduce wirelength, ones without careful timing constraint considerations might degrade the timing characteristics (worst negative slack, total negative slack, etc) and/or introduce more electrical violations (exceeding maximum output load constraints and maximum input slew constraints). In this paper, we propose a new detailed placement paradigm, which use a set of pin-based timing and electrical constraints in detailed placement to prevent it from degrading timing or violating electrical constraints while reducing wire-length, thus dubbed as Hippocrates: FIRST-DO-NO-HARM optimizations. Our experimental results show great promises. By honoring these constraints, our detailed placement technique not only reduces total wirelength (TWL), but also significantly improves timing, achieving 37% better total negative slack (TNS).

This paper describes a simple and effective quadratic placement algorithm called RQL. We show that a good quadratic placement, followed by local wirelength-driven spreading can produce excellent results on large-scale industrial ASIC designs. As opposed to the current top performing academic placers [4, 7, 11], RQL does not embed a linearization technique within the solver. Instead, it only requires a simpler, pure quadratic objective function in the spirit of [8, 10, 23]. Experimental results show that RQL outperforms all available academic placers on the ISPD-2005 placement contest benchmarks. In particular, RQL obtains an average wire-length improvement of 2.8%, 3.2%, 5.4%, 8.5%, and 14.6% versus mPL6 [5], NTUPlace3 [7], Kraftwerk [20], APlace2.0 [11], and Capo10.2 [18], respectively. In addition, RQL is three, seven, and ten times faster than mpL6, Capo10.2, and APlace2.0, respectively. On the ISPD-2006 placement contest benchmarks, on average, RQL obtains the best scaled wirelength among all available academic placers.

Physical synthesis, the integration of logic synthesis with physical design information, was born in the mid to late 1990s, which means it is about to enter its teenage years. Today, physical synthesis tools are a major part of the EDA industry, accounting for hundreds of millions of dollars in revenue. This work looks at how technology and design trends have affected physical synthesis over the last decade and also how physical synthesis will continue to evolve on its way to adulthood.

The traditional purpose of physical synthesis is to perform timing closure , i.e., to create a placed design that meets its timing specifications while also satisfying electrical, routability, and signal integrity constraints. In modern design flows, physical synthesis tools hardly ever achieve this goal in their first iteration. The design team must iterate by studying the output of the physical synthesis run, then potentially massage the input, e.g., by changing the floorplan, timing assertions, pin locations, logic structures, etc., in order to hopefully achieve a better solution for the next iteration. The complexity of physical synthesis means that systems can take days to run on designs with multimillions of placeable objects, which severely hurts design productivity. This paper discusses some newer techniques that have been deployed within IBM's physical synthesis tool called PDS that significantly improves throughput. In particular, we focus on some of the biggest contributors to runtime, placement, legalization, buffering, and electric correction, and present techniques that generate significant turnaround time improvements

Placement migration is the movement of cells within an existing placement to address a variety of postplacement design-closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To fix a design problem, one would like to perturb the design as little as possible while preserving the integrity of the original placement. This paper presents a new diffusion-based placement method based on a discrete approximation to the closed-form solution of the continuous diffusion equation. It has the advantage of smooth spreading, which helps preserve neighborhood characteristics of the original placement. Applying this technique to placement legalization demonstrates significant improvements in wire length and timing compared with other commonly used techniques.

Placement is a critical component of today's physical-synthesis flow with tremendous impact on the final performance of very large scale integration (VLSI) designs. Unfortunately, it accounts for a significant portion of the overall physical-synthesis runtime. With the complexity and the netlist size of today's VLSI design growing rapidly, clustering for placement can provide an attractive solution to manage affordable placement runtimes. However, such clustering has to be carefully devised to avoid any adverse impact on the final placement solution quality. This paper presents how to apply clustering and unclustering strategies to an analytic top-down placer to achieve large speedups without sacrificing (and sometimes even enhancing) the solution quality. The authors' new bottom-up clustering technique, called the best choice (BC), operates directly on a circuit hypergraph and repeatedly clusters the globally best pair of objects. Clustering score manipulation using a priority-queue (PQ) data structure enables identification of the best pair of objects whenever clustering is performed. To improve the runtime of PQ-based BC clustering, the authors proposed a lazy-update technique for faster updates of the clustering score with almost no loss of the solution quality. A number of effective methods for clustering score calculation, balancing cluster sizes, handling of fixed blocks, and area-based unclustering strategy are discussed. The effectiveness of the resulting hierarchical analytic placement algorithm is tested on several large-scale industrial benchmarks with mixed-size fixed blocks. Experimental results are promising. Compared to the flat analytic placement runs, the hierarchical mode is 2.1 times faster, on the average, with a 1.4% wire-length improvement.

Placement migration is the movement of cells within an existing placement to address a variety of post-placement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To fix a design problem, one would like to perturb the design as little as possible while preserving the integrity of the original placement. This work presents a new diffusion-based placement method based on a discrete approximation to a closedform solution of the continuous diffusion equation. It has the advantage of smooth spreading, which helps preserve neighborhood characteristics of the original placement. Applying this technique to placement legalization demonstrates significant improvements in wire length and timing compared to other commonly used techniques.

Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant portion of the over-all physical synthesis runtime. With complexity and netlist size of today's VLSI design growing rapidly, clustering for placement can provide an attractive solution to manage affordable placement runtime. Such clustering, however, has to be carefully devised to avoid any adverse impact on the final placement solution quality. In this paper we present a new bottom-up clustering technique, called best-choice, targeted for large-scale placement problems. Our best-choice clustering technique operates directly on a circuit hypergraph and repeatedly clusters the globally best pair of objects. Clustering score manipulation using a priority-queue data structure enables us to identify the best pair of objects whenever clustering is performed. To improve the runtime of priority-queue-based best-choice clustering, we propose a lazy-update technique for faster updates of clustering score with almost no loss of solution quality. We also discuss a number of effective methods for clustering score calculation, balancing cluster sizes, and handling of fixed blocks. The effectiveness of our best-choice clustering methodology is demonstrated by extensive comparisons against other standard clustering techniques such as Edge-Coarsening [12] and First-Choice [13]. All clustering methods are implemented within an industrial placer CPLACE [1] and tested on several industrial benchmarks in a semi-persistent clustering context.

Without the MCNC and ISPD98 benchmarks, it would arguably not have been possible for the academic community to make consistent advances in physical design over the last decade. While still being used extensively in placement and floorplanning research, those benchmarks can no longer be considered representative of today's (and tomorrow's) physical design challenges. In order to drive physical design research over the next few years, a new benchmark suit is being released in conjunction with the ISPD2005 placement contest. These benchmarks are directly derived from industrial ASIC designs, with circuit sizes ranging from 210 thousand to 2.1 million placeable objects. Unlike the ISPD98 benchmarks, the physical structure of these designs is completely preserved, giving realistic challenging designs for today's placement tools. Hopefully, these benchmarks will help accelerate new physical design research in the placement, floor-planning, and routing.

There are a number of factors that motivate the use of hierarchical physical design approaches for ASIC and mircroprocessor designs. While microprocessor designs have traditionally been done using hierarchy, the trend in ASIC designs is more recent. The growing use of hierarchy presents new challenges to the design automation community. Tools and algorithms that are designed to work well on flat chips certainly can be applied to individual partitions of a hierarchical design. This works well for some tasks, but there are a host of new problems introduced by hierarchy boundaries that are not addressed by such an approach. This talk will focus on some of the new and interesting physical design automation tasks, with an emphasis on the placement and timing closure aspects of the hierarchy problem.

Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or post routing stage, which may be too late. Since placement determines the overall routing congestion, which correlates with the coupling capacitance, which in turn correlates with the crosstalk noise, placement shall be a good level to do early noise mitigation. The only existing work for the crosstalk aware placement (to our best knowledge) is by Lou and Chen (2004), which uses the coupling capacitance map to guide placement. However, crosstalk is determined not only by the coupling capacitance, but also by many other factors, such as the driver resistance of the victim net and the coupling location (near source vs near sink coupling) (Cong et al., 2001). We introduce a concept of noise map which takes those factors into account. Guided by this accurate noise map explicitly, we propose an incremental placement technique to mitigate noise without disturbing the global placement order. Our incremental placement has two key steps, namely noise aware cell inflation and local refinement. Experimental results on industrial circuits show that our approach is able to reduce the number of top noise nets by 25% and improve the timing (300ps on the worst slack), with no wire length penalty or CPU overhead. Our incremental approach is also able to maintain the placement stability.

Over the last five years, the large scale integrated circuit placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by a nontrivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper, we review motivations for benchmarking, especially for commercial electronic design automation, analyze available benchmarks, and point out major pitfalls in benchmarking. Our empirical data offers perhaps the first comprehensive evaluation of several leading large-scale placers on multiple benchmark families. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.

Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by non-trivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper we review motivations for benchmarking, especially for commercial EDA, analyze available benchmarks, and point out major pitfalls in benchmarking. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.

In recent years the role of placement in the Physical Design of large chips has grown dramatically. One factor for this growth is that wire delays are increasing as a percentage of overall cycle time. As a result, placement needs to consider more than just routability of the final design. Placement is now a major contributor to timing closure results. The problem space for placement now covers a broad range of design styles, including ASIC, SOC, and Microprocessor. Each of these introduce unique challenges to placement algorithms. In addition, the ability of the placement algorithms to operate incrementally within a timing closure system is growing in significance. This talk will outline the variety of placement problems that are routinely encountered, describe major algorithmic approaches that are used to solve the problems, and discuss timing closure characteristics of different approaches.

As technology scales, interconnect-centric design flows become imperative for achieving timing closure. Preplanning buffers and wires in the layout is critical for such flows. Both buffers and wires must be considered simultaneously, since wire routes determine buffer requirements and buffer locations constrain the wire routes. In contrast to recently proposed buffer-block planning approaches, our novel design methodology distributes a set of buffer sites throughout the design. This allows one to use a tile graph to abstract the buffer planning problem and simultaneously address wire planning. We present a four-stage heuristic called resource allocation for buffer and interconnect distribution for resource allocation that includes a new, efficient technique for buffer insertion using a length-based constraint. Extensive experiments validate the effectiveness of this approach.

IP blocks and large macro cells are becoming more prevalent in the physical layout of a design, actually causing an increase in the available free space. We observe that top-down placement based on recursive bisection with multilevel partitioning performs poorly on these porous designs since it lacks a global view of the ideal placement. However, the strength of analytic placement methods lies in their ability to ascertain this global view. Consequently, we propose an enhancement to cut-based placement called analytic constraint generation (ACG). ACG utilizes an analytic engine to distribute available free space appropriately by determining balance constraints for each partitioning step. For one-dimensional placements, our experiments illustrate the large gap between analytic engines, traditional cut-based placement, and ACG as a design becomes increasingly sparse. We also show that for real industry designs, ACG significantly improves the performance of cut-based placement, particularly timing perspective, as implemented within a state-of-the-art industrial placer.

IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-down placement based on recursive bisection with multilevel partitioning performs poorly on these porous designs. However, analytic solvers have the ability to find the natural distribution of cells in the layout. Consequently, we propose an enhancement to cut-based placement called Analytic Constraint Generation (ACG). ACG utilizes an analytic engine to set constraints for the multi-level partitioner. We show that for real industry designs, ACG significantly improves the performance of cut-based placement, as implemented within a state-of-the-art industrial placer.

As technology scales, interconnect-centric design flows become imperative for achieving timing closure. Preplanning buffers and wires in the layout is critical for such flows. Both buffers and wires must be considered simultaneously, since wire routes determine buffer requirements and buffer locations constrain the wire routes. In contrast to recently proposed buffer-block planning approaches, our novel design methodology distributes a set of buffer sites throughout the design. This allows one to use a tile graph to abstract the buffer planning problem and simultaneously address wire planning. We present a four-stage heuristic called resource allocation for buffer and interconnect distribution for resource allocation that includes a new, efficient technique for buffer insertion using a length-based constraint. Extensive experiments validate the effectiveness of this approach.

Buffer insertion has become an increasingly critical optimization in high performance design. The problem of finding a delay-optimal buffered Steiner tree has been an active area of research, and excellent solutions exist for most instances. However, current approaches fail to adequately solve a particular class of real-world “difficult” instances which are characterized by a large number of sinks, variations in sink criticalities, and varying polarity requirements. We propose a new Steiner tree construction called C-Tree for these instance types. When combined with van Ginneken style buffer insertion, C-Tree achieves higher quality solutions with fewer resources compared to traditional approaches.

This paper presents a design methodology emphasizing early and quick timing closure for high frequency microprocessor designs. This methodology was used to design a Gigahertz class PowerPC microprocessor with 19 million transistors. Characteristics of “Timing Closure by Design are 1) logic partitioned on timing boundaries, 2) predictable control structures (PLAs), 3) static interfaces for dynamic circuits, 4) low skew clock distribution, 5) deterministic method of macro placement, 6) simplified timing analysis, and 7) refinement method of chip integration with early timing analysis.

Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algorithms that minimize a global cost function based on an abstract representation of the design, we decomposed the placement function into a set of transforms and coupled them directly with incremental timing, noise, and/or power analyzers. This coupling results in a direct and more accurate feedback on optimizations for placement actions. These placement transforms are then integrated with traditional logic synthesis transforms leading to a converging set of optimizations based on the concurrent manipulation of boolean, electrical, as well as physical data. Experimental results indicate that the proposed approach creates an efficient converging design flow that eliminates placement and synthesis iteration. It results in timing improvements, and maintains other global placement measures such as wire congestion and wire length. The flexibility of the transformational approach allows us to easily add, extend and support more sophisticated algorithms that involve critical as well as non-critical regions and target a variety of metrics including noise, yield and manufacturability:.

This paper describes an approach for tight integration between a synthesis and a placement tool. The purpose of this integration is to improve timing convergence of advanced microprocessors. It is shown that this approach results in "legal" placements with, in general, lower delay, and design size. More significantly, the number of iterations to reach a timing closure is reduced drastically. The wire length estimates that are being used to traditionally drive the timing optimization in synthesis are inadequate. Instead, the integrated approach leads to enhanced results as well as faster timing convergence. The impact of various parameters in synthesis and placement on the final results is shown.

An overview is given of the chip design methodology of the IBM Austin, Texas Advanced Workstation Division. The primary components of this methodology are a high-level language (DSL); a common database (CDB); synthesis, simulation, and floor planning tools; and custom-built circuit elements. The methodology and tools support a top-down design that begins with a high-level logic specification. The hierarchical nature of the methodology permeates all aspects of the design environment, beginning with logic entry, proceeding through physical implementation, and terminating with checking. New additions to the methodology include a high-level language, a synthesis tool, a hardware simulator, a third metal layer for better IO handling, a new min-cut placement program, and an RC estimator/calculator.>