High test coverage is critical to manufacturing a competitive integrated circuit. Design-for-test infrastructure, however, increases the power-performance-area of a chip. This research describes an approach to reduce scan test overhead based on circuit topology heuristics. The heuristics are applied on full-scan designs to convert a subset of the scan flip-flops to D flip-flops, and then evaluated on robust K longest path per gate (KLPG) test patterns. These patterns are modified with multicycle path extension, to minimize test coverage loss even with high scan cell conversion rates. The results are demonstrated using the ISCAS89 and ITC99 benchmark circuits.

The minimum voltage of operation (Vmin) for memory arrays often limits the lowest system operating voltage. This paper introduces a novel read assist topology for a domino-based evaluation architecture in a read only memory (ROM). The implementation incorporates an assist pull-down (PD) device, which activates during the evaluation phase in order to increase the effective pull-down strength of the bit cells. This implementation maintains Vmin without increasing the size of pull down devices inside the bit cells. The assist topology improves read delay by 11-30% and increases noise margin. Area overhead can be limited to 27% in a typical ROM.

Differences in power supply noise (PSN) between functional and structural delay testing can lead to differences in chip operating frequencies of 30% or more. High delay correlation between structural and functional test requires the paths under test to experience the worst-case realistic PSN. We present a PSN control method for pseudo functional test that combines random flipping and background patterns to efficiently fill don't care bits. Dynamic bit weighting permits intelligent selection of background patterns. Experimental results on benchmark circuits achieve worst-case realistic PSN in significantly less CPU time than prior techniques.

Pseudo functional K Longest Path Per Gate (KLPG) test (PKLPG) is proposed to generate delay tests that test the longest paths while having power supply noise similar to that seen during normal functional operation. Our experimental results show that PKLPG is more vulnerable to under-testing than traditional two-cycle transition fault test. In this work, a simulation-based X'Filling method, Bit-Flip, is proposed to maximize the power supply noise during PKLPG test. Given a set of partially-specified scan patterns, random filling is done and then an iterative procedure is invoked to flip some of the filled bits, to increase the effective weighted switching activity (WSA). Experimental results on both compacted and uncompacted test patterns are presented. The results demonstrate that our method can significantly increase effective WSA while limiting the fill rate.

In this paper, we present a timing-driven test generator to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.

Power supply noise is very important in delay testing. Excessive noise can cause circuit delay increases that lead to test overkill. Test patterns that are too quiet can lead to test escapes. In this work, we introduce a realistic low cost delay test compaction flow that guardbands circuit delay during test using a sequence of estimation metrics. Significant reductions in CPU time are demonstrated over prior work.

This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs.

Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.

Testing longer paths in an integrated circuit with a proper path selection strategy has the potential to increase the quality of a delay test. However, the benefit on silicon is not completely clear because a theoretical test quality increase is normally simulated using an assumed distribution of defect sizes. In this work, silicon data is collected and maximum operating frequency (Fmax) compared using test patterns generated by a variety of delay test methodologies. The silicon data is consistent with theoretical predictions and the benefits of testing delay faults through the longest path are quantified.

Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied

Leakage current or the I/sub DDQ/ test has been shown to be an effective test screen in combination with traditional test methods. However, leakage current is rising rapidly as semiconductor technology advances. This makes it difficult to distinguish between faulty and fault-free chips using traditional threshold setting methods. This paper presents a method to estimate leakage current using neighboring chip information on a wafer. Outlier chips are rejected, and a least-squares-fit plane through neighboring chips is used to estimate defect-free I/sub DDQ/. Chips that significantly deviate from the estimate are rejected. The proposed method is evaluated using industrial test data.

Excessive power supply noise can lead to overkill during delay test. A static test vector compaction solution is described to prevent such overkill. Low-cost power supply noise models are developed and used in compaction. An error analysis of these models is given. This paper improves on prior work in terms of models and algorithm to increase accuracy and performance. Experimental results are given on ISCAS89 circuits

A practical built-in current sensor (BICS) is described that senses the voltage drop on supply lines caused by quiescent current leakage. This noninvasive procedure avoids any performance degradation. The sensor performs analog-to-digital conversion of the input signal using a stochastic process, with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. The measurement results of a 350 nm test chip are described. The sensor achieves a resolution of 182 /spl mu/A, with the promise of much higher resolution.

This paper describes algorithms for creation and maintenance of a spanning tree connecting nodes to the central observer (root) in wireless sensor networks. The tree is dynamically reconfigured to route around failed nodes, while minimizing energy consumption. Reconfiguration uses only local information, so that the algorithm scales to large sensor networks. The performance of the algorithm is compared to the single path with repair routing scheme.

Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different power grid environments are presented.

Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To detect delay faults due to local defects and process variation, it is necessary to test all longest paths through each net. Previous approaches to this problem were inefficient because of the large number of paths that are not longest. This paper presents an efficient method to generate the set of longest paths for delay test under process variation. To capture both structural and process correlation between path delays, we use linear delay functions to express path delays under process variation. A novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths. In experiments on International Symposium on Circuits and Systems (ISCAS) circuits, our number of longest paths is 1-6% of the previous best approach, with 300/spl times/ less running time.

To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are inefficient in automatically identifying the longest testable paths due to the high computational complexity. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on ISCAS89 benchmark circuits and industrial designs. Experiments show that testing transition faults through the longest paths can be done in reasonable test set size.

The path delay fault model is the most realistic model for delay faults. Testing all the paths in a circuit achieves 100% delay fault coverage according to traditional path delay fault coverage metrics. These metrics result in unrealistically low fault coverage if only a subset of paths is tested, and the real test quality is not reflected. For example, the traditional path delay fault coverage of any practical test for circuit c6288 is close to 0 because this circuit has an exponential number of paths. In this paper, a statistical and realistic path delay fault coverage metric is presented. Then the quality of several existing test sets (path selection methods) is evaluated in terms of local and global delay faults using this metric, in comparison with the transition fault and traditional path delay fault coverage metrics.

I/sub DDQ/ test-based outlier rejection becomes difficult for deep sub-micron technology chips due to increased leakage and process variations. The use of neighbor current ratio (NCR) that uses wafer-level spatial correlation for identifying outlier chips has been proposed earlier as a means of coping with these issues. Due to the slow speed of I/sub DDQ/ test, there is a strong motivation to reduce the number of test vectors without compromising the fault coverage. In this paper, we examine the effectiveness of neighbor current ratio using a reduced I/sub DDQ/ vector set and industrial test data.

Supply current measurement-based test is a valuable defect-based test method for semiconductor chips. Both static leakage current (IDDQ) and transient current (IDDT) based tests have the capability of detecting unique defects that improve the fault detection capacity of a test suite. Collectively these test methods are known as IDDXtests. However, due to advances in the semiconductor manufacturing process, the future of these test methods is uncertain. This paper presents a survey of the research reported in the literature to extend the use of IDDXtests to deep sub-micron (DSM) technologies.

Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288. 1.

Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.

With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for I/sub DDQ/ test due to increased spread in the distribution. In this paper, the concept of current ratio is extended to exploit wafer-level spatial correlation. Two metrics - current ratio and neighbor current ratio - are combined to screen outliers at the wafer level. We demonstrate that a single metric alone cannot screen all outliers, however, their combination can be used for effectively screening outlier chips. Analyses based on industrial test data are presented.

Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

CMOS chips having high leakage are observed to have high burn-in fallout rate. I/sub DDQ/ testing has been considered as an alternative to burn-in. However, increased subthreshold leakage current in deep submicron technologies limits the use of I/sub DDQ/ testing in its present form. In this work, a statistical outlier rejection technique known as the median of absolute deviations (MAD) is evaluated as a means to screen early failures using I/sub DDQ/ data. MAD is compared with delta I/sub DDQ/ and current signature methods. The results of the analysis of the SEMATECH data are presented.

Abstract — Traditional state-traversal-based methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification problem can be transformed into an easier combinational verification problem. In this paper, we propose an approach that combines two complementary simulation-based methods for fast and accurate storage correspondence. Experiments on the large ISCAS89 benchmark circuits demonstrate the superiority. I.

This paper describes a new built-in current sensor (BICS) design, comprised of a MAGFET current sensor, stochastic sensor, self-calibration tool, counter, and scan chain. By indirectly measuring the current, the sensor avoids the unacceptable drawbacks of past BICS designs. Test chips fabricated in 180 nm and 250 nm technology demonstrate that the sensor can be used for IDDQ testing of large, high-performance, deep submicron circuits. This sensor should extend practical IDDQ testing to the 35 nm technology generation.

This paper proposes a new methodology for estimating the upper bound on the I/sub DDQ/ of defect free chips by using wafer level spatial information. This can be used for I/sub DDQ/ pass/fail limit setting. This methodology is validated using SEMATECH data. Such a methodology accounts for the change in I/sub DDQ/ due to process variations across wafers and reduces false rejects resulting in yield loss. Typical scenarios in using this approach are discussed. The results are compared with traditional methods.

Test pattern generation and diagnosis algorithms that target realistic bridging faults must be provided with a realistic fault list. In this work we describe FedEx, a bridging fault extractor that extracts a circuit from the mask layout, identifies the two-node bridges that can occur, their locations, layers, and relative probability of occurrence. Our experimental results show that FedEx is memory efficient and fast.

Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a Streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.

Capacitive coupling between interconnects can lead to pattern-dependent delay variation. Statistical process fluctuations result in variation in gate and interconnect delays, and interconnect coupling. These effects become increasingly important in deep submicron circuits. In this work we describe a statistical timing analyzer for combinational circuits that takes these effects into account. The tool searches for input vectors that sensitize the longest path and maximizes the delay on these paths due to capacitive coupling. The best and worst-case timing on the paths is then computed using random gate delay variation and spatially-correlated interconnect parasitic variation. We demonstrate timing analysis results on a subset of the ISCAS85 circuits.

Bridging faults in CMOS circuits are usually modeled as a wired-OR, wired-AND, or small fixed resistance. Real bridging faults have a resistance distribution ranging from very small to quite large. The parametric model has been proposed to handle this resistance distribution, along with table-oriented approaches that are accurate and fast. Fault simulators and a test generator have been developed using these models. Prior approaches were too slow to simulate or generate large test sets, handle large circuits, or analyze a wide variety of different test sets. We have developed PROBE, A PSEUDO-PPSFP simulator for resistive bridging faults that is significantly faster while maintaining circuit-level accuracy. We have used PROBE to analyze several large test sets on the ISCAS85 circuits in an effort to gain insight into how existing test generation approaches detect resistive bridges.

This paper presents a quiescent current-based (I/sub DDQ/) approach for testing input/output resources in SRAR-based FPGAs. Input/output resources include input/output blocks (IOBs) and the I/O interconnect. Test generation and application strategies are proposed by taking into account the limited controllability of the I/O resources. Configuration of these resources requires that the test stimuli must be provided by internal (logic and routing) resources. A detailed presentation for testing the I/O resources of the Xilinx XC4000 family is given.

In this work/sup 1/ we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the first resistive bridging fault ATPG, which attempts to detect the maximum possible bridging resistance at each fault site. We compare the results of the ATPG to the coverage obtained from other test sets, and coverage obtained by using the ATPG in a clean-up mode. Results on ISCAS85 circuits show that stuck-at test sets do quite well, but that the ATPG can still improve the coverage. We have also found that the loss of fault coverage is predominantly due to undetected faults, rather than faults in which only a small resistance is detected. This suggests that lower-cost fault models can be used to obtain high resistive bridge fault coverage.

Introduction Most IC design engineers today are at the same stage when considering Design for Yield (DFY) and Design for Reliability (DFR) as they were when considering Design for Test (DFT) 20 years ago. Most engineers poorly understand them, there are few EDA tools to help them, and there is no consensus about whether it is even worthwhile. It is just one more Design for X that they don’t have time to worry about. However this is not quite right. In fact DFY and DFR rules long preceded DFT rules, in the form of layout and electrical design rules. However most design engineers treated them as sort of like the laws of physics, something to be obeyed or fact the wrath of the manufacturing engineers. Clearly in the past DFY and DFR were more important than DFT. This is still true today, and more DFY and DFR activity must move earlier in the design process, rather than remain mostly a last-minute physical design check.

This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process or due to specification changes. We incrementally use simulation to identify suspect nets, and then attempt correction based on our error model. We use multiple iterations to handle multiple errors. Experimental results on ISCAS'85 benchmarks are shown for circuits containing up to four random errors. Diagnosis and correction can be done quickly, with the bulk of the time going to diagnosis. Our tool is accurate in that even with multiple errors present, the corrected circuit is identical to the original most of the time.

This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.

This paper presents an I/sub DDQ/-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100% coverage of I/sub DDQ/-testable bridging faults. Since reconfiguration programming time can dominate total test time, even with slow I/sub DDQ/ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first, and then to minimize the number of test vectors. 100% coverage for I/sub DDQ/-testable bridging faults is achieved in 5 programming phases and 16 I/sub DDQ/ vectors in the Xilinx XC4000 FPGA family. The RAM modes are tested in a further phase, using 48 test vectors and 38 I/sub DDQ/ measurements.

This paper presents an I/sub DDQ/-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The proposed approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100 percent coverage of I/sub DDQ/ testable bridging faults. We use a hierarchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables), Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow I/sub DDQ/ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for I/sub DDQ/-testable bridging faults is achieved in five programming phases and 16 I/sub DDQ/ vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 I/sub DDQ/ measurements.

Bridging faults in CMOS circuits sometimes degrade the output voltage and time performance without altering the logic function. The traditional voltage testing models based on the normal power supply voltage do not accurately model this behavior. In this paper we develop a model of bridging faults that accounts for both the bridging resistance distribution and gate sensitization and propagation choices. This model shows that fault coverage increases at lower power supply voltages. It suggests that decreasing the power supply voltage is a promising technique to maximize the real fault coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.

This paper describes test generation for delay faults caused by global process disturbances. The correlations between path delays is used to reduce the number of paths that must be tested. We build macro models of path delays as a function of process parameters to reduce test generation time. The test generation problem is formulated as a nonlinear optimization using a set of candidate paths supplied by a path generator. Results are given for the ISCAS85 benchmarks.

This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache.

In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus an two fault types: resistive bridges between gate outputs that cause pattern sensitive functional faults and opens in transmission gates that cause delay faults. In both cases, the traditional stuck at model is inadequate. The test vector to sensitize and propagate a resistive bridging fault is not unique. The traditional greedy test vector selection is optimistic, with some choices having poor real coverage. We realistically model the fault and fault coverage, and describe an optimal selection strategy. In a transmission gate with an open NMOS or PMOS device, the output voltage is degraded, increasing delay and reducing noise margin. We model this fault and show how low-voltage testing can be used to detect it. Our goal in applying these techniques to all important fault types is to maximize the real coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.

This paper presents a methodology to estimate the defect Pareto in an IC process through the use of production functional test data. This Pareto can then be used for yield improvement activities. We demonstrate the concept on several benchmark circuits. We show how limited IDDQ current testing can significantly improve the Pareto accuracy.

This paper presents a methodology for predicting the electrical performance of integrated circuits prior to packaging and final test. A simulation-based approach is used to build response surface prediction models. The work focuses on determining the optimal set of test measurements required for on-line product-based control, package selection, binning and die selection for MCMs.

This work describes the Semiconductor Wafer Representation (SWR) for representing and manipulating wafer state during process and device simulation. The goal of the SWR is to provide an object-oriented interface to a collection of functions designed for developing and integrating Technology CAD (TCAD) applications. By providing functions which can be common across many applications, we aim to greatly reduce tool development and integration time. Corporate, vendor, and university TCAD developers have worked together under the auspices of the CAD Framework Initiative to create an architecture and C++ programming interface for an SWR 1.0 draft standard. Here we describe this architecture and the results of creating and using a prototype implementation of the standard both to integrate existing TCAD tools and to develop simple new tools.>

This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects in the manufacturing process on a design, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the simulation effort needed. It also reports hierarchical faults that can be fed into a hierarchical fault simulator. Yield analysis results are given for designs of up to 164K transistors. Test quality analysis results are given for an adder module.

Estimating the reject ratio for integrated circuits is an important problem to a test engineer. Using information about the decrease in reject ratio with increasing test length, the test engineer can estimate the test length necessary to achieve a desired product quality goal. This paper suggests a method for estimation of reject ratio for random testing of combinatorial circuits that takes into account differing individual fault probabilities. The authors also suggest some ways of estimating the fault probabilities. They then demonstrate the method on an example and compare results to previous work.>

The chip database (CDB) and the hierarchical chip database (HCDB) and their uses in a wafer representation server are described. The server provides data types and methods for hierarchically representing the three-dimensional geometry and fields of a semiconductor wafer during process, device, and yield simulation. The basic database data types and the general attribute mechanism have been used to create database extensions. These extensions implement operations frequently used by process and device simulation models. The combination of the databases and extensions forms a CDB/HCDG server that greatly reduces the effort required to create new statistical process, device, and yield simulation models. Examples of using the server to implement new models are described. Performance data demonstrate that the server is fast enough for use by analytical models during statistical simulation of macrocells, and is able to meet the representation needs of numerical simulation.>

geometry and field Database (CDB), for representing the results of IC process and device simulation, and its use in the PREDITOR process editor and statistical simulator.Using fast analytical models, process simulation and device parameter extraction for a CMOS inverter takes 1.3sec on a DECstation 3100, with database access taking 14-34% of that time.

Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic-fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a simulation. In order to reduce the simulation time, DVLASIC, the distributed-environment version developed by the authors, achieves a speedup of 13.3 over VLASIC, with an efficiency of 89%. The authors describe the distributed processing environment and implementation techniques used to obtain this speedup. The distributed processing environment can also be applied to many other CAD problems.>

This paper describes the yield simulator VLASIC (VLSI Layout Simulation for Integrated Circuits). VLASIC is a Monte Carlo simulator that uses defect models and statistics to place random catastrophic point defects on a chip layout and determine what circuit faults, if any, have occurred. The defect models are described in tables, and so are readily extended to new processes or defect types. The defect statistical model is based on actual fabrication line data, and has not appeared before in the literature. The circuit fault information generated by VLASIC can be used to predict yield, optimize design rules, generate test vectors, evaluate redundancy, etc. A redundancy analysis system which uses these data is described, and an example of its use given.