OBJECTIVE: Electrocardiogram (ECG) signals commonly suffer noise interference, such as baseline wander. High-quality and high-fidelity reconstruction of the ECG signals is of great significance to diagnosing cardiovascular diseases. Therefore, this paper proposes a novel ECG baseline wander and noise removal technology. METHODS: We extended the diffusion model in a conditional manner that was specific to the ECG signals, namely the Deep Score-Based Diffusion model for Electrocardiogram baseline wander and noise removal (DeScoD-ECG). Moreover, we deployed a multi-shots averaging strategy that improved signal reconstructions. We conducted the experiments on the QT Database and the MIT-BIH Noise Stress Test Database to verify the feasibility of the proposed method. Baseline methods are adopted for comparison, including traditional digital filter-based and deep learning-based methods. RESULTS: The quantities evaluation results show that the proposed method obtained outstanding performance on four distance-based similarity metrics with at least 20% overall improvement compared with the best baseline method. CONCLUSION: This paper demonstrates the state-of-the-art performance of the DeScoD-ECG for ECG baseline wander and noise removal, which has better approximations of the true data distribution and higher stability under extreme noise corruptions. SIGNIFICANCE: This study is one of the first to extend the conditional diffusion-based generative model for ECG noise removal, and the DeScoD-ECG has the potential to be widely used in biomedical applications.

Side-channel attacks (SCA) have been studied for several decades, which resulted in many techniques that use statistical models to extract system information from side channels. More recently, machine learning has shown significant promise to advance the ability for SCAs to expose vulnerabilities. Artificial neural networks (ANN) can effectively learn nonlinear relationships between features within a side channel. In this paper, we propose a multi-architecture data aggregation technique to profile power traces for a system with an embedded processor that is based on three types of deep NNs, namely, multi-layer perceptrons (MLP), convolutional neural networks (CNN), and recurrent neural networks (RNN). This is one of the first works to explore the inter-architecture portability of NNs and SCAs. We demonstrate the robustness of the ANNs performing power-based SCAs on multiple architecture configurations with different architectural features, such as L1/L2 caches' size and associativity, and system memory size. We provide a comprehensive set of benchmarks to demonstrate that architecturally identical devices are not essential for profile-based SCAs

Automatic mitosis detection is a key step in measuring cell proliferation and analyzing the responses to various stimuli. Current deep neural networks can learn complex visual features and capture long-range temporal dependencies. However, the state-of-the-art mitosis detection models require massive ground truth annotations which is labor intensive in biomedical experiments. Therefore, we propose a sequence-level supervised neural networks model to detect mitosis events at pixel-and-frame level. By using binary labels, the proposed network is trained to predict the presence of mitosis for the input microscopy sequences. Then we leverage the feature map produced by the proposed network to localize the cell division. The proposed model achieved a detection F1-score 0.881.With significantly less amount of ground truth in the training data, our method achieved competitive performance compared with the state-of-art fully supervised mitosis detection methods.

Counting dead cells is a key step in evaluating the performance of chemotherapy treatment and drug screening. Deep convolutional neural networks (CNNs) can learn complex visual features, but require massive ground truth annotations which is expensive in biomedical experiments. Counting cells, especially dead cells, with very few ground truth annotations remains unexplored. In this paper, we automate dead cell counting using a weakly supervised strategy. We took advantage of the fact that cell death is low before chemotherapy treatment and increases after treatment. Motivated by the contrast, we first design image level supervised only classification neural networks to detect dead cells. Based on the class response map in classification networks, we calculate a Dead Confidence Map (DCM) to specify confidence of each dead cell. Associated with peak clustering, local maximums in the DCM are used to count the number of dead cells. In addition, a biological experiment based weakly supervised data preparation strategy is proposed to minimize human intervention. We show classification performance compared to general purpose and cell classification networks, and report results for the image-level supervised counting task.

This paper presents a methodology for evaluating power obfuscation approaches that seek to obfuscate the location of sensitive operations in the power trace, thereby increasing the complexity of automated trace alignment. The paper presents a new adversary model and proposes a new metric, mean trials to success (MTTS), to evaluate power obfuscation methods in the context of automated trace alignment. We evaluate two common obfuscation methods, namely instruction shuffling and random instruction insertion, and we present a new obfuscation method using power shaping to intentionally mislead the attacker.

With embedded systems and IoT devices being widely deployed nowadays, their security becomes a major concern. Among all possible attacks, side channel attacks (SCA) represent a major source of threats. For power side channels, template attacks have been proven to be efficient and widely applicable. Traditional template attacks require physical access to an identical target device for extensive profiling to construct the attack template. In this paper, we present a composable template attack that relaxes this requirement by constructing the attack template as a composition of templates from individual architectural components, including processor, caches, and memories. The proposed approach enables an attacker to construct a template using only information of a system's components and device models thereof.

Wearable technology and mobile platforms are becoming more and more popular in health care. This paper introduces a real time stress management system using wearable sensors and Smartphone mobile platform. The new system estimates stress level in real time using heart rate variability and patient activity cycles, and provides relaxation exercises instantaneously to help manage stress. The system relies on a wearable sensor to collect data (i.e., heart rate and respiration rate) and transmits data to Smartphones using Bluetooth to further process data. We also introduce a new breathing template matching algorithm to identify the best breathing exercise for users. A 2D visualization display shows that stress can be effectively relieved by the proposed stress management system.

Timing characterization of standard cells is one of the essential steps in VLSI design. The traditional static timing analysis (STA) tool assumes single input switching models for the characterization of multiple input gates. However, due to technology scaling, increasing operating frequency, and process variation, the probability of the occurrence of multiple input switching (MIS) is increasing. On the other hand, considering all possible MIS scenarios for the characterization of multiple input logic gates, is computationally intensive. To improve the efficiency, this work proposes a finite-point-based characterization methodology for multiple input gates with the effects of MIS. Furthermore, delay variation due to MIS is integrated into the STA flow through propagation of switching windows. The proposed modeling methodology is validated using benchmark circuits at the 45nm technology node for various operating conditions. Experimental results demonstrate significant reduction in computation cost and data volume with less than ∼10% error compared to that of traditional SPICE simulation.

This article proposes a novel methodology for robust analog/mixed-signal IC design by introducing a notion of budget of uncertainty. This method employs a new conic uncertainty model to capture process variability and describes variability-affected circuit design as a set-based robust optimization problem. For a prespecified yield requirement, the proposed method conducts uncertainty budgeting by associating performance yield with the size of uncertainty set for process variations. Hence the uncertainty budgeting problem can be further translated into a tractable robust optimization problem. Compared with the existing robust design flow based on ellipsoid model, this method is able to produce more reliable design solutions by allowing varying size of conic uncertainty set at different design points. In addition, the proposed method addresses the limitation that the size of the ellipsoid model is calculated solely relying on the distribution of process parameters, while neglecting the dependence of circuit performance upon these design parameters. The proposed robust design framework has been verified on various analog/mixed-signal circuits to demonstrate its efficiency against the ellipsoid model. Up to 24% reduction of design cost has been achieved by using the uncertainty budgeting-based method.

Wireless sensors are being increasingly used to monitor/collect information in healthcare medical systems. For resource-efficient data acquisition, one major trend today is to utilize compressive sensing, for it unifies traditional data sampling and compression. Despite the increasing popularity, how to effectively process the ever-growing healthcare data and simultaneously protect data privacy, while maintaining low overhead at sensors, remains challenging. To address the problem, we propose a privacy-aware cloud-assisted healthcare monitoring system via compressive sensing, which integrates different domain techniques with following benefits. By design, acquired sensitive data samples never leave sensors in unprotected form. Protected samples are later sent to cloud, for storage, processing, and disseminating reconstructed data to receivers. The system is privacy-assured where cloud sees neither the original samples nor underlying data. It handles well sparse and general data, and data tampered with noise. Theoretical and empirical evaluations demonstrate the system achieves privacy-assurance, efficiency, effectiveness, and resource-savings simultaneously.

With continuously shrinking technology, reliability issues such as Negative Bias Temperature Instability (NBTI) has resulted in considerable degradation of device performance, and eventually the short mean-time-to-failure (MTTF) of the whole multicore system. This article proposes a new workload balancing scheme based on device-level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. Starting with NBTI-induced threshold voltage degradation, we define a concept of Capacity Rate (CR) as an indication of one core's ability to accept workload. Capacity rate captures core's performance variability in terms of delay and power metrics under the impact of NBTI aging. The proposed workload balancing framework employs the capacity rates as workload constraints, applies a Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on a 64-core system show that by allowing a small part of the cores to relax over a short time period, the proposed methodology improves multicore system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).

An FPGA based, single cycle, low latency router design that can be reconfigured to 1-D and 2-D network on chip architectures is proposed. The design is highly scalable and exploits the features provided by any standard FPGA platform and can be easily ported to an ASIC or any other FPGA platform. Due to the highly interconnect-centric nature of NoCs, the built-in resources of an FPGA in terms of routing channels and on chip logic are ideal and provide a well-utilized platform for the router design. Experimental results prove the proposed design is robust and cost effective. Each router consumes a mere 2.08 μW per bit per hop of power in the worst case while achieving high clock rates of 325 MHz easily on the target FPGA device post design synthesis and emulation.

This paper proposes a novel methodology for robust analog/mixed-signal IC design by introducing a notion of budget of uncertainty. This method employs a new conic uncertainty model to capture process variability and describes variability-affected circuit design as a set-based robust optimization problem. For a pre-specified yield requirement, the proposed method conducts uncertainty budgeting by associating performance yield with the size of uncertainty set for process variations. Hence the uncertainty budgeting problem can be further translated into a tractable robust optimization problem. Compared with the existing robust design flow based on ellipsoid model, this method is able to produce more reliable design solutions by allowing varying size of conic uncertainty set at different design points. In addition, the proposed method addresses the limitation that the size of ellipsoid model is calculated solely relying on the distribution of process parameters, while neglecting the dependence of circuit performance upon these design parameters. The proposed robust design framework has been verified on various analog/mixed-signal circuits to demonstrate its efficiency against ellipsoid model. An up to 24% reduction of design cost has been achieved by using the uncertainty budgeting based method.

This article aims to achieve computational reliability and energy efficiency through codevelopment of algorithms, device, and circuit designs for application-specific, reconfigurable architectures. The new methodology characterizes aging-switching activity and aging-supply voltage relationships that are applicable for minimizing power consumption and task execution efficiency in order to achieve low bit energy ratio (BER). In addition, a new dynamic management algorithm (DMA) is proposed to alleviate device degradation and to extend system lifespan. In contrast to traditional workload balancing schemes in which cores are regarded as homogeneous, the new algorithm ranks cores as “highly competitive,” “less competitive,” and “not competitive” according to their various competitiveness. Core competitiveness is evaluated based upon their reliability, temperature, and timing requirements. Consequently, “competitive” cores will take charge of the majority of the tasks at relatively high voltage/frequency without violating power and timing budgets, while “not competitive” cores will have light workloads to ensure their reliability. The new approach combines intrinsic device characteristics (aging-switching activity and aging-supply voltage curves) into an integrated framework to achieve high reliability and low energy level with graceful degradation of system performance. Experimental results show that the proposed method has achieved up to 20% power reduction, with about 4% performance degradation (in terms of accomplished workload and system throughput), compared with traditional workload balancing methods. The new method also improves system mean-time-to-failure (MTTF) by up to 25%.

Energy harvesting is becoming one of the most important issues today due to the fast depletion of conventional energy resources. Current research efforts focus on efficient and reliable use of renewable resources such as solar, hydro, wind, and thermal resources to provide environmentally friendly solutions while minimizing the cost. However, an efficient and effective delivery of green energy to individual households remains a challenging issue. One key roadblock is the high complexity of the smart grid system. In this paper, we propose a new interface theory based energy-timing model for smart homes and smart grid management and design. This model allows simple yet accurate computations for energy supply and consumptions involved with photovoltaic (PV) cells, storage units, and load appliances for each home. At community, and city or state level (or nationwide), this model also has the potential to facilitate fast and effective energy management, optimization, and load scheduling. The end result is the possibility of managing smart grid with millions of households to achieve low cost and high energy savings.

As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process variations cause errors in data delivering through interconnects. This paper proposes an Information Theory based design method to accommodate process variations. Different from the traditional delay based design metric, the current approach uses achievable rate to relate interconnect designs directly to communication applications. More specifically, the data communication over a typical interconnect, a bus, subject to process variations (“uncertain” bus), is defined as a communication problem under uncertainty. A data rate, called the achievable rate, is computed for such a bus, which represents the lower bound on the maximal data rate attainable over the bus. When a data rate applied over the bus is smaller than the achievable data rate, a reliable communication can be guaranteed regardless of process variations, i.e., a bit error rate arbitrarily close to zero is achievable. A single communication strategy to combat the process variations is proposed whose code rate is equal to the computed achievable rate. The simulations show that the variations in the interconnect resistivity could have the most harmful effect regarding the achievable rate reduction. Also, the simulations illustrate the importance of taking into account bus parasitic parameters correlations when measuring the influence of the process variations on the achievable rates.

As device feature sizes continue to shrink, long-term reliability such as Negative Bias Temperature Instability (NBTI) leads to low yields and short mean-time-to-failure (MTTF) in multi-core systems. This paper proposes a new workload balancing scheme based on device level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. The proposed method employs the Capacity Rate (CR) provided by the NBTI model, applies Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on 64-core system show that by allowing a small part of the cores to relax over a short time period (10 seconds), the proposed methodology improves multi-core system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).

This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18% power reduction with about 4% performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.

As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. To accurately consider both global and local process variations, a large number of random variables (or parameters) have to be incorporated into circuit models. This in turn raises the complexity of the circuit models. In this paper, we propose a principle Hessian direction-based parameter-reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In interconnect cases, the proposed method reduces 70% of parameters. In some cases, for example, the mesh circuit in the current paper, the new approach leads to an 85% reduction. We also tested ISCAS benchmarks. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.

The increasing wire delay constraints in deep sub-micron VLSI designs have led to the emergence of scalable and modular network-on-chip (NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose iDEAL - inter-router, dual-function energy and area-efficient links capable of data transmission as well as data storage when required. iDEAL enables a reduction in the router buffer size by controlling the repeaters along the links to adaptively function as link buffers during congestion, thereby achieving nearly 30% savings in overall network power and 35% reduction in area with only a marginal 1 - 3% drop in performance. In addition, aggressive speculative flow control further improves the performance of iDEAL. Moreover, the significant reduction in power consumption and area provides sufficient headroom for monitoring negative bias temperature instability (NBTI) effects in order to improve circuit reliability at reduced feature sizes.

This paper proposes a new model for interconnect communication capacity in the presence of process variations. Different from previous research works, this model, for the first time, reveals the dependency of interconnect communication capacity on its parasitic parameters. A new method based on Uncertainty Ellipsoid Method (UEM) is applied to optimize the interconnect capacity considering random parameters variations. This new approach incorporates both spatial correlations of intra-die width and parameters variations in the optimization procedure. As is well known, process variation introduces perturbations in the transfer function of interconnect networks. The perturbed transfer function in turn causes variations in the Bit Error Rate (BER). Becoming random, the perturbed BER leads to a changing communication capacity. Based on robust communication theory, we propose a new capacity model which is a function of interconnect geometric parameters. With the help of Geometric Programming (GP) procedure, we use the new model to conduct optimization with regard to the design parameters. Experimental results show that the new model provides less than 7:3% mean square error in capacity prediction comparing with Monte-Carlo method. Based on this bit error value, GP technique is applied to determine the optimal solution, which in return guides the fabrication of interconnects.

In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches are not able to handle the uncertain distribution property coming from the process data. Other approaches are inadequate considering correlations among the parameters. This paper suggests a new approach that not only takes care of the correlations among distributions but also provides a low cost and efficient computation scheme. The proposed method approximates the parameter variations with Chebyshev affine arithmetics (CAA) to capture both the uncertainty and the nonlinearity in cumulative distribution functions (CDF). The CAA based probabilistic presentation describes both fully and partially specified process and environmental parameters. Thus we are capable of predicting probability bounds for leakage consumption under unknown dependency assumption among variations. The end result is the chip level parametric yield estimation based on leakage prediction. The experimental results demonstrate that the new approach provides reliable bound estimation while leads to 20% yield improvement comparing with interval analysis.

In nanometer regime, IC designs have to consider the impact of process variations, which is often indicated by manufacturing/parametric yield. This paper investigates a yield model — the probability that the values of multiple manufacturing/circuit parameters meet certain target. This model can be applied to predict CMP (Chemical-Mechanical Planarization) yield. We focus on the difficult cases which have large number of partially correlated variations. In order to predict the yield for these difficult cases efficiently, we propose two techniques: (1) application of Orthogonal Principle Component Analysis (OPCA); (2) hierarchical adaptive quadrisection (HAQ). Systematic variations are also included in our model. Compared to previous work, the OPCA based method can reduce the error on yield estimation from 17.1%–21.1% to 1.3%–2.8% with 4.6× speedup. The HAQ technique can reduce the error to 4.1% – 5.6% with 6 × –9.4× speedup.

Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. This paper proposes a statistical centering-based clock routing algorithm that is built upon deferred merging embedding that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by the following ways: (1) choosing the best center measure which is dynamically based on the first three moments of the skew distribution and (2) designing for all sink pairs in the subtrees simultaneously. In addition, a variation-aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate that the proposed method reduces the number of skew violations by 12%-37%.

Due to the hard-to-measure distributions of real process data, it is difficult to provide accurate parametric yield prediction for modern circuit design. Most existing approaches are not able to handle the uncertain distribution properties coming from the process data. Other approaches are inadequate in considering correlations among the distributions of variations. This paper suggests a new approach that not only takes care of correlations among distributions but also provides a low-cost and efficient computation scheme. The proposed method approximates the parameter variations with Chebyshev affine arithmetic (CAA) to capture both the uncertainty and nonlinearity in a cumulative distribution function. The CAA-based probabilistic range presentation describes, both fully and partially, specified process and environmental parameters. Thus, we are able to predict the probability bounds for leakage consumption with unknown dependences among variations. The end result is the chip-level parametric yield estimation based on leakage prediction. Experimental results demonstrate that the new approach provides a reliable bound estimation, which leads to a 20% yield improvement compared with only using the intervals of partially specified uncertainties.

Due to the nonuniform interconnect scaling in the Deep Sub Micron (DSM) region, the coupling capacitance between wires becomes an increasingly dominant fraction of the total wire capacitance. This couple capacitance introduces server crosstalk which causes delay variations on signal lines and raises signal integrity problems. Therefore, including crosstalk in the timing analysis methods has become imperative for current technologies. And to correctly model the crosstalk, output loading effects, waveform shape and gate driving capability have to be considered. However, most existing crosstalk models have not yet included these factors and consequently suffer from the low accuracy problem. In this article, we propose a noniterative equivalent waveform model that addresses the above mentioned issues. Our experimental results have shown that the new model achieves 3 times speed up and 95% accuracy compared to the existing models.

Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: timing uncertainty reduction by gate-interconnect splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the chemical-mechanical polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to its variation. Improvements of up to 30% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation IC design. One of the biggest challenges is the enormous number of process variation related parameters. These parameters represent numerous local and global variations, and pose a heavy burden in today's chip verification and design. This paper proposes a new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance. The new approach creates an effective reduction subspace (ERS) and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which we process variability analysis. Thus, the computational cost due to the number of variations is greatly reduced. Experimental results show that by using new method we can achieve 20% to 50% parameter reduction with only less than 8% error on average.

This paper proposes a robust gate model based on a finite-point modeling scheme. With current source model (CSM) framework, a robust, finite-point gate model is constructed. The new model depends on the selective points of I-V curves of gates. Thus, it implicitly incorporates the variation related parameters into finite points. In addition, to provide good accuracy on output waveform, the new model creates the input and output capacitance elements as nonlinear dependency on input/output waveform and process variation parameters. Experimental results show that the generated gate model has less than 3.7% error at mean, less than 6.2% error at variance and less than 5.8% at 90% percentile for cumulative density functions (CDFs).

As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessian Direction (PHD) based parameter reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis (PCA) method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.

With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged as one of the efficient way to subside the yield deterioration due to manufacturing variations. In the past single-objective optimization techniques have been used to optimize the timing variation whereas on the other hand multi-objective optimization techniques can provide a more promising approach to design the circuit. We propose a new algorithm called YOGA, based on multi-objective optimization technique called non-dominated sorting genetic algorithm (NSGA). YOGA optimizes a circuit in multi domains and provides the user with Pareto-optimal set of solutions which are distributed all over the optimal design spectrum, giving users the flexibility to choose the best fitting solution for their requirements. YOGA overcomes the disadvantages of traditional optimization techniques, while even providing solutions in very stringent bounds

The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named DMA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, DMA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125% are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency

In this paper, an integrated adaptive output switching converter is proposed. The design uses a one-cycle control for fast line regulation and a single outer loop for load regulation and fine tuning. A switched-capacitor integrator is introduced in the one-cycle control to obtain positive integration with a single positive power supply, allowing a standard low-cost CMOS fabrication process. To improve the efficiency, a dynamic loss control technique is presented. HSPICE simulations are performed with transistor models from TSMC 0.35mum N-well CMOS fabrication process. With a supply voltage of 3 V, a voltage ripple of less than 15 mV is measured. The maximum efficiency is 92% with a load power of 475 mW. The converter exhibits a tracking speed of 2 mus/V for both start-up and reference voltage transitions. The recovery time for a 20% load change is approximately 2.6mus. The overall design exhibits superior system robustness to battery perturbations, noise and process variations

Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high speed, large area clock networks. To achieve multi-GHz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. We propose statistical centering based clock routing algorithm built upon DME that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by: i) choosing the best center measure which is dynamically based on the first three moments of the skew distribution, and ii) designing for all sink pairs in the subtrees simultaneously. In addition, a variation aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate the efficiency of the proposed method in reducing the number of skew violations by 12%-37%.

Variations in the interconnect geometry of nanoscale ICs translate to variations in their performance. The resulting diminished accuracy in the estimates of performance at the design stage can lead to a significant reduction in the parametric yield. Thus, determining an accurate statistical description (e.g., moments, distribution, etc.) of the interconnect's response is critical for designers. In the presence of significant variations, device or interconnect model parameters such as wire resistance, capacitance, etc., need to modeled as random variables or as spatial random processes. The corner-based analysis is not accurate, and simulations based on sampling require long computation times due to the large number of parameters or random variables. This study proposes an efficient method of computing the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by projecting the infinite series representation onto a finite dimensional subspace. The advantage of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called orthogonal polynomial expansions for response analysis (OPERA). Results from OPERA simulations on a number of design test cases match well with those from the classical Monte Carlo simulation program with integrated circuits emphasis (SPICE) and from perturbation methods. Additionally, OPERA shows good computational efficiency: speedup of up to two orders of magnitude have been observed over Monte Carlo SPICE simulations.

Feature sizes of less than 90 nm and clock frequencies higher than 3 GHz calls for fundamental changes in driver-load models. New driver-load models must consider the process variation impact of the manufacturing procedure, the nonlinear behavior of the drivers, the inductance effects of the loads, and the slew rates of the output waveforms. The present deterministic driver-load models use the conventional deterministic driver-delay model with a single$C_ eff$(one ramp) approach. Neither the statistical property of the driver nor the inductance effects of the interconnect are taken into consideration. Therefore, the accuracy of existing models is questionable. This paper introduces a new driver-load model that predicts the driver-delay changes in the presence of process variations and represents the interconnect load as a distributed resistance, inductance and capacitance (RLC) network. The employed orthogonal polynomial-based probabilistic collocation method (PCM) constructs a driver-delay analytical equation from the circuit's output response. The obtained analytical equation is used to evaluate the driver output delay distribution. In addition, the load is modeled as a two-effective-capacitance in order to capture the nonlinear behavior of the driver. The lossy transmission line approach accounts for the impact of the inductance when modeling the driving-point interconnect load. The new model shows improvements of 9% in the average delay error and 2.2% in the slew rate error over the simulation program with integrated circuit emphasis (SPICE) and the one ramp modeling approaches. Compared with the Monte Carlo method, the proposed model demonstrates a less than 3% error in the expected gate delay value and a less 5% error in the gate delay variance.

It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45%. improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.

We present a practical flow that automates the process of analyzing noise failures and determining and implementing the most appropriate design fixes in high performance designs. For each noise problem, the flow implicitly identifies the most sensitive relevant electrical parameter(s) which it then maps to a physical solution that minimizes design perturbation. Integrated with standard physical synthesis, it was used extensively in a high volume 90 nm multi-GHz microprocessor project.

In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid's electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an explicit analytical representation of the stochastic voltage response using orthogonal polynomials in a Hilbert space. The approach has been implemented in a prototype software called OPERA (Orthogonal Polynomial Expansions for Response Analysis). Use of OPERA on industrial power grids demonstrated speed-ups of up to two orders of magnitude. The results also show a significant variation of about /spl plusmn/35% in the nominal voltage drops at various nodes of the power grids and demonstrate the need for variation-aware power grid analysis.

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses an orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.

New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.

Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100/spl times/ speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.

This paper proposes a new statistical response surface based power estimation technique. The new approach is able to include a number of parameters such as multiple Vdd, multiple Vth and gate sizing parameters. It has both deterministic ability and statistical ability. The deterministic ability allows the new model to provide optimal design parameters for power reduction. The statistical ability can be used to model the process variation impact on power.

This paper presents an integrated power system for low-power wireless sensor networks with dynamic efficiency optimization technique. By adaptively resizing power transistors and adjusting switching frequency, system efficiency is enhanced significantly. Theoretical analysis is elaborated to support the proposed technique. A prototype integrated power system for self-powered photovoltaic wireless sensing node was designed and simulated with TSMC 0.35μm CMOS process. With a power range of 0.5μW to 10mW, power efficiency stays above 71%. Tolerance between theoretical and simulated optimal power transistor sizes is less than 6.7%, while that of optimal switching frequencies is less than 5%. The paper gives another solution to minimizing system power in the perspective of power processing

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.

The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing uncertainty in the performance of CMOS circuits. Accounting for the worst case values of all parameters will result in an unacceptably low timing yield. Design for Variability, which involves designing to achieve a given level of confidence in the performance of ICs, is fast becoming an indispensable part of IC design methodology. This paper 1 describes a method to identify certain paths in the circuit that are responsible for the spread of timing performance. The method is based on defining a disutility function of the gate and path delays, which includes both the means and variances of the delay random variables. Based on the moments of this disutility function, an algorithm is presented which selects a subset of paths (called undominated paths) as being most responsible for the variation in timing performance. Next, a statistical gate sizing algorithm is presented, which is aimed at minimizing the delay variability of the nodes in the selected paths subject to constraints on the critical path delay and the area penalty. Monte-Carlo simulations with ISCAS ’85 benchmark circuits show that our statistical optimization approach results in significant improvements in timing yield over traditional deterministic sizing methods.

As we scale toward nanometer technologies, the increase in interconnect parameter variations will bring significant performance variability. New design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new performance models which accurately capture the manufacturing realities. In this paper, we present a Linear Fractional Transform (LFT) based model for interconnect Parametric Uncertainty. This new model formulates the interconnect parameter uncertainty as a repeated scalar uncertainty structure. With the help of generalized Balanced Truncation Realization (BTR) based on Linear Matrix Inequalities (LMI's), the new model reduces the order of the original interconnect network while preserves the stability. This paper also shows that the LFT based model even guarantees passivity if the BTR reduction is based on solutions to a pair of Linear Matrix Inequalities (LMI's) which generalizes Lur'e equations.

Deformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.

As the feature size is scaled down to 90 nm and below, fundamental modeling changes, such as the nonlinearity and higher frequencies of signals, require driver-load models to take into account propagation delay and slew rates. The conventional single Ceff (one-ramp) with lumped RC model is no longer accurate. In this paper we propose a new multi-ramp model with general RLC interconnects as loads. This new model accurately predicts both the 50% delay and the overall output waveform shape with inductance effects.

This paper presents a method for general reduced order analysis of linear circuits with a large number of independent sources. This type of circuit is used to model the power grid in power supply noise analysis for example. The large size of the linear circuit model renders circuit simulation inefficient. The large number of independent sources makes conventional multi-port model reduction ineffective. In order to address these problems, this paper proposes an extended Krylov subspace method which constructs a transformation matrix based on the dynamics of the circuit as well as the source excitations, thus avoiding the multi-port problem of model reduction. The transformation matrix is then used to reduce the given circuit to a smaller circuit model, which allows for more efficient analysis.

In this paper, we provide a new passive model order reduction algorithm on interconnects, which is based on the Chebyshev expansion of their impulse response. The Chebyshev coefficient matrices of the impulse response of the reduced order model up to a given order remain the same as those of the original network, so that the time domain transient response of the reduced order model matches that of the original network well. Compared with the model order reduction algorithms based on the frequency domain response, it is more efficient in dealing with complicated transient waveforms of interconnects where strong inductance effects are involved.

With the increase in signal speed and the development of process technology, distributed RC line model is found to be more suitable for on-chip interconnects than lumped RC model, especially for interconnects around and below 0.25 /spl mu/m. In this paper, we first describe a new explicit form for crosstalk approximation for coupled RC lines. Then we introduce a novel passive model order reduction technique for distributed RC lines. These two parts serve as two steps in static noise analysis of full on-chip interconnect networks called pruning process and static analysis process.

A new Chebyshev expansion based model for distributed interconnect networks is presented in this paper. Unlike the moment methods, this new model is optimal and it does not require the knowledge of expansion points. An automatic order selection scheme is also included in the new model. By using the integrated congruence transform, we guarantee the passivity of the new model for distributed interconnect networks. Because of the orthogonality of Chebyshev polynomials, the Modified Gram-Schmidt algorithm can be simplified. In the experimental examples, the new model is found to be accurate and efficient.

In this paper, \ve provide a multipoint moment matching model for mult iport distributed interconnect net~vorks.We introd uce a ne~v concept: integratcd-congruence transform ~vhichcan be apphed to the partial differential equations of a distributed line and generate a passive finite order system as its model.Lloreover, ~vedso provide an efficient algorithm b~sed on the L2 Hilbert space theory so that exact moment matching at multiple points can be obtained.

In this paper we use the method of characteristics to derive a new simulation model of lossy transmission lines, and we present the sensitivity analysis in the time-domain. The simulation model is as fast as the recursive convolution model based on moment matching and Pade' approximation, but does not have the stability problem. The sensitivity analysis model is particularly useful for transmission line circuits containing nonlinear elements, and is believed to be the first time-domain model. Also we show that any nonlinear circuit element has a very simple linear model in sensitivity analysis. Furthermore, we demonstrate that for any circuits, the modified nodal admittance (MNA) matrices in simulation and in sensitivity analysis are the same, therefore no LU decomposition is needed in sensitivity analysis. The contributions in this paper have been implemented into a general-purpose program CSSC which shows excellent accuracy and efficiency in both simulation and sensitivity analysis of transmission line circuits.