We present the development and implementation of the Itty Bitty Computing Machine (IBCM), a machine language designed specifically to be taught to lower-level undergraduate students. The presentation of the material takes about one-week of lecture, and allows understanding of all the concepts of machine language without having to deal with the complexity of modern machine language implementations, such as x86 and MIPS. A number of pedagogical aspects are addressed concisely via IBCM, such as treating all data as untyped and performing arithmetic on instructions.

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After 50 years, it is time to seriously reassess some of the basic premises of engineering education. The long-term needs of engineers and society demand it. To keep up with the changes in both technology and engineering practice we have tried to add content to a more or less fixed-size program. There are three possibilities for a resolution: to lengthen the program, to do more in the same time, or to make it continuous. In fact, we must do all three, and those are the first three challenges. The issues are not all just quantitative, however. The qualitative, practical experience of "design under constraint" needs to become an integral part of engineering education, and we need to find a way to engage more faculty with personal experience in the practice of engineering. Likewise, we need to bring more diverse backgrounds to bear on engineering problems, to increase the creativity, and hence to engineer better. Hence the fourth and fifth challenges. Last, we engineering educators must accept the responsibility for ensuring a technologically literate citizenry.

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes traditional caching schemes effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible. Unlike most other hardware prefetching or stream buffer designs, this system does not increase bandwidth requirements. The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of special purpose hardware. We present simulation results for fast-page mode and Rambus DRAM memory systems and we describe a prototype system with which we have observed performance improvements for inner loops by factors of 13 over traditional access methods.

Processor speeds are increasing rapidly and memory speeds are not keeping up. Streaming computations (such as multimedia or scientific applications) are among those whose performance is most limited by the memory bottleneck. Rambus hopes to bridge the processor/memory performance gap with a recently introduced DRAM that can deliver up to 1.6 Gbytes/sec. We analyze the performance of these interesting new memory devices on the inner loops of streaming computations, both for traditional memory controllers that treat all DRAM transactions as random cacheline accesses, and for controllers augmented with streaming hardware. For our benchmarks, we find that accessing unit-stride streams in cacheline bursts in the natural order of the computation exploits from 44-76% of the peak bandwidth of a memory system composed of a single Direct RDRAM device, and that accessing streams via a streaming mechanism with a simple access ordering scheme can improve performance by factors of 1.18 to 2.25.

As the processor-memory performance gap continues to grow, so does the need for effective tools and metrics to guide the design of efficient memory hierarchies to bridge that gap. Aggregate statistics of cache performance can be useful for comparison, but they give us little insight into how to improve the design of a particular component. We propose a different approach to cache analysis-viewing caches as filters-and present two new metrics for analyzing cache behavior: instantaneous hit rate and instantaneous locality. We demonstrate how these measures can give us insight into the reference pattern of an executing program, and show an application of these measures in analyzing the effectiveness of the second level cache of a particular memory hierarchy.

Conventional approaches to building and assessing securitycritical software are based on the implicit assumption that security is the single most important concern and can be the primary factor driving the software development process. Changes in the marketplace and the nature of security requirements have brought this assumption into question. There is now a large class of systems in which security must compete with other development goals. A risk-driven process model of software development provides a framework for building software that balances conflicting requirements. But a risk-driven process invalidates many of the assumptions made by conventional approaches to the specification and verification of security requirements. This paper presents a new approach to assessing the degree to which software meets its security requirements. It does not propose a new specification notation or analysis technique, but provides a general framework into which existing notations and techniques ...

Information flow predicates are properties of sets of traces and therefore cannot be handled under the Alpem-Schneider framework and the Abadi-Lamport Composition Principle. McLean proposed a theory (1994) to investigate the composition properties of these predicates and derived a partial order on them. In this paper we present an alternate framework based on many-sorted predicate logic for specifying the information flow properties and show that this framework can be used to reason about the composition of such properties that is amenable to automated theorem proving.

The coming of giga-bit networks makes possible the realization of a single nationwide virtual computer comprised of a variety of geographically distributed high-performance machines and workstations. To realize the potential that the physical infrastructure provides, software must be developed that is easy to use, supports a large degree of parallelism in the application code, and manages the complexity of the underlying physical system for the user. Legion is a metasystem project at the University of Virginia designed to provide users with a transparent interface to the available resources, both at the programming interface level as well as at the user level. Legion addresses issues such as parallelism, fault-tolerance, security, autonomy, heterogeneity, resource management and access transparency in a multi-language environment. In this paper, we present a high-level overview of Legion, its vision, objectives, a brief sketch of how some of those objectives will be met, and the current status of the project.

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes caches effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe and evaluate a Stream Memory Controller system that combines compile-time detection of streams with execution-time selection of the access order and issue. The technique is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. With our prototype system, we have observed performance improvements by factors of 13 over normal caching. 1. INTRODUCTION...

With the rapid growth of the information age, open distributed systems have become increasingly popular.The need for protection and security in a distributed environment has never been greater.The conventional approach to security has been to enforce a system-wide policy, but this approach will not work for large distributed systems where entirely new security issues and concerns are emerging.We argue that a new model is needed that shifts the emphasis from "system as enforcer" to user-definable policies.Users ought to be able to select the level of security they need and pay only the necessary overhead.Moreover.ultimately, they must be responsible for their own security.This research is being carried out in the context of the Legion project.We start by describing the objectives and philosophy of the overall project and then present our conceptual model and design decisions.A set of technical challenges and related issues are also addressed.

As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance, factor for many applications. Several approaches to bridging this performance gap have been suggested. This paper examines one approach, access ordering, and pushes its limits to determine bounds on memory performance. We present several access-ordering schemes, and compare their performance, developing analytic models and partially validating these with benchmark timings on the Intel i860XR.>

We propose the view that formal specification of a security critical system can be realized by placing suitable restrictions on the otherwise unrestricted functional behavior of its entities. We propose a framework based on traces for developing the specification of such a system. We come up with the characterization of a specification that maximizes functionality of the system with respect to the security policy that it is required to satisfy. The utility of the concepts developed in this paper are illustrated by considering the implementation of MLS policy expressed as restrictions on the information flow relations using the access control mechanisms provided by the take-grant model.>

article Free Access Share on Undergraduate computer science education: a new curriculum philosophy & overview Authors: John C. Knight Department of Computer Science, University of Virginia, Charlottesville, VA Department of Computer Science, University of Virginia, Charlottesville, VAView Profile , Jane C. Prey Department of Computer Science, University of Virginia, Charlottesville, VA Department of Computer Science, University of Virginia, Charlottesville, VAView Profile , Wm. A. Wulf Department of Computer Science, University of Virginia, Charlottesville, VA Department of Computer Science, University of Virginia, Charlottesville, VAView Profile Authors Info & Claims ACM SIGCSE BulletinVolume 26Issue 1March 1994 pp 155–159https://doi.org/10.1145/191033.191093Online:12 March 1994Publication History 17citation305DownloadsMetricsTotal Citations17Total Downloads305Last 12 Months10Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This report describes the results of studies of the WM architecture—its performance, the values of some of its key architectural parameters, the difficulty of compiling for it, and hardware implementation complexity. The studies confirm that, with comparable chip area and without heroic compiler technology, WM is capable of outperforming traditional scalar architectures by factors of 2-9. They also underscore the need to devise higher bandwidth memory systems.

Abstract Four programming languages (Fortran, Cobol, Jovial and the proposed DoD standard) are compared in the light of modern ideas of good software engineering practice. The comparison begins by identifying a core for each language that captures the essential properties of the language and the intent of the language designers. These core languages then serve as a basis for the discussion of the language philosophies and the impact of the language on gross program organization and on the use of individual statements.

Traditionally, the first two programming courses have emphasized basic techniques and skills—the details of a programming language, basic problem solving and program development, “structured programming”, the manipulation of simple data structures and files, basic sorting and searching algorithms, etc.

The programming language Alphard is designed to provide support for both the methodologies of "well-structured" programming and the techniques of formal program verification. Language constructs allow a programmer to isolate an abstraction, specifying its behavior publicly while localizing knowledge about its implementation. The verification of such an abstraction consists of showing that its implementation behaves in accordance with its public specifications; the abstraction can then be used with confidence in constructing other programs, and the verification of that use employs only the public specifications.

The extent to which resource allocation policies are entrusted to user-level software determines in large part the degree of flexibility present in an operating system. In Hydra the determination to separate mechanism and policy is established as a basic design principle and is implemented by the construction of a kernel composed (almost) entirely of mechanisms. This paper presents three such mechanisms (scheduling, paging, protection) and examines how external policies which manipulate them may be constructed. It is shown that the policy decisions which remain embedded in the kernel exist for the sole purpose of arbitrating conflicting requests for physical resources, and then only to the extent of guaranteeing fairness.

An overview of the hardware and philosophic context in which the Hydra design was done is discussed. The construction methodology is discussed together with some data which suggests the success of this methodological approach.

Abstract Within a programmed system, we may distinguish between different kinds of information in order to control the use of each kind by separate security policies, where each policy is tailored to the sensitivity and desired dissemination of that one kind of information. This paper analyses the implications of implementing security policies and describes mechanisms which can be used as the basis for constructing operating systems with the desired security attributes.

Deals with the problem of reliability in a hardware/software system. More specifically it deals with the strategy used to achieve reliability in a particular hardware/software system built by the author and his colleagues. Rather than dealing with the myriad details of the reliability aspects of this system, the paper focuses on the design philosophy which aims at keeping the system operational even though the underlying hardware may be malfunctioning. This philosophy is essentially an extension of the `modular' programming methodology to include dynamic error detection and recovery.

Lest the readers of this review be misled by the title of the book being considered, it is not a definitive text on the subject of program testing. Nor is it a catalogue of existing, known, and practical techniques for program testing from which the interested reader may choose an appropriate one for the validation of some particular program.

This paper proposes a scheme for improving the throughput of multi-programming systems. The basis of the proposal is the collection of a suitable set of measures of total system performance as well as corresponding per-process measures. Two types of control over system performances are suggested: (1) dynamic tuning of allocation policies to reflect the total system load, and (2) adjustment of the mix of processes competing for system resources in such a way as to keep the system within the range over which its allocation policies function properly.This work was supported in part by the Advanced Research Projects Agency at the Office of the Secretary of Defense (F 44620-67-C-0058) and is maintained by the Air Force Office of Scientific Research. Reproduction in whole or in part is permitted for any purpose of the United States Government.