The Session Initiation Protocol (SIP) is at the root of many sessions-based applications such as VoIP and media streaming that are used by a growing number of users and organizations. The increase of the availability and use of such applications calls for careful attention to the possibility of transferring malformed, incorrect, or malicious SIP messages as they can cause problems ranging from relatively innocuous disturbances to full blown attacks and frauds. To this end, SIP messages are analyzed to be classified as “good” or “bad” depending on whether this structure and content are deemed acceptable or not. This paper presents a classifier of SIP messages based on a two stage filter. The first stage uses a straightforward lexical analyzer to detect and remove all messages that are lexically incorrect with reference to the grammar that is defined by the protocol standard. The second stage uses a machine learning approach based on a Support Vector Machine (SVM) to analyze the structure of the remaining syntactically correct messages in order to detect semantic anomalies which are deemed a strong indication of a possibly malicious message. The SVM “learns” the structure of the “good” and “bad” SIP messages through an initial training phase and the SVM thus configured correctly classifies messages produced by a synthetic generator and also “real” SIP messages that have been collected from the communication network at our institution. The preliminary results of such classification look very promising and are presented in the final section of this paper.

Voice and multimedia communications are rapidly migrating from traditional networks to TCP/IP networks (Internet), where services are provisioned by SIP (Session Initiation Protocol). This paper proposes an on-line filter that examines the stream of incoming SIP messages and classifies them as good or bad. The classification is carried out in two stages: first a lexical analysis is performed to weed out those messages that do not belong to the language generated by the grammar defined by the SIP standard. After this first stage, a second filtering occurs which identifies messages that somehow differ - in structure or contents - from messages that were previously classified as good. While the first filter stage is straightforward, as the classification is crisp (either a messages belongs to the language or it does not), the second stage requires a more delicate handling, as it is not a sharp decision whether a message is semantically meaningful or not. The approach we followed for this step is based on using past experience on previously classified messages, i.e. a "learn-by-example" approach, which led to a classifier based on Support-Vector-Machines (SVM) to perform the required analysis of each incoming SIP message. The paper describes the overall architecture of the two-stage filter and then explores several points of the configuration-space for the SVM to determine a good configuration setting that will perform well when used to classify a large sample of SIP messages obtained from real traffic collected on a VoIP installation at our institution. Finally, the performance of the classification on additional messages collected from the same source is presented.

Computations in Support Vector Machines (SVM) involve a large number of vector multiplications. When implementing such architectures on a stand alone, embedded system, the complexity of the hardware implementation of the multipliers can be a limiting factor. This paper proposes a representation of numerical data to be processed by an approximation of the logarithm of the number, thus allowing the substitution of expensive multipliers with simpler adders. Additional circuitry is proposed to translate between standard and the proposed pseudo-logarithmic number representation. The operations for the representation translation, addition and multiplication with pseudo-logarithmic numbers have been implemented in software and several experiments have been carried out to assess their performance when used in a SVM-based computational architecture that was used for data classification. The results obtained show that the proposed representation yields an accuracy that is comparable with that obtained by using standard floating point or fixed point number representation.

The availability of powerful field programmable gate arrays (FPGA) has been exploited for their ability to rovide hardware solutions for many application areas, resulting in high-performance systems that can operate in real time by operating in parallel. The support vector machine computational paradigm can be cast as a collection of multiple streams operating in parallel on one such FPGA. This paper presents a parallel architecture that implements an SVM on a Xilinx FPGA. The results obtained by using this architecture for a complex pattern classification from high-energy physics involving thousands of patterns are reported and discussed, comparing the performance obtained by this architectural solution to that of a simpler sequential architecture.

In this paper we show how to map a LSSVM on digital hardware. In particular, we provide a theoretical analysis of quantization effects, due to finite register lengths, that leads to some useful bounds for computing the necessary number of bits for a correct hardware implementation. Then, we describe a new FPGA-based architecture, the KTRON, which implements the feed-forward phase of a LSSVM.

In this paper a simple procedure for pattern pre-recognition is presented. The task is to recognize whether a given pattern should be interesting for further analysis or not. The description of the procedure presented in this paper is based on formal theory of fuzzy logic in narrow sense so that the procedure – being general – can be used for many other purposes where patterns are to be recognized.

The problem of recovering multipipelines in the presence of faulty stages is addressed. The stages are assumed to be organized in rows and columns. The pipeline stages are alternated with reconfiguring circuitry which is used for bypassing the faulty stages. The pipelines are configured by programming the switches in a distributed manner using fault information available locally. The configuration algorithm is optimal in the sense that it recovers the maximum number of pipelines under any fault pattern. Probabilistic bounds on the delay (the number of bypassed faulty stages) and yield (the number of nonfaulty pipelines recovered) are derived. It is shown that the maximum signal delay in any of the pipelines is O(log m), where m is the initial number of pipelines. A constant fraction of these pipelines can be recovered with the scheme, as opposed to an exponentially decreasing number when no reconfiguration is used. The reconfiguration scheme can also be used to provide fault-tolerant buses on a wafer.>

The well known divide-and-conquer paradigm has proved to be useful for deriving efficient algorithms for many problems. Several researchers have pointed out its usefulness for parallel processing; however, the problem of analyzing such parallel algorithms in a realistic setting has been largely overlooked. In this paper a realistic model for divide-and-conquer based algorithms is postulated; the efficiency of some algorithms is then analyzed, taking into account all relevant parameters of the model (time, data movement and number of processors.)

The binary tree is a natural way to organize complex computations by a computer. For problems that can be naturally divided into a tree structure, a great deal of parallelism may be employed. In this paper we examine several aspects of the binary tree structure as it relates to both multiprocessor systems and to VISI circuit design. First, we present an algorithm for mapping an arbitrary binary tree onto the plane. An analysis shows the density of this mapping. Second, we consider the problem of routing messages within a binary tree under the assumption that certain nodes may be faulty. Finally, we analyze the binary tree's capacity to transfer information between nodes and we compare it to the capacity of the linear array and the grid.

A new method of description of a straight line defined on a square grid is presented. The discrete equation of the straight line (desl) is introduced as an extension of the classical Cartesian equation, and applies to straight lines quantized on a grid by the grid intersect method. The desl includes a set of intercepts which can be scanned in proper order to generate the chain for the given straight line.