There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed synchronous circuit core. The clock frequency adjusts automatically to inter-and intra-chip process, voltage and temperature variations, making it possible to design the circuit assuming typical rather than worst-case conditions. The resulting circuit uses much fewer high-speed, low-voltage-threshold cells, and consequently has significantly reduced leakage power. Post-layout test results on a 32-bit microprocessor implemented in 90-nm technology showed 10X less leakage and 19% less dynamic power when operating under typical conditions, compared to a conventional, fixed-frequency implementation. The system is functional under all PVT corners.

Synchronous pipelines usually have a fixed clock frequency determined by the worst-case process-voltage-temperature (PVT) analysis of the most critical path. Higher operating frequencies are possible under typical PVT conditions, especially when the most critical path is not triggered. This paper introduces a design methodology that uses asynchronous design to generate the clock of a synchronous pipeline. The result is a variable clock period that changes cycle-by-cycle according to the current operations in the pipeline and the current PVT conditions. The paper also presents a simple design flow to implement variable-clock systems with standard cells using conventional synchronous design tools. The variable-clock pipeline technique has been tested on a 32-bit microprocessor in 90 nm technology. Post-layout simulations with three sets of benchmarks demonstrate that the variable-clock processor has a two-fold performance advantage over its fixed-clock counterpart. The overhead of the added clock generation circuit is merely 2.6% in area and 3% in energy consumption, compared to an earlier proposal that costs 100% overhead.

This paper introduces enhancements to the synthesis of circuits that involve write-afterread (WAR) operations and use the four-phase handshake protocol. The paper demonstrates that the use of edge-triggering makes possible many useful trade-offs among speed, area and powerdelay product. Significant increases in speed are possible as a result of increased concurrency in the circuit's operation, which compensates for much of the penalty associated with the down phase of the four-phase protocol. It is also shown that concurrency can be increased by the judicious insertion of T-elements in the system's control structure. Simulation results for a 16-bit accumulator showed a speed increase of 50% and a reduction of 23% in the power-delay product. The speed of a radix-4 Booth multiplier increased by over 27% and its area and energy consumption were reduced by 5%. These results were derived using test circuits synthesized by Balsa and implemented in Synopsys using 180-nm technology.

A method for decomposing combinational functions for the purpose of obtaining a multilevel synthesis is proposed. A cascade of mapping stages is used to transform the function being synthesized into a simple one called the goal function. The goal function-usually a one-variable function-is selected at the outset and then used to guide the definition of the transformations to be implemented by the mapping stages. The resulting circuits are comparable in size to those derived from minimal prime-implicant covers. However, goal-oriented synthesis is faster, yields circuits that are easier to test, and offers more flexibility in the choice of gates.>

A novel, hybrid protocol LAN called TORNET2 is proposed, and its performance is evaluated. TORNET2 is a ring intended for high-speed applications in the 100 Mb/s range. Short-packet, high-priority traffic is handled by the register insertion technique. Combining this protocol with the early-release token protocol for handling low-priority asynchronous traffic is the novel aspect of TORNET2. The hybrid protocol operates in such a way that high-priority packets may be embedded in low-priority packets. This results in the best possible transfer delay for the high-priority traffic. In fact, the high-priority traffic is unaffected by the presence of low-priority traffic. Low-priority traffic is not locked out by high-priority traffic, but its transfer delay performance degrades as the volume of high-priority traffic increases. An approximate performance analysis of the TORNET2 network along with simulation results to verify the analysis is presented.>

Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f(x) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to minimize the number of such transitions. Two-variable functions are synthesized as a sum of products of literals, taking advantage of literals that are easily implemented in CCD technology. It is concluded that the proposed algorithms perform better than those published previously.>

In the context of mapping-based methods for multilevel circuit synthesis, the authors propose a method, called the direct implementation procedure (DIP), to synthesize combinational functions. An algebra is defined in which a set of mappings together with a parallel composition operation can produce arbitrary mappings. The resulting mappings can be easily implemented as macrocells. The DIP procedure is simpler than existing methods, and takes advantage of the property of mappings which produces fanout-free circuits. Thus, simple and easily testable combinational circuits can be synthesized using DIP and a mapping-based strategy such as the goal-oriented method.>

A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is simple and easy to use for any number of processors, buses, or memory modules and for arbitrary memory block size. The model is used to study the access time of the global memory as a function of the number of buses for different local-memory/global-memory traffic rates.>

Basic multivalued building blocks constructed using CCD (charge-coupled devices) technology are presented. They are used to realize simple threshold functions. Existing techniques for decomposition of multivalued multithreshold functions into simpler subfunctions are reviewed. Usage of the CCD technology in implementation of these subfunctions is discussed. Two new decomposition techniques are proposed. Their aim is to obtain realizations that are better suited to CCD technology in terms of the maximum number of thresholds per element and the generation of negative weights. Synthesis techniques based on the proposed decompositions are presented and compared. Although 4-valued logic functions are stressed, the techniques are, in principle, applicable to functions of any radix.

Abstract This paper presents a syntax‐directed editor dubbed SRE, for syntax recognizing editor. Unlike other syntax‐directed editors, SRE enables the user to edit programs with nearly the same natural and unrestrictive ease as a conventional text editor. In addition, it helps identify syntax errors and many typing errors before leaving the editor and attempting to compile a program. Programs are also formatted during entry, thereby providing immediate visual feedback of the recognized structure. The editor replaces the scanner/parser pass of a conventional compiler and thus reduces compilation time substantially.

TORNET is an experimental local area computer network presently being designed and built in the Computer Group Laboratory of the Department of Electrical Engineering at the University of Toronto. The network consists of a number of local rings, each attached to a central ring. The local rings employ a variation on the slotted-ring format that uses a limited insertion technique to achieve reasonable response times for character traffic among many devices and small computers. Two fixed-length packet formats (one byte or 128 bytes of data) are used on the local rings. Only the longer format is used on the central ring which generally provides record level access to shared specialized equipment.

This paper presents a virtual memory system which may be connected to the memory bus of a host computer. The system is based on the use of a separate processor to interface to the backing store and perform all the processing related to managing the virtual memory. The proposed approach provides a virtual memory that is transparent to the host processor, with one exception. When a memory reference generated by the host results in a page fault, a long delay is encountered. This delay corresponds to the time taken by the virtual memory controller to carry out a page transfer.

This paper presents a method for correlating performance measures of small computers to design parameters. An experiment is described in which execution times and memory space requirements are gathered for three small benchmark kernels when run on fifteen small computers. The benchmarks are drawn from three different application areas. All of them exercise only the CPU ↔ memory area of the machines, and I/0 operations are not involved.Using standard regression analysis techniques, this data is then used to calculate coefficients in empirical equations which relate the performance measures, time and space, to easily quantifiable design parameters of the machines.