Memory can be located close to a CPU, at remote sockets, or on devices connected via interconnects such as CXL or NVLink.A larger distance between memory and a core accessing the memory usually results in higher access latency.Software prefetching algorithms claim to hide memory access latencies by moving data to the CPU cache before a core accesses the data.In this work, we analyze to what extent software prefetching can hide increased memory access latencies.We evaluate these on seven systems, each offering different memory technologies and access latencies.We show that prefetching can increase performance by up to 2.6× and 2.8× for B + -Tree and binary search workloads.We find that CPU fill buffers, which track L1 cache misses, and a workload's memory intensity dictate how much access latency can be hidden.CPUs implement prefetches differently.We introduce microbenchmarks that identify concrete target cache and eviction strategies for different prefetch localities across x86 and ARM architectures.When the fill buffers are full, CPUs either drop prefetches or halt until all can be executed.We refer to these behaviors as weak and strong prefetching reliability.We introduce microbenchmarks identifying a CPU's reliability.When prefetching 8 KiB B + -Tree nodes, weak reliability achieves a speedup of 2× while strong reliability degrades performance with a slowdown of 2.5× for lookup workloads.

Data centers produce a significant and increasing amount of CO 2 emissions. In the past, these have been predominantly due to energy generation for powering data centers. With the transition to energy sources with lower carbon production, the embodied carbon (i.e., CO 2 and other greenhouse gas emissions during production, transport, and end-of-life) plays an increasing role when planning server lifecycles. While replacing an old server with newer hardware will typically reduce the power consumption of individual tasks, due to better efficiency of modern CPUs, offsetting the embodied carbon of new hardware can take months to tens of years, depending on the grid carbon intensity. In this demo, we invite attendees to interactively analyze the ecological lifecycles of modern database servers for different workloads and grid carbon intensities. Attendees can compare servers with different CPU architectures and estimate ecological deployment cycles for database servers.

The Compute Express Link (CXL) standard enables new forms of memory management and access across devices and servers. Based on PCIe, it enables cache-coherent access to remote memory. This widens the design space for database systems by expanding the available memory beyond memory local to the CPU. Efficiently utilizing CXL-attached memory requires conscious decisions by data systems about data placement and management. In this paper, we provide an in-depth analysis of database operation performance with data interleaved across multiple CXL memory devices. We experimentally evaluate the memory access performance for basic access patterns, the performance impact of placing data across multiple CXL memory devices for in-memory column scans and in-memory B+tree operations, and the performance impact of placing data in CXL memory for an in-memory database system when running the analytical TPC-H workload. Our experiments show that access to CXL-attached memory does not have to penalize performance over local access, but careful workload-aware data management is required. Our TPC-H evaluation shows that placing table columns based on access frequencies allows storing over 80% of the table data in CXL memory with a performance of 85% of a local-memory-only solution.