This paper presents a dual-band architecture, which combines radio-frequency energy harvesting (RFEH) and a wake-up receiver (WuRX) for wireless sensor networks (WSNs). By separating the wake-up and energy-harvesting frequency bands, the design eliminates co-channel interference (CCI), improving wake-up sensitivity. To achieve high integration, a frequency-blocking single-balun time-division multiplexing (FB-TDM) is proposed, enabling RFEH and WuRX to share antenna (ANT), matching network (MN), and balun across different frequency bands, without high-loss MOS switches or bulky off-chip filters. Moreover, to address missed detection caused by time division multiplexing (TDM), discontinuity-tolerant coding and correlator are proposed. The self-powered WuRX is implemented in a 65nm CMOS process, occupying an active area of 0.33 mm2. The measurement results show that the chip can harvest RF energy at -35 dBm with a DC output exceeding 0.45 V, and supports wake-up reception at -55 dBm with 50 bps data rate, 158 ms latency, and an energy cost of 3.712 nJ per activation.

For vibration monitoring applications, the wide-bandwidth low noise MEMS accelerometer with high efficiency is required. Conventionally, the sensor resonant frequency is increased to achieve wide bandwidth, which however trades off the sensor sensitivity and degrades system noise and power efficiency (FoM). To meet this challenge, this paper proposed a Microlevers Assisted Hybrid Damping (MAHD) system. Instead of increasing the resonant frequency, the MAHD system employs critical hybrid damping for bandwidth improvement, in order to avoid degradation of the system noise and efficiency. The critical hybrid damping is implemented with an interface circuit providing tunable electrostatic damping force. Asensor structure with microlever is employed to enhance the merit of the critical damping system. The interface circuit is fabricated by a commercial$0.18\mu $m CMOS process and the sensor is fabricated by a commercial surface micromachining process. The measurement results show that, without increasing the sensor resonant frequency, the proposed method improve the system 3dB-bandwidth and 5%-bandwidth by 454% and 550%, respectively. The noise floor is$68.33\mu $g/$\surd $Hz with$600\mu $A current consumption.

Spiking Neural Networks (SNN) is well-suited for always-on near-sensor intelligence, due to its spike-driven nature; however, its IC realization is complicated by the temporal dimension. Asynchronous low-power SNN chips employing analog computing-in-memory (CIM) techniques have been demonstrated to enable real-time, energy-efficient inference. However, their tolerance to nonidealities remains to be improved, and their peripherals for multiphase or multilevel signal control are complex. This paper proposes a general-purpose, spike-driven SNN chip designed with efficient analog-computing circuits, featuring two key contributions: 1) A compact direct current-add CIM synapse design that significantly simplifies control peripherals, thereby reducing latency and enhancing energy efficiency. 2) A PVT-aware multi-network learning method underpinned by detailed analyses and modeling, coupled with a label-normalization-based synapse-strengthening method, to mitigate the impact of nonidealities. Fabricated in 65nm CMOS process, the proposed design achieves a state-of-the-art latency of$10\mu $s and an energy efficiency of 0.40pJ/spike. The generalization ability of the design is verified through its successful application to two distinct tasks: voice activity detection (VAD) and ECG anomaly detection. The tolerance to nonidealities is validated by the VAD task. The ten chips maintain over 90% detection accuracy across signal-to-noise ratios (SNRs) of$4\sim 16$dB, ±10% supply voltage variation, and a temperature range of$- 25\sim 55^{\circ }$C.

This paper demonstrates a 12-bit 100-MS/s PVT-stabilized pipelined-SAR ADC with fully integrated on-chip calibration. Two key innovations facilitate over 65-dB SNDR with less than 2.2-dB variation from -20 °C to 125 °C: First, a PVT-stabilized nested negative-C topology boosts open-loop gain ($G_{ol}$) of the residue amplifier (RA) by 28 dB, enabling one-time foreground calibration that avoids persistent inter-stage gain error tracking. Second, a dynamic auto-zeroing technique addresses offsets from both the RA and first-stage comparator through a switched-capacitor filter that extracts offsets based on the stochastic characteristics of residue signals. Dynamically level-shifted capacitors (DLSC) are embedded at the differential inputs to neutralize aliased noise and thermal noise, so that the offset drifts under high-temperature environment are effectively cancelled. Fabricated in 40-nm CMOS, the prototype occupies 0.22 mm2and achieves 65.5-dB SNDR and 83-dB SFDR at Nyquist input while consuming 3.7 mW. Across six tested chips, the prototype design exhibits merely 2.2-dB SNDR degradation over -20 °C ~ 125 °C and 1.3-dB variation under ± 5 % supply voltage (1.1 V) fluctuations.

This article presents a Single-Photon Avalanche Diode (SPAD)-based LiDAR sensor featuring a low-resource time-of-flight (ToF) extraction architecture with robust background-light suppression. The proposed ToF extraction architecture integrates a first effective event detection (FEED) circuit, a shared histogram accumulation circuit, and an address-event representation (AER)-based peak detection circuit. The FEED circuit employs a tunable firing threshold (Fire${}_{\mathrm {th}}$) to suppress background-induced false triggers, and determines whether the shared histogram circuit should operate in first-event or last-event mode. An artificial neural network (ANN) is trained to optimize Firethunder varying background and ranging conditions. The shared histogram architecture exploits the complementary histogram characteristics of the two modes to store the histogram results of two pixel groups in a single shared RAM, thereby improving memory utilization while enabling adaptive exposure control to avoid redundant accumulations. Experimental results demonstrate operation under up to 100 klux background light intensity, a maximum ranging distance of 46 m, and a maximum non-linearity of 0.13 m.

This paper presents a DFT-IDFT-based minimum-segment calibration technique for SAR ADCs, specifically targeting capacitor mismatch-induced nonlinearity under incoherent sampling conditions. By employing multi-term cosine-sum window functions, spectral leakage is significantly suppressed, enabling accurate digital estimation of nonlinear bit-weight errors. The proposed method employs lookup tables (LUTs) to integrate DFT/IDFT and windows, greatly simplifying ADC error extraction, while employingLDL${}^{\mathbf {T}}$decomposition for numerically stable least-squares estimation. A novel metric, Maximum Single-Tone Offset Attenuation (MSTOA), is introduced to evaluate window functions’ efficacy in suppressing spectral leakage. Among digital calibration methods, the minimum-segment approach achieves substantial improvement in calibration accuracy while maintaining comparable computational complexity. The non-iterative, one-shot error extraction method eliminates convergence delays inherent in iteration-based methods. Additionally, built-in self-test (BIST) capability enables concurrent dynamic performance evaluation. Measurement results from a 20-bit 1-MS/s prototype implemented in 180-nm CMOS demonstrate that post-calibration SNDR/SFDR can be improved by 22.7dB and 27.3 dB, respectively.

Piezoelectric energy harvesting interfaces are mainly categorized into single-stage conversion interfaces with high efficiency and cascaded conversion interfaces with high output power. However, the single-stage conversion interface has limited output power and lacks an MPPT configuration, while the cascaded conversion interface suffers from low end-to-end harvesting efficiency due to the cascaded conversion process. This paper proposes a load-independent Split-S-SSHI (SS-SSHI) interface with an envelope-tracking MPPT that can simultaneously achieve high output power and high end-to-end efficiency. In addition, the split S-SSHI eliminates the need for a rectifier capacitor and enhances the response speed of the MPPT. The proposed harvester is fabricated in a 0.18-$\mu $m CMOS process with a low quiescent current of 39 nA. Measurements indicate a maximum MPPT efficiency and end-to-end harvesting efficiency up to 99.5% and 91.9%, respectively, and the maximum output power reaches 9.7 times that of a conventional full-bridge rectifier.

The JESD204C receiver has emerged as a mainstream SerDes interface in high-speed analog-to-digital converters (ADCs). However, it faces challenges such as long link initialization time, substantial hardware area and power consumption. To address these issues, this paper presents an optimized link-layer design for the JESD204C receiver, with a focus on enhancing synchronization header (SH) detection efficiency and reducing the area of Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) decoding circuits. First, a dynamic search space(DSS)-based SH detection method is proposed. Leveraging multi-level XOR logic, this method efficiently eliminates non-transition bits from the data stream, enabling rapid localization of the 2-bit SH and thus shortening the synchronization delay during link establishment. Second, to mitigate the large area overhead of the data link layers decoding module, a CRC and FEC decoder (CAFD) with a logic-sharing architecture is designed: common factors in the decoding process are identified and shared, significantly reducing redundant hardware resources. Additionally, a low-complexity critical path identification algorithm is introduced to guide factor-sharing constraints, ensuring the decoder meets timing requirements while optimizing area. Finally, the proposed JESD204C receiver is implemented with a 28-nm CMOS process and verified on an FPGA platform. Experimental results show that the design not only eliminates redundant SH detection operations and accelerates link initialization/synchronization but also improves hardware resource utilization. Compared with state-of-the-art solutions, the hardware area and power consumption are reduced by 47.6% and 15.1%, respectively, while the SH locking time is shortened by 60%.

This paper presents a PVT-insensitive and wide electrode DC offset (EDO) elimination range bio-signal instrumentation amplifier (Bio-IA). A bulk-driven bias voltage adaptive adjustment (BD-VAA) OTA is proposed to effectively suppress the leakage current of the input transistors’ gate in the amplifier, thus stabilizing the bias voltage of the Bio-IA. In addition, a pre-feedback analog DC servo loop (PF-ADSL) based on an expanded input-stage (EIS) fully differential difference amplifier (DDA) buffer is proposed to increase the EDO elimination range. Each input stage in the DDA employs the improved parasitic capacitance shielding (IPCS) technique, which significantly enhances both the common-mode (CM) input impedance and the differential-mode (DM) input impedance. The Bio-IA is implemented based on a 65 nm CMOS process. Measurement results indicate that the input bias voltage of the Bio-IA is stable. The EDO elimination range of the Bio-IA is extended to$\pm ~240$mV, the CM input impedance of the Bio-IA is as high as 39.9G$\Omega $, and the DM input impedance reaches 5.2 G$\Omega $.

For wearable applications, the small size low noise MEMS accelerometer with high efficiency is required. However, the sensitivity of the MEMS sensor reduces with the sensor size scaling down, leading to deterioration of the circuit noise. To meet this challenge, the interface circuit with high-voltage pulse excitation (HVPE) and active noise cancelation readout technique is proposed. The HVPE reduces the circuit noise and the wire resistance noise significantly without introducing additional electrostatic force to the sensor. The drift and mismatch problems of the HVPE are addressed by three specific correction circuits. The power efficiency of the system is optimized by the capacitance-to-voltage converter with active noise cancellation and pulse current supply. The propose HVPE technique is demonstrated in an interface IC fabricated by$0.18\mu $m BCD process and tested with a small size MEMS accelerometer (0.64mm2/axis). The measurement result shows that this IC has achieved a noise floor of$32.5\mu $g/$\surd $Hz with 2kHz bandwidth and$80\mu $W power consumption.

A resource-efficient readout integrated circuit (ROIC) optimized for single-photon avalanche diode (SPAD) array has been implemented in 180 nm CMOS technology to enable high-precision depth sensing. A synchronous-sampling-based iterative candidate histogram circuit is proposed, which leverages photon-trigger correlation analysis to significantly reduce memory consumption, requiring only 90 bits of memory per pixel. An extremum-tracking circuit is employed to enhance the noise suppression capability of the iterative candidate histogram by identifying trigger timestamps with the maximum photon counts within each exposure cycle. To achieve sub-nanosecond range accuracy, a multi-phase synchronous sampling circuit combined with a differential fitting algorithm is employed. A macro-pixel reconstruction circuit is employed to enable adaptive imaging resolution, supporting configurable modes of$160\times 120$,$40\times 40$, and$20\times 20$. The core power of the ROIC is 14.36 mW. To evaluate the ranging performance of the ROIC, a SPAD-based LiDAR prototype is implemented, incorporating a$320\times 240$SPAD array. Experimental results demonstrate that the ROIC achieves 1.8 cm ranging precision with over 90 % measurement success rate within a 30 m detection range and 30 klux background illumination.

Conventional duty-cycle-based (DCB) maximum power point tracking (MPPT) schemes generally assume a 50% duty cycle for operation at the maximum power point (MPP). However, due to nonideal losses in the piezoelectric transducer (PZT), such as dielectric loss, mechanical damping, and rectifieroff-state leakage, the actual optimal duty cycle deviates from this nominal value. This brief develops a theoretical model that incorporates these losses, which is derived, analyzed, and experimentally validated using a piezoelectric energy harvester (PEH) integrated with a bias-flip MPPT regulating rectifier (BMRR). Measurement results show that the optimal duty cycle ranges from 42.3% to 42.8%, under which the rectifier delivers 1.1 times the output power compared to operation at a fixed 50% duty cycle. Furthermore, the proposed rectifier achieves a peak power conversion efficiency (PCE) of 89.6% and demonstrates a 7.4-fold improvement in energy extraction compared to a full-bridge rectifier (FBR).

This work presents a self-feeding-priority power management strategy for a multi-input piezoelectric energy harvester based on the synchronous electric charge extraction (SECE). While conventional SECE can harvest intermittent vibration energy, it typically relies on battery power, which is continuously drained during vibration-free periods, causing net energy loss. The proposed solution prioritizes using harvested energy to sustain harvester operation, with surplus directed to storage, preventing consumption of stored energy when environmental kinetic energy is absent. In addition, by integrating a voltage clamping circuit and multistep charge extraction, the harvester efficiently harvests energy from diverse kinetic energy, operating over a wide input range. Fabricated in 180 nm CMOS technology, the harvester supports autonomous cold-start from 0.35 V and reliably harvests energy from periodic, shock, plucking, pressing, and walking-induced vibrations.

This brief presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipelined analog-to-digital converter (ADC) with the reusing feedback capacitor (RFC) technique. With the proposed RFC technique, the feedback capacitor can simultaneously accomplish the 1st-stage residue transfer, the 2nd-stage quantization error extraction and feedback, and reference voltage matching, which reduces circuit complexity and enhances linearity. To mitigate the noise leakage resulting from gain error, a single-stage closed-loop gain-boosted cascoded floating inverter amplifier (GBCFIA) with 85-dB open-loop gain is proposed. The GBCFIA demonstrates a combination of robustness, high accuracy, and enhanced energy efficiency. Fabricated in a 65-nm CMOS process, the ADC prototype achieves a measured 78.5-dB signal-to-noise and distortion ratio (SNDR) in a 250 MS/s at an oversampling ratio (OSR) of 8. With 2.96-mW power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 175.7 dB.

This work presents a multibit$\Delta \Sigma $time-to-digital converter (TDC) employing a space–time averaging (STA) technique, designed for ultrawideband (UWB) transceivers to achieve fine-resolution time-of-flight (ToF) ranging. The proposed TDC offers both high time resolution and strong immunity to bit errors. By dynamically controlling the input reference signals of multiple phase detectors (PDs), the STA technique significantly reduces the quantization error of the$\Delta \Sigma $TDC, thereby achieving fine time resolution with a limited oversampling ratio (OSR). Additionally, by introducing a delay in the PD reset path, the TDC provides strong immunity to bit errors caused by UWB receiver misdetection. Implemented in 65-nm CMOS, the proposed multibit$\Delta \Sigma $TDC achieves a root-mean-square (rms) error of 14.43ps with an OSR of 50, consuming$276.5~\mu $W at a 10-MHz clock frequency from a 1-V supply.

Event Cameras offer appealing advantages, including power efficiency and ultra-low latency, driving forward advancements in edge applications. In order to leverage mature frame-based algorithms, most approaches typically compute dense, image-like representations from sparse, asynchronous events. However, they are often unable to capture comprehensive information or are computationally intensive, which hinders the edge deployment of event-based vision. Meanwhile, pillar-based paradigms have been proven to be efficient and well established for dense representations of sparse data. Hence, from a novel pillar-based perspective, we present EventPillars, an efficient, comprehensive framework for dense event representations. To summarize, it (i) incorporates the Temporal Event Range to describe an intact temporal distribution, (ii) Activates the Event Polarities to explicitly record the scene dynamics, (iii) enhances the target awareness by a spatial attention prior from Normalized Event Density, (iv) can be plug-and-played into different downstream tasks. Extensive experiments show that our EventPillars records a new state-of-the-art precision on object recognition and detection datasets with surprisingly 9.2× and 4.5× lower computation and storage consumption. This brings a new insight into dense event representations and is promising to boost the edge deployment of event-based vision.

In this paper, a neural network-based approach for the co-design of transmission channels and matching networks in chiplet-based 2.5-D integrated circuits (ICs) for radio frequency (RF) applications is presented. This work proposes a dual-neural network framework that synergizes cascaded S-parameter modeling with data augmentation techniques. First, a cascaded method is developed to accurately model the 2.5-D signal transmission channel, incorporating through-silicon vias (TSVs), redistribution layers (RDLs), and matching networks, validated against commercial circuit tools. A convolutional neural network (CNN) is then trained to inversely map S-parameter requirements to optimal structural and matching network parameters. Concurrently, a denoising diffusion probabilistic model (DDPM) generates augmented S-parameter datasets to expand the design space while reducing simulation overhead. The framework enables automated compliance with critical constraints while optimizing secondary objectives such as matching network area minimization and frequency response enhancement. This work provides a robust artificial intelligence (AI)-driven methodology for high-efficiency RF interconnects in heterogeneous integration platforms.

基于半模基片集成波导(HMSIW),提出一种宽阻带小型化双工器。该双工器将双模谐振器(DMR)与单模谐振器(SMR)相结合。采用HMSIW技术突破了SMR在小型化方面的限制,同时有效解决了SMR中常见的TE202模式对宽阻带性能的限制。采用TE101/TE301 DMR设计并制造了一个二阶原型,原型的中心频率分别为10.34 GHz和13.90 GHz。测量结果显示,该双工器的阻带范围为2.16f1(f1是通道1的中心频率),具有优于20 dB的带外抑制水平。与此同时,该双工器的尺寸被显著缩小至1.363λg2(λg是f1时介质基底中的导波波长)。

This paper presents a low-noise class-F23voltage-controlled oscillator (VCO) with harmonic resonance expansion and$2^{\mathrm {nd}}$/$3^{\mathrm {rd}}$-harmonic outputs for multiband mm-wave applications. By using a single four-coil transformer to extend the common-mode (CM) and differential-mode (DM) harmonic resonance bandwidths, the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic resonances can be acquired without additional frequency alignment calibration. Meanwhile, benefiting from the favorable differential response at the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic frequencies, the corresponding harmonic frequency outputs are extracted, simultaneously. Fabricated in 65-nm CMOS process, the proposed VCO achieves a frequency tuning range (FTR) of 20.8% from 10.71 GHz to 13.20GHz with 1-MHz offset phase noise (PN) from -117.4 to -114.5 dBc/Hz, while consuming 7.8-9.8 mW at 0.6 V. The VCO core area is only 0.054 mm2and the flicker noise corner is 310-450 kHz. The figure-of-merit (FoM) at 10-MHz offset scores 189.8-191.7 dBc/Hz. The harmonic outputs achieve a FTR of 21.42-26.40 GHz and 32.13-39.60 GHz, with a 1-MHz-offset PN from –110.5 to –107.5 dBc/Hz and –107.6 to –104.8 dBc/Hz.

This paper presents an image sensor system based on single-photon avalanche diode (SPAD) utilizing a hybrid time-of-flight (ToF) method, which achieves an imaging resolution of$64\times 128$based on a hybrid scanning system. The primary components of the image sensor system include a$16\times 8$SPADs array fabricated using 130nm CMOS technology, along with 128 passive quenching circuits and 128 pulse shaping circuits within the pixels, a digital signal processing (DSP) circuit implemented on the FPGA, and a laser driving circuit with adjustable pulse width. The laser pulse width can be adaptively modified according to the bin size of the partial histogram, thereby improving the signal-to-background light ratio (SBR) and reducing measurement jitter. The DSP incorporates a hybrid partial histogram (HPH) algorithm based on both direct time-of-flight (DToF) and indirect time-of-flight (IToF), along with a non-linear spatiotemporal coincidence detection (NSCD) circuit. The proposed HPH algorithm significantly reduces the storage resource requirements for histograms, eliminating the need for in-pixel time-to-digital converter (TDC). Each pixel’s histogram requires only 180 bits of storage resource. Moreover, the IToF algorithm effectively enhances the system’s measurement precision. The NSCD significantly improves the sensor’s background noise suppression and weak echo detection capabilities. Experimental results indicate that, under a background light intensity of 60 Klux, the image sensor can measure distances up to 60 m, with a measurement precision less than 1 cm.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a$\lambda $/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of$- 25~^{\circ }$C to$125~^{\circ }$C, and below 0.74 dB over supply variations of ±5%.

This paper presents a mode-reconfigurable 2nd-order noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) featured with the ability of optimizing the noise transfer function (NTF) synchronously. Three operation modes, the energy-saving (ES) mode, the normal (NM) mode, and the high-resolution (HR) mode, can be supported by reconfiguring the resolution of the internal SAR ADC (N${}_{\mathrm {SAR}}$) and the oversampling rate (OSR), while the NTF optimization is realized by modulating locations of zeros and poles in the context of a specific mode to enhance the NS effect. The prototype ADC is fabricated in a 180-nm CMOS and operates under a 1.8-V supply. Operating at 5MS/s sampling rate, the ADC’s OSR can be configured as 8 or 16 in different operation modes, so its bandwidth can be configured as 312.5kHz or 156.25kHz. With NSARand OSR reconfigured to be 8-bit and 8 for the ES mode, it achieves a signal-to-noise and distortion ratio (SNDR) of 80.3dB and consumes$201\mu $W. Attributing to the NTF optimization, 27% power saving can be reached in the ES mode with respect to that when the optimization were disabled for the same SNDR. In the HR mode, NSARand OSR are set to be 9-bit and 16, respectively. And a SNDR of 93.3dB is obtained at the expense of consuming$280\mu $W. It is evidenced that the SNDR can be boosted by 6.4dB owe to the NTF optimization, resulting in an optimal SNDR-based Schreier figure-of-merit (FoM${}_{\mathrm {S}}$) of 180.8dB for the ADC. The values for NSARand OSR are determined to be 9-bit and 8 for the NM mode, and the achievable SNDR is 88.2dB. The occupied core area is 0.537 mm2.

This paper presents a high-efficiency, wide-input power range ambient Radio Frequency Energy Harvester (RFEH) system, which comprises an adaptive 4-mode impedance matching network (IMN), a single-stage cross-coupled differential-drive (CCDD) rectifier, a maximum power point tracking (MPPT) circuit, and a power manager unit (PMU). To adaptively configure the impedance matching network and modulate the TONof the buck-boost converter, a feedback-free fast (F3) MPPT technique based on the input power detection and parameters direct adjustment is proposed. It can effectively address the trade-off between the speed and accuracy in the impedance matching as well as in the maximum power transmission. Therefore, the power conversion efficiency (PCE) of the proposed RFEH system has been greatly improved. The power manager unit (PMU) is composed of a buck-boost converter, a self-supply unit, and a load regulator, which is employed to implement the F3MPPT, startup, and self-powered of the RFEH system. The proposed design is fabricated in a 0.18-$\mu $m CMOS technology, and the chip area is about$1.52\times 0.78$mm2. The measurement results demonstrate that the proposed RFEH system can operate in a wide PINrange of −23 to 1 dBm with over 96% MPPT accuracy. It achieves PCE >20% in the PINrange of −17 dBm to 1 dBm, with a peak PCE of 49.4% at P$_{\mathrm {IN}}= -5$dBm.

This paper reports a dual-mode analog counter for Single Photon Avalanche Diode (SPAD)-based image sensors. With the proposed comparator feedback scheme, the precise counting step size configuration is achieved. Cascade counting mode and up/down counting mode are also supported. Additionally, a successive approximation (SA) type calibration method is also proposed to enhance the process, voltage, temperature (PVT) robustness of up/down counting step. With the calibration method, the analog counter in up/down counting mode supports adjusting the step of arrayed analog counters with a master-slave approach and this functionality has been validated through four slave counters. This dual-mode analog counter is fabricated in 180-nm CMOS process and primarily comprises two counting modules (up and down). In each counting module: the dynamic range is 10 bits with the step of 1.3 mV, the area is 79.25 μm2without storage capacitor, and the power consumption is 108.3 nW. The area of SA calibration circuit and four slave-counters is about 350 μm × 255 μm.

This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma ($\Delta$$\Sigma$) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC)$\Delta$$\Sigma$modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/$\surd$Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16$\mu$$\text{V}_\text{rms}$(0.5-100 Hz) and 1.93 to 3.51$\mu$$\text{V}_\text{rms}$(0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-$\text{V}_\text{pp}$differential input and can support 16$\times$power/BW reconfigurability with ENOB$>$15 bit. The complete system occupies an active area of 0.56 mm$^{2}$and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8$\mu$W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.

This article reports a high acoustic overload point (AOP) single-ended digital MEMS microphone system. For audio applications in high sound pressure environments, a high AOP MEMS microphone is required. The nonlinearity of MEMS microphone is contributed by the MEMS sensor and the signal path of the readout ASIC. For the MEMS sensor with fixed sensitivity, the low analog supply voltage in the readout ASIC is the main limitation to achieve high AOP. To address this challenge, a single-ended digital MEMS microphone system with a self-adaption loop (SAL) is proposed. The SAL automatically adjusts the gain of the analog front end and the digital back end by detecting the input signal, breaking the limitation of the analog supply voltage on the AOP of the system. Besides, the proposed system features an always-on characteristic, and the power consumption is scalable. A prototype is realized in a$0.153~\mu $m CMOS process, performing 67.34 dB-A SNR with an AOP of 132 dB SPL, consuming$738~\mu $A at 2.4 MHz sampling rate and 1.5-V supply voltage.

This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM’s sampling frequency$f_{s}$. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (~90dB) and linearly scalable power and BW (2.5nW/Hz) over a$\times 30$scaling range of$f_{s}$. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.

In this paper, we present an ultra-low power wake-up receiver (WuRX) with effective interference suppression capability. A specific robust design has been implemented to address the common interference issues in the industrial, scientific, and medical (ISM) frequency band. A mathematical expression is derived in this paper for the minimum signal-to-noise ratio (SNR) required by the comparator at which a envelope detector first (ED-first) WuRX can detect the wake-up message in the presence of interference. Aiming to meet the minimum SNR requirements, a quasi-direct coupling (QDC) baseband buffer scheme is proposed. Compared to the output SNR of traditional AC schemes, the QDC baseband buffer scheme achieves a 4.16 dB increase in output SNR under optimal conditions. To solve the problem where traditional comparator calibration schemes require recovery time after sudden disappearance of interference, the multipath signal detection (MPSD) scheme proposed in this paper can immediately detect information following the disappearance of interference, which improves detection efficiency. The WuRX is manufactured in 65nm LP process, consuming 7.56nW at a 0.4V power supply, with a sensitivity of −79dBm in the 433MHz ISM band. Under continuous wave (CW) interference, the receiver achieves a signal-to-interference ratio (SIR) of −31dB at a frequency offset of 1MHz.

Current LiDAR-Camera fusion methods for 3D object detection achieve considerable accuracy at the immense cost of computation and storage, posing challenges for the deployment at the edge. To address this issue, we propose a lightweight 3D object detection framework, namely TinyFusionDet. Specially, we put forward an ingenious Hybrid Scale Pillar Strategy in LiDAR point cloud feature extraction to efficiently improve the detection accuracy of small objects. Meanwhile, a low cost Cross-Modal Heatmap Attention module is presented to suppress background interference in image features for reducing false positives. Moreover, a Cross-Modal Feature Interaction module is designed to enhance the cross-modal information fusion among channels for further promoting the detection precision. Extensive experiments demonstrated that TinyFusionDet achieves competitive accuracy with the lowest memory consumption and inference latency, making it suitable for hardware constrained edge devices. Furthermore, TinyFusionDet is implemented on a customized FPGA-based prototype system, yielding a record high energy efficiency up to 114.97GOPS/W. To the best of our knowledge, this marks the first real-time LiDAR-Camera fusion detection framework for edge applications.

This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase-domain and voltage-domain hybrid calibration, the accumulated quantization error (Q-error) of the delta-sigma modulator (DSM) is compensated, and the locking problem caused by large sampling voltage fluctuation is solved. Meanwhile, a voltage shifting technique is introduced to adjust the locked voltage region of differential sampling PD (DSPD), which can improve the linearity of DSPLL for better calibration. Fabricated in 65-nm CMOS process, the presented DSPLL achieves measured integrated jitter of 69.09 and 73.26 fs for integer-N and fractional-N modes, respectively. The reference spur is −72.96 dBc, and the worst fractional spur is −55.26 dBc. The total power consumption is 19.2 mW at a 1.2-V supply, achieving a figure of merit jitter (FOMJ) of −249.9 dB.

Traditional wake-up receiver (WuRX) systems based on voltage-domain comparators for weak signal detection can readily suffer from false triggering due to noise. To address this issue, this work analyzes the mechanism of noise-induced failure in traditional voltage-domain comparator and proposes a time-domain comparator (TDCMP) scheme based on time-domain integration. By temporally integrating the input signal, the noise immunity of the comparator is significantly enhanced. To suppress process, supply voltage, and temperature (PVT) drift in the TDCMP, this work designs a frequency-locked loop (FLL) that employs a voltage-controlled oscillator (VCO) isomorphic to the TDCMP’s voltage-controlled delay line (VCDL) for drift calibration while simultaneously providing the clock signal for the WuRX. Implemented in a 65-nm CMOS process, the core chip area is 0.23 mm2, with a total system power consumption of 20.9 nW. The measurement results demonstrate that the proposed TDCMP enhances the WuRX sensitivity by 4 dB.

Electromagnetic interference (EMI) is an inevitable issue in power electronics applications. Although many kinds of solutions have been presented to attenuate EMI noise, there is still little research about the EMI suppression scheme utilized in multimode primary-side regulation (PSR) flyback converters. Targeting EMI regulation in multimode PSR flyback converter, a combo EMI suppression scheme comprised of frequency modulation and dual-slope gate driver is adopted to meet stringent EMI requirements, simplifying peripheral components and design of EMI filter. The proposed scheme is implemented in$0.18~\mu $m 5/40 V BCD process and occupies a die size (with pads) of$1.05\times 0.8$mm2. The experimental results show that the conducted EMI waveforms with line/neutral polarity can easily comply with regulations. The deviations of the output voltage are within ±1.3% under different inputs and loads while the peak effciency of 90% is achieved.

This article presents a low-power bandgap reference (BGR) featuring high power supply rejection ratio (PSRR) and fast start-up capability, operating across a wide supply voltage range of 1.3–5 V. A novel prebiased pulse current injection technique is proposed in the start-up circuit, achieving a 1% settling time of$50~\mu $s and a$25\times $speed gain during start-up. To enhance supply noise immunity, the proposed BGR employs a preregulated (PR)-based amplifier that effectively decouples the reference voltage from supply voltage fluctuations. Fabricated in a 0.18-$\mu $m BCD process, the proposed reference occupies an active area of 0.0394 mm2. Under a 5 V supply, the circuit generates a 1.2 V reference voltage while consuming only 48 nA quiescent current. Operating down to a minimum supply voltage of 1.3 V, it maintains a low power consumption of 57.2 nW at room temperature. The reference exhibits an average temperature coefficient (TC) of 5.95 ppm/°C across a wide temperature range ($- 40~^{\circ }$C to$125~^{\circ }$C) and achieves an outstanding line sensitivity (LS) of 0.00308%/V over the 1.3–5 V supply range. Furthermore, the measured PSRR reaches −85 dB at 100 Hz.

The power over Ethernet (PoE) technology has gained intensive attention in networking market owing to the advantages of compactness, flexibility, and cost in application. The automatic maintain power signature (MPS) function specified by IEEE standard extracts the periodic pulsed current to enable applications requiring low power modes. However, a large driving capacity is required due to a large MPS current above 10 mA, sacrificing a certain area. This brief proposes an adaptive MPS scheme, which reuses existing class regulator and delay timer to source a pulsed MPS current to meet the MPS requirements, saving an area of 0.0104 mm2. The proposed MPS scheme has been fabricated in 0.18-$\mu $m 120-V BCD process and the area is$1.37\times 1.00$mm2. The experimental results show that the proposed PoE interface draws a pulsed current with a period of 312 ms and 25.6% duty cycle to address the issue of MPS absence in very low-power standby modes.

A compact half-mode substrate-integrated waveguide (HMSIW) dual-band bandpass filter (BPF) is proposed based on the through silicon vias (TSVs) technology in this brief. The two pass bands of the filter operating at 14.02 and 21.46 GHz with the 3-dB fractional bandwidth (FBW) of 32.2% and 27.5% are constructed by the quasi-TEM and TE102 modes, respectively. 3-D-stacked inductors utilizing TSVs and redistribution layers (RDLs) are employed to induce mixed couplings, thereby generating a transmission zero (TZ) above the passband, which are analyzed by the equivalent circuit of the filter. The circuit size of the fabricated prototype of the dual-band HMSIW BPF is$0.18\lambda _{g}^{2}$. The in-band insertion losses (ILs) are 1.37 and 1.33 dB, severally. Measurement results agree well with the electromagnetic (EM) simulation results.

This brief presents an on-chip, real-time rotation calibration (RRC) technique aimed at alleviating the inter-channel offset mismatch in time-interleaved (TI) successive-approximation register analog-to-digital converter (SAR ADC). By leveraging auto-rotation calibration and self-compensation strategies in the analog domain, the proposed technique demonstrates robust performance across PVT variations. Two additional sub-channels are involved in the TI quantization mechanism, where the continuous rotation of the sampling clock distribution ensures their operation in calibration mode. To validate the effectiveness of the proposed calibration, an$8\times 8$bit 8 GS/s TI-SAR ADC is designed and implemented in a 28-nm process and occupies an active area of 0.273 mm2, with each sub-channel SAR ADC covering only$86\times 23~\mu $m. Extensive simulation results validate the efficacy of RRC, demonstrating significant improvements in dynamic performance. Specifically, SNDR increases from 37.1 to 45.4 dB, while SFDR rises from 57.8 to 60.7 dB, as observed at the Nyquist input frequency.

In this work, a comprehensive analysis and optimization method of electrical and thermal characteristics in 2.5-D integrated circuits (ICs) is performed, including rapid heat distribution modeling, integrated voltage regulator (IVR) chip modeling, and power delivery network (PDN) modeling. Based on the proposed method, chiplet placement, decoupling placement, and IVR parameter settings that compromise the total PDN impedance, IVR impedance, and thermal distribution characteristics can be obtained. First, a rapid thermal analysis method for multiple heat sources is proposed by integrating the equivalent thermal resistance method and commercial tools. The thermal method significantly improves the computational efficiency and reduces the memory usage. Then, we analyze the electrical characteristics of a typical low dropout (LDO) and model the complete 2.5-D PDN, including interposers, chiplets, IVRs, through-silicon vias (TSVs), bumps, decoupling capacitors, and other components. The electrical and thermal problems in the 2.5-D system are formulated and a Metropolis rule-based algorithm is used to derive optimal solutions. Finally, the optimal placement schemes and parameter settings are iterated under different constraints. This method allows for the adjustment of target impedance, noise current, thermal limit, and other constraints based on varying practical situations. In the time-domain analysis, it can be found that the capacitance value is reduced while maintaining the power supply performance. With high accuracy in thermal and electrical modeling, this work provides an in-depth reference for the co-design of chiplet-based 2.5-D ICs.

This brief presents a ping-pong continuous-time noise-shaping successive-approximation register (CT NS-SAR) analog-to-digital converter (ADC) architecture. Compared with the previous works, two ping-pong operation DACs are utilized to release the conversion time from 5% to 95% of the clock period, while ensuring the continuity of CT integration in the time domain, thus realizing the ideal noise transfer function (NTF) of the true CT-NS SAR. The DAC of each channel performs two roles of integration and conversion alternately, not only converting the signal in the current period but also bringing the generated residue voltage into the next period. Besides, the$G_{ {m}}$-OTA-Cintegrator replaces the open-loop$G_{ {m}}$-Cintegrator, where the OTA isolates the output parasitic capacitance, achieving an exact CT integration. The effective conversion bits are calculated by the bandwidth (BW) and the time of bit cycle, thus avoiding the redundant bits. Verified by postsimulation in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB over 20-MHz BW with an oversampling ratio (OSR) of 15. Under a 1.2-V supply voltage, the ADC consumes 2.3 mW and exhibits a Schreier figure of merit (FoM${}_{ {S}}$) of 170.2 dB.

Detailed routing is a crucial and time-consuming stage for ASIC design. As the number and complexity of design rules increase, it is challenging to achieve high solution quality and fast speed at the same time in detailed routing. In this work, a high performance detailed routing algorithm named IPAG with integer programming (IP) is proposed. The IP formulation uses the selection of candidate routes as decision variables. High quality candidate routes are generated by queue-based rip-up and reroute with adaptive global route guidance. A design rule checking engine which can simultaneously process nets with multiple routes is designed, to efficiently construct penalty parameters in the IP formulation. Experimental results on ISPD 2018 detailed routing benchmark show that IPAG achieves better solution quality in shorter or comparable runtime, as compared to the state-of-the-art academic detailed router.

This paper presents an integer-N sampling phase-locked loop (S-PLL) characterized by both low jitter and low spur. The design integrates a high-gain double-edge sampling phase detector (PD) and a self-retimed multi-modulus divider (MMD) aimed at mitigating the in-band noise. Furthermore, it features a compact implicit common-mode voltage-controlled oscillator (VCO) with a second harmonic tuning tailored for noise reduction. The proposed S-PLL, fabricated in a 28-nm CMOS technology, operates at 31 GHz with a 250-MHz reference. The measured RMS jitter is 39.69 fs integrated from 10 kHz to 100 MHz, with a reference spur of −63.2 dBc. The proposed PLL achieves a figure-of-merit (FoM) of −253.6 dB with a 28-mW power and a 0.047-mm2area.

Linearity testing, including differential nonlinearity (DNL) and integral nonlinearity (INL), is of great significance to evaluate the performance of an analog-to-digital converter (ADC). However, highly linear signal generator and large amount of samples are two challenges in conventional histogram testing method. This paper proposes a segmentation nonlinear model with partial polynomial fitting to reduce the required samples, while the source nonlinearity removal scheme relaxes the precision requirement of signal generator. The influence of noise and source resolution are analyzed. Measurement results show that with a 12-bit digital-to-analog converter (DAC) and 393 216 samples, the 16-bit ADC INL and DNL can be measured with estimation errors less than 0.3 LSB.

The utilization of modular chiplets in interposer-based 2.5-D heterogeneous systems simplifies fabrication and design, however, it also introduces significant noise challenges. This paper presents a collaborative jitter-aware optimization in 2.5-D integrated circuits (ICs), incorporating power supply induced jitter (PSIJ), system impedance, target impedance, and decoupling capacitors, based on the hybrid pre-computation and pre-storage/duplicate removal-non-dominated sorting differential evolution (PCPS/DR-NSDE) algorithm. An automatic channel model algorithm and a uniform decoupling capacitor placement strategy are proposed to improve the design efficiency. Then, the system transfer impedance, simultaneous switch current, sensitivity function, and amplification factor are individually modeled, leading to the assembly and verification of the final PSIJ in the 2.5-D system. A PCPS strategy is proposed to handle high-time-consuming modules in the objective function and a DR operation is added to improve algorithm performance. The proposed PCPS/DR-NSDE is faster than traditional algorithms and has optimal hypervolume and coverage-metric (C-metric) indicators. The procedures for further obtaining desired solutions in the Pareto front are discussed. The impact of practical constraints and target impedance is also analyzed. This work provides a collaborative optimization and analysis of jitter, noise, and impedance in 2.5-D systems.

This paper presents a digital background timing-skew calibration technique with high accuracy and bandwidth in time-interleaved (TI) analog-to-digital converters (ADCs). Compared with other calibration works, it features three highlights. Firstly, the proposed DCSD-based step-by-step and grouping calibration scheme can effectively improve the correction accuracy by minimizing the root mean square (RMS) value of the detected timing skews. Secondly, the linear compensation for a 13-taps FIR filter and the decimation-calibration-interpolation working pattern are used to expand the calibration effective bandwidth to the whole first Nyquist zone from different perspectives. Thirdly, the binary search is employed, instead of LMS algorithm, in order to meet the compensation requirement for FIR filter and improve the convergence speed and accuracy significantly in timing-skew detection. As a result, the proposed technique achieves the widest calibration bandwidth and higher accuracy compared to other fully digital calibration techniques while having the great convergence speed. Simulation model in MATLAB and FPGA-based hardware verification are employed to demonstrate its significant improvement on the performance and hardware overhead of the TI-ADCs. Finally, the proposed technique is employed in a 10-bit 2.5 GS/s 4-way TI-SAR ADC fabricated by standard CMOS 28nm process. The measurement results show that with the proposed technique, the SFDR and SNDR are improved by 18.9 and 17.9 dB at Nyquist frequency, respectively.

This paper introduces a dual main clock generator (DMCG) and a digital serializer (DS) to improve the power efficiency of the time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines a dual-path front end and an improved selecting signal generator that addresses the potential phase error and reduces the peak current of the clock-driving circuits by 60%. The DS is proposed to serialize the digital outputs without employing power-hungry inverter-based buffer chains thus reducing the power consumption by 39.2%. The reference-free time skew extraction algorithm (RFA) is presented to mitigate the accuracy deterioration due to selecting the fixed middle channel. These techniques are validated by a prototype 12-bit 10-GS/s TI pipelined successive approximation register (TI-Pi-SAR) ADC. Fabricated in a 28-nm CMOS process, the prototype chip occupies an area of 4.4 mm2. The measurement results show that the ADC achieves a 49.8 dB SNDR and 60.0 dB SFDR after calibration at Nyquist frequency, while the total power consumption is 270 mW, leading to the figure of merits of Schreier (FoM$_{\mathrm {S}}$) and Walden (FoM$_{\mathrm {W}}$) of 152.5 dB and 106.9 fJ/conv.-step, respectively.

This paper proposed a fully integrate single photon ranging system (ISPRS), which mainly consists of a laser pulse driver circuit with adaptive power adjustment, bias voltage generation circuit, 512 independently enabled single photon avalanche diodes (SPADs) used as Reference SPAD array and Return SPAD array respectively, two multi-event time-to-digital converters (TDCs) based on multi-phase sampling, and the ranging extraction circuit. The ranging extraction circuit mainly consists of nonlinear histogram, the FIR with adaptively coefficient adjustment algorithm, and receiving photon adaptive conditioning circuit. The nonlinear histogram is proposed to collect the distribution characteristics of the photons received by the Reference SPAD array and Return SPAD array, which can enhance the equivalent trigger probability of the SPAD array for laser echo. The coefficients of the FIR filter are obtained by normalizing the histogram collected by the Reference SPAD array. By adjusting the number of the enabled SPADs of Reference SPAD array, the envelope of the histogram collected by Reference SPAD array will be changed to match different measurement signal-to-background noise ratio (SBR) for Return SPAD array, which can improve the measurement precision of the ISPRS. The laser power meets the safety of the human eye while effectively improving the measurement range based on the proposed ranging extraction circuit and receiving photon adaptive conditioning circuit. The experimental results show that the measurement range and precision can reach 4.7 m and ±0.5 cm respectively of the ISPRS when the measurement rate is set 30 Hz.

This paper presents a reconfigurable 2.4/5-GHz dual-band power amplifier (PA) for WLAN 802.11ax application. The PA employs a series-combining transformer (SCT) in the output matching network to deliver high output power. To extract high passive efficiency of the output matching network both in the 2.4-and 5-GHz bands, a new efficiency-oriented design methodology of reconfigurable dual-band output matching network is proposed. Besides, the reconfigurable dual-band inter-stage matching network using power splitting structure is introduced. Based on the proposed methodology, the PA is designed and fabricated in 40-nm CMOS technology, and the passive efficiencies of the implemented output matching network are 70.3% and 73.8% at 2.4 and 5.5 GHz respectively. For continuous-wave, the proposed PA achieves a saturated power (P$_{\mathrm{sat}}$) of 25.4 and 24.4-24.8 dBm with power-added efficiency (PAE) of 25% and 20.8-27.3% in the 2.4-and 5-GHz WLAN bands, respectively. The proposed PA outperforms other reconfigurable dual-band or multi-band PAs in terms of the efficiency. When testing with 802.11ax signal with 1024-quadrature amplitude modulation (QAM), a -35-dB error vector magnitude (EVM) specification can be satisfied in the 2.4-and 5-GHz bands.

This article presents a fully dynamic switched-capacitor zoom ADC with 1st-order interstage leakage shaping (ILS). Noise shaping capability is integrated into the coarse stage by a low-cost error-feedback (EF) path, effectively mitigating quantization noise leakage in the traditional zoom architecture due to the non-unity STF. In addition, a swing-enhanced floating inverter amplifier (FIA) architecture is proposed for improved linearity as well as fully dynamic operations. The prototype ADC is fabricated in a 65-nm CMOS process and occupies an active area of 0.22 mm2. With a 1.2-V supply, it achieves 98.1-dB peak SNDR over a 20-kHz bandwidth with 142.8$\mu $W power consumption, resulting in a DR-based Schreier FoM of 182.9 dB and an SNDR-based FoM of 179.5 dB, respectively. According to the measurement results, 8$\times $power/BW configurability can be achieved by the zoom ADC while maintaining SNDR above 98 dB.

This article presents a background calibration method for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). The proposed algorithm employs fast adaptive particle swarm optimization (FAPSO) to detect the timing skews in sub-channels and compensates them using second-order finite impulse response (FIR) differentiators. This approach enables simultaneous convergence of each channel and reduces the convergence time significantly. Hardware implementation of the proposed timing skew calibration is synthesized by field-programmable gate array (FPGA), and it consumes a total power of 7.3 mW. The effectiveness of the proposed FAPSO algorithm is verified through a commercial 12-bit 3.6-GS/s 4-channel TI-ADC. After applying FAPSO timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved by 16.5 and 29.6 dB, respectively.

This paper presents a$G_{m}$-C integrator-implanted DC servo loop (GMCI2-DSL) and a bulk-driven ripple reduction loop (BD-RRL) for bio-potential readout analog-front-end (AFE) amplifier. The proposed bio-potential readout AFE amplifier employs the GMCI2-DSL and BD-RRL to achieve low noise and significant total harmonic distortion (THD) with small ripple amplitude. A prototype has been taped out using a 0.18-$\mu \text{m}$standard CMOS technology, and the core circuit occupies 880$\mu \text{m}\,\,\times $630$\mu \text{m}$. The mid-band gain is about 40 dB with a 1.3-V supply voltage, and the chip’s quiescent power is 10.8$\mu \text{W}$. The measured results show that the input-referred noise density is 26 nV/$\surd $Hz, and the input-referred integrated noise in the range from 0.5 Hz to 500 Hz is 0.93$\mu V_{rms}$. The measured THD of a 5-$\text{m}V_{pp}$input sinusoidal signal at 5.1 Hz is −64.3 dB without any input offset. The amplitude of residue ripple is achieved as 197.8$\mu \text{V}$around chopping frequency ($f_{ch}$) by ripple suppression. High-fidelity and real-time electrocardiogram (ECG) signals are acquired.

Reducing the power consumption of intelligence edge devices that require long standby periods is highly significant. The use of CMOS analog computing circuits for instant feature extraction and wake-up signal generation from the sensed signal has emerged as an efficient signal processing paradigm for data volume reduction and power minimization. This review highlights the progress of ultra-low-power (sub-$\mu $W) analog computing circuits for instant 1-dimensional audio signal processing in edge devices in recent years, at architecture and circuit levels. A comparative analysis of existing works is presented, offering choices that cater to various performance requirements. The low power consumption in the range of tens of nanowatts has been achieved. Finally, we provide insights into the future potential of these analog computing circuits.

The Vision Transformer (ViT) models have demonstrated excellent performance in computer vision tasks, but a large amount of computation and memory access for massive matrix multiplications lead to degraded hardware performance compared to convolutional neural network (CNN). In this paper, we propose a ViT accelerator with a novel “Weight-Loop” dataflow and its computing unit, for efficient matrix multiplication computation. By data partitioning and rearrangement, the number of memory accesses and the number of registers are greatly reduced, and the adder trees are eliminated. A computation pipeline with the proposed dataflow scheduling method is constructed to maintain a high utilization rate through zero bubble switching. Moreover, a novel accurate dual INT8 multiply-accumulate (DI8MAC) method for DSP optimization is introduced to eliminate the additional correction circuits by weight encoding. Verified in the Xilinx XCZU9EG FPGA, the proposed ViT accelerator achieves the lowest inference latencies of 3.91 ms and 13.98 ms for ViT-S and ViT-B, respectively. The throughput of the accelerator can reach up to 2330.2 GOPs with an energy efficiency of 109 GOPs/W, showing a significant improvement compared to the state-of-the-art works.

A highly linear input buffer is crucial for high-speed and high-resolution analog-to-digital converters (ADCs) since it isolates the kickback noise and package inductance. Several important factors affecting the linearity of the input buffer are analyzed in this brief, and a wideband input buffer with high linearity based on cascade complementary source follower (CCSF) is proposed. This cascaded input buffer is composed of a pMOS source follower (PSF) and an nMOS source follower (NSF). Compensation capacitor, assisted operational amplifier (opamp), bootstrapped-capacitor level-shifting circuit, current amplifier, and optimization strategies are utilized to extend the bandwidth and reduce distortion. Designed in a 65-nm CMOS, the CCSF input buffer achieves the spurious-free dynamic range (SFDR) and a signal-to-noise and distortion ratio (SNDR) of 76.6 and 58.1 dB with 1.9-GHz input frequency, respectively. It occupies 0.0155 mm$^2$and consumes 27 mW at 2.5 V.

文章提出一种应用于 X 频段和 Ku 频段卫星无线通信的带有滤波效应的新型宽带圆极化天线。该结构包含一个驱动层(同时也是滤波层)以及一个堆叠层(同时也是圆极化层)。带通滤波响应中的两个辐射零点,是衬底集成波导(SIW)腔体支持的开口与嵌入式驱动贴片的综合效果。引入倒角贴片作为堆叠元件,具有同时实现圆极化和拓宽工作带宽的能力。使用多层印制电路板(PCB)工艺制作了一个尺寸为 0.8λ0×0.71λ0×0.16λ0 的紧凑原型进行演示。实验结果与仿真结果吻合良好,测量的 −10-dB 阻抗带宽和 3-dB 轴比带宽分别为10.83% 和 15.54%。此外,还获得了 8.9 dBic 的左旋圆极化峰值增益,大于 7 dBic 的带内平均左旋圆极化增益,以及良好的频率选择性。

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with$16\times $linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm2. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoMw) is 24.4 fJ/conversion-step.

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR’s, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18-$\mu \text{m}$CMOS process, the prototype occupies 1.01 mm2. On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the bypass windows. It utilizes the time information of the MSB comparison to coarsely detect the input range without a dedicated timing budget. Based on the coarse detection results, the fine bypass window is configured by reusing the digital-to-analog converter (DAC) to accurately detect the input signal. Due to the presence of the coarse detection, the multi-window detection and its corresponding bypass operation are realized to maximize the effectiveness of the bypass window technique. In addition, the MSB-spilt switching scheme is proposed to reduce the DAC switch-back energy. A prototype 8-bit SAR ADC equipped with the proposed technique is fabricated in a 65-nm CMOS process. At a 350-MS/s sampling rate with a Nyquist input, the measured signal-to-noise-plus-distortion ratio (SNDR) and spurious-free dynamic ranges (SFDR) are 44.9 dB and 63.9 dB, respectively. At a supply voltage of 1.2 V, the ADC consumes power of 1.58 mW with the full-scale sinusoidal input signal. The ADC achieves an effective number of bits (ENOB) of 7.17 bit, resulting in a figure-of-merit (FoM) of 31.3 fJ/conversion-step. The ADC core occupies an active area of 0.0096 mm2.

An analog silicon photomultiplier (SiPM) based receiver with wideband transimpedance amplifier (TIA) is proposed for direct ToF LiDAR applications. The analog SiPM comprises a$16\times 32$single photon avalanche diodes (SPADs) array with a 25% fill factor. A fully differential pixel readout circuit is proposed within the pixel cell to facilitate the monolithic integration with the subsequent TIA and reduce the output capacitance of the analog SiPM. The TIA with the multipath feedforward compensation technique is proposed to improve the stability and achieve a wider −3-dB bandwidth. The adder array is used in this design to output the intensity information for the walk error compensation and the target identification. The proposed receiver, which is fabricated in$0.18~\mu \text{m}$HV-CMOS technology, achieves a −3-dB bandwidth of 420 MHz. A maximum detection range of 65 m is obtained with 20 W laser peak power,$1.8^{\circ }\times 1.8^{\circ }$field of view, and 40 mm aperture. A ranging accuracy of ±0.4 cm and precision of 4.5 cm are attained under a condition of 5 klux ambient light based on 1000 measurement results.

This article presents a single-loop third-order discrete-time delta-sigma modulator (DTDSM) with a 4-bit second-order noise shaping successive approximation register (NS SAR) quantizer. To realize an aggressive noise transfer function (NTF), a novel Finite Impulse Response (FIR) filter is embedded in the NS SAR. As employing a flipped voltage follower (FVF), which offers unity gain instead of an open loop dynamic amplifier, the proposed FIR filter is sharp and insensitive to process, voltage, and temperature (PVT) variation. Fabricated in a 65-nm 1P9M CMOS technology, the prototype DTDSM consumes$44 \mu \text{W}$when operating at a 1.2-V supply voltage and a sampling rate of 2.4 MS/s. It achieves a peak Schreier figure of merit (FoM) of 177.9 dB with a signal-to-noise and distortion-ratio (SNDR) of 91.3 dB at an oversampling ratio (OSR) of 64.

In this paper, a mutually synergistic hybrid energy harvesting (SHEH) circuit with both AC and DC energy harvesting capability is proposed. Within the proposed hybrid harvester, the vibration period of the piezoelectric transducer (PZT) is served as the switching signal for photovoltaic (PV) energy harvesting so that a dedicated clock generator is saved. Meanwhile, during the sampling phase, a small portion of the PV energy is injected into the PZT as an investment, which enhances the damping force and charge extraction of the PZT. Theoretically, the total synergistically extracted power from the proposed hybrid harvester is more than the sum of the power obtained from each transducer independently. The proposed SHEH circuit is fabricated with a 0.18-$\mu \text{m}$CMOS process. The buck-boost converter with zero-current switching control achieves a peak efficiency of 82.8%, and the maximum efficiency of piezoelectric energy harvesting can reach 4.5 times that of the full-bridge rectifier.

This article presents a constant voltage control scheme to improve the transfer efficiency and output voltage accuracy for single-stage AC-DC converters. The proposed scheme also has the advantage of low cost because of the simple application and few peripheral devices. To realize above features, the peak current and frequency curves with high efficiency are selected by analyzing the power losses of the applied topology. A voltage self-compensation circuit is designed to improve the output accuracy, especially the output voltage below 5V. Furthermore, a multi-stage startup circuit is also proposed to reduce the output voltage overshoot. To verify the feasibility of the proposed constant voltage control scheme, a BUCK controller adopting the proposed control scheme has been designed and fabricated with$0.18~\mu \text{m}$BCD process. Using the proposed controller, the peak efficiency of the prototype can reach as high as 66.9%, 78.9% and 82.8% under 115Vac input and 3.3V@300mA, 5V@300mA and 12V@300mA respectively. The load regulation is counted to be within ±1%.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, voltage control readout technique suffers from poor noise performance and low power efficiency (in terms of FoM). In this paper, the weak feedback oversampling successive approximation readout circuit which merges the closed-loop hybrid dynamic amplifier with noise reduction technique is proposed to achieve low noise floor, high power efficiency and high accuracy. The proposed WFB-OSA based readout circuit is fabricated in a commercial$0.18\mu \text{m}$1.8V CMOS process. The measurement result shows that the circuit has achieved a noise floor of$63\mu g/\surd Hz$and an FoM of 14pJ.

This brief presents an 8-bit two-step successive approximation register analog-to-digital converter (SAR ADC), where the interstage gain is embedded in the second-stage comparison to eliminate the dedicated residue amplifier and its timing cost. Combined with the passive residue transfer technique, the prototype ADC realizes high speed while requiring small overhead. Fabricated in 28-nm CMOS, it operates at 1.5 GS/s and achieves an signal-to-noise-and-distortion-ratio (SNDR) of 43.3 dB at Nyquist rate while consuming 2.32 mW, resulting in a Walden figure-of-merit (FOM) of 12.9 fJ/conv-step.

Enhancing the integration of directional couplers is a crucial challenge in the design of wireless communication circuits and systems. This article proposes a design strategy based on through-silicon via (TSV) insertion and neuro-transfer function (Neuro-TF) modeling to achieve miniaturization of coupled-line couplers. By embedding coupled TSV pairs inside the substrate, a planar coupler can be transformed into a 3-D structure with a smaller footprint. Furthermore, a design flow is proposed to achieve the initial parameters of TSV insertion for various application scenarios. Two insertion schemes with regular and coaxial TSVs are applied to handle different requirements and process constraints. The flow also estimates the number of required TSV pairs based on the area reduction target. To reduce dependence on electromagnetic (EM) simulation and make the strategy more widely applicable to various coupler types, Neuro-TF modeling is utilized for optimization after the initial design. Subsequently, the compatibility between the TSV insertion flow and the Neuro-TF method is analyzed to develop a comprehensive miniaturization strategy. The approach has been validated by two design cases through EM simulations. The results indicate that the proposed strategy enables rapid design and achieves area reduction targets effectively.

This brief proposes a time-domain second-order noise shaping analog-to-digital converter (ADC). It employs a voltage-to-time converter (VTC) in tandem with a second-order noise shaping time-to-digital converter (TDC), which realizes the goal of reducing the power consumption and accommodating different resolutions by configuring locations of poles of the transfer function. Note that the time-register constructed TDC, which performs the signal processing function in the time domain, is implemented with digital cells thoroughly. In this way, the proposed architecture can be more friendly to the increasingly scaled process. The reconfigurable architecture enables to obtain the target signal-to-noise-and-distortion ratio (SNDR) with decreased oversampling ratio (OSR), which improves energy efficiency relatively. In addition, compared with the conventional CMOS gated delay cell, the proposed single fan-out (SFO) gated delay cell is featured with lower power dissipation and shorter delaying time. The prototype is implemented in a 0.18-$\mu \text{m}$CMOS technology to demonstrate the validity of this proposed time-domain ADC. It achieves 64.5-, 56.1-, and 51.2-dB SNDR in 0.025-, 0.05-, and 0.1-MHz bandwidth on conditions of the OSR being 200, 100, and 50, respectively.

This brief presents a single-channel 8-bit 1.5-GS/s voltage–time (V-T) hybrid two-step analog-to-digital converter (ADC). Benefiting from the fine quantification in the time domain, the power-to-noise requirement of a comparator and speed limitation in the voltage domain have been significantly relaxed. An efficient cross-coupled linearized technique (CCLT) is proposed in a dynamic voltage-to-time converter (VTC) design as a crucial part of this ADC. This technique helps improve the total harmonic distortion (THD) of VTC by 8 dB across most process–voltage–temperature (PVT) variations by avoiding using a power-harvest current-source (CS)-based VTC. Moreover, a dynamic conversion strategy is proposed in a time quantizer to build a more power-efficient design. Fabricated in a 28-nm CMOS process, the prototype ADC consumes 3.3 mW at 1-V supply with an active area of 0.0035 mm2. With a Nyquist input, it achieves a signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 45.4 and 60.3 dB, respectively, yielding a Walden figure of merit (FoMW) of 14.4 fJ/conversion-step.

This article introduces a pulsed laser direct time-of-flight (dTOF) flash light detection and ranging (LiDAR) sensor fabricated in 0.18-$\mu \text{m}$HV CMOS technology. The chip includes$32\times 32$macro pixels and 1024 time-to-digital converters (TDCs). A noise filtering circuit with different threshold ($\text{N}_{\mathrm {th}}$) configuration is adopted in each macro pixel [formed by four single-photon avalanche diodes (SPADs)], which can suppress strong background light (BG) induced pile-up. To verify the imaging function and effectiveness of the noise filtering circuit, two systems are implemented (System1 for indoor imaging measurement and System2 for outdoor distance measurement). With the help of the noise filtering circuit and a reasonable signal-to-background noise ratio (SBR), the maximum detection range outdoors with reasonable accuracy can be greatly extended (from 12m @ Nth= 1 of System2 to more than 20m @ Nth= 2 of System2 under 70klux of background noise). The counter in the noise filtering circuit can be reused to get intensity information. A robust 13-bit TDC with a reliable reset is introduced. Thanks to a dedicated START/STOP logic and a Schmitt trigger, large TDC quantization errors can be avoided. It achieves a 200ps resolution (LSB) and exhibits an INLp-pof 3.55LSB and a DNLp-pof 0.53LSB. The maximum inter-frame rate can reach 270kfps with 16 IOs operating at speed of 500MHz. Combining 9k inter-frames to get one frame, a frame rate of 30 is achieved for an indoor 3-D imaging. For outdoor measurement, more laser pulses should be accumulated.

This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18-$\mu \text{m}$HV-CMOS technology in a 32$\times32$array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.

This article presents a 16-channel analog silicon photomultiplier (SiPM) with on-chip front-end for direct time-of-flight (D-ToF) LiDAR applications. The proposed receiver is mainly composed of 16-channel SiPM, variable gain amplifier (VGA) and time-to-digital converter (TDC). Each SiPM channel consists of 256 microcells, and their outputs are connected to a common output terminal in parallel. A novel active quenching circuit is adopted to reduce the long exponential tail in conventional SiPM and enable the capability of multi-echo detection. Current steering circuits are adopted within microcells to make the output current of SiPM immune to SPAD gain variations. The receiver was fabricated in 180-nm HV CMOS technology and integrated into the 16-line LiDAR prototype with optical components. Measurement results show that the sensor is capable of 20 m range imaging with 3 cm accuracy under 40 klux background light conditions. With the mechanical scanning system, a high-resolution image ($240\times16$) can be obtained.

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW,includingon-chip reference buffers.

A united-reference fractional counter (URFC) is proposed for multi-level time-to-digital converters (TDCs) used in direct time-of-flight (dToF) light detection and ranging (LiDAR) applications. The URFC combines the integer counter and the second-level interpolation in one functional block that derives both the integer part and the fractional part from the same synchronization result. Thus the proposed TDC has a more robust structure to deal with misalignment errors, and measurement results from different levels can be perfectly matched. High linearity and high precision can be guaranteed because of the united reference without calibration. The response time of the URFC decreases to hundreds of picoseconds, which makes it suitable for all output pulses from the avalanche photodiode. A TDC with the proposed URFC was implemented in 65nm standard CMOS technology with a detection range of$2.5~\mu \text{s}$($\sim 375\text{m}$) and a single shot precision of 27.63ps (~4.0mm). The power consumption is 51.4mW with a reference clock at 200MHz and a repetition rate at 999kHz. The INL and DNL are ±2.751 LSB and ±1.679 LSB, respectively.

To increase the light detection and ranging (LiDAR) system spatial resolution, the multiple photodetectors are typically deployed in the receiver. An equivalent linear-array receiver with multiplexing operation scheme is presented for the direct time of flight (dToF) LiDAR applications. In particular, the analog front-end (AFE) circuit of the proposed receiver mainly consists of eight transimpedance preamplifiers (preTIAs), a dummy preTIA, a post amplifier (PA) with an 8-to-1 multiplexer, an analog output buffer and a timing discriminator. The proposed AFE circuit, which achieves a transimpedance gain of ~106 dB$\Omega $, a bandwidth of ~220 MHz, an equivalent input-referred noise current of ~5.1 pA/Hz0.5 and a channel switchover time of 6 ns, was fabricated in a 65 nm standard CMOS technology. The associated DC power consumption is 137 mW with a power supply of 2.5 V. The total area of the proposed AFE circuit, which includes the circuit core, bias circuits and I/O PADs, is approximately equal to$1.2\times 1.2$mm2.

Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, the voltage control readout technique suffers from low dynamic range and low power efficiency (in terms of$\mathbf {FoM}$). In this paper, the voltage control ratiometric (VCR) readout technique is proposed to improve both dynamic range and power efficiency. The VCR readout technique is demonstrated in a readout circuit fabricated in a commercial 0.18$\mu {\mathrm{ m}}$1.8V/5.0V CMOS process. Compared to the traditional voltage readout circuit fabricated with the same CMOS process and tested with the same sensing element, the VCR readout circuit improves full input signal range by$\mathbf {3.5dB}$(from$\boldsymbol {\pm 8g}$to$\boldsymbol {\pm 12g}$) and the noise floor by$\mathbf {9.5dB}$(from$\mathrm {\mathbf {804~\mu g/}}\sqrt {\mathbf {Hz}} $to$\mathbf {270~\mu g/}\sqrt {\mathbf {Hz}} $). As a result, the dynamic range is improved by$\mathbf {13.0dB}$(from$\mathbf {44.0dB}$to$\mathbf {57.0dB}$), the$\mathbf {Fo}\mathbf {M}_{\mathbf {1}}$is improved from$\mathbf {310pJ}$to$\mathrm {\mathbf {83pJ }}$and the$\mathbf {Fo}\mathbf {M}_{\mathbf {2}}$is improved from$\mathbf {1977~\mu W\cdot \mu g/Hz}$to$\mathbf {796~\mu W\cdot \mu g/Hz}$.

This brief presents a digital background calibration technique for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). It updates the calibration step adaptively based on the detection error. This results in large update step initially, and it reduces with the calibration cycle going on. More than two times convergence time is saved compared with the conventional fixed update step method. Besides, by extending the compensation to second-order, both calibration range and accuracy are improved. To demonstrate the effectiveness of the proposed timing skew calibration, extensive simulation and measurement results are provided. It shows that after timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of a two-channel prototype TI ADC are improved by 8.2 and 14.9 dB, respectively.

An original concept of 3-D through-silicon via (TSV)-based Marchand baluns and its design methodology is proposed for on- chip and 3-D integration. By utilizing a 3-D packaging process that includes a TSV and redistribution layer (RDL), a meander coupling path is established and embedded in the vertical direction of the substrate for balun design. The 3-D structure can effectively reduce the on- chip area while maintaining good balance characteristics. Furthermore, the structure can be flexibly integrated with 3-D integrated circuits (3-D ICs) to realize signal conversion between different stacking tiers. An equivalent circuit model based on the TSV-to-TSV coupling channel and coupled transmission line has been established for initial estimation before electromagnetic (EM) optimization. To shorten the design cycle, a specific flow is proposed to meet the structural particularity and different application scenarios. To verify the design method and flow, a design case is analyzed and EM simulated with the antenna feeding network as the target application. The EM simulation results show that the design can work at 43–82 GHz with an amplitude imbalance of less than 0.3 dB and a phase imbalance of less than 1.3°, which meets the requirements of balanced feeding. It only costs a$0.084\,\,\lambda _{\text {g}}\,{\times }\,0.009\,\,\lambda _{\text {g}}$footprint, which is far lower than that of the conventional planar types.

A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expanding with conversion mode. The reconfigurable capacitor digital to analog converter (CDAC) is proposed to achieve multiple conversion modes without wasting capacitance. In 1-b/cycle conversion mode, the proposed ADC can achieve the sampling rate of 60-Ms/s and 9-b resolution. Based on the 2-b/cycle conversion mode, the proposed ADC can double the sampling rate and be reconfigured as a 120-MS/s, 8-b converter. Besides, the detection skip algorithm and charge sharing technology are involved to remove the precharge operation time and reduce the switching energy consumption. Moreover, the control logic is optimized to minimize the chip area and matches the reconfigurable characteristics well. A prototype ADC is fabricated in the 180-nm standard CMOS process, which achieves the 54.1-/46.7-dB signal-to-noise-plus-distortion ratio (SNDR) at 60-/120-MHz sampling frequency with the power consumption of 1.9/3.5 mW. The prototype ADC achieves a peak figure of merit (FoM) of 77-fJ/Conv.step at 2-b/cycle conversion mode. The ADC core occupies an active area of only 0.12 mm2.

An extended model of through-silicon via (TSV)-based solenoid inductor is proposed to save on-chip areas for 3-D radio frequency (RF) ICs and package integration. To achieve a high inductance density, the nested topology consists of high-density TSVs in high-resistivity silicon substrate and multilayers of metals in compatible CMOS process. Then, an analytical inductance model, considering the mutual inductance of TSVs and complicated metal traces, is established and verified. The inductance variation in physical dimensions is studied based on the modeled and simulated results of a TSV solenoid inductor in single tier. The proposed TSV solenoid typology gets better performance at inductance density and quality factor around some frequencies through analytical model and full-wave simulations. Further studies are directed toward RF application overview according to broadband and low power consumption.

In this brief, a fully digitized pulse generator with programmable pulse number and width is used as an ultrawideband (UWB) pulse transmitter with 17.7-dBm output power for see-through-wall (STW) radar. A fully differential operation broadband CMOS power amplifier (PA) with a power-switchable mode and fast settling time for pulse radar is presented, achieving excellent power consumption, considerable output power, and a -3-dB bandwidth from 3.6 to 6.6 GHz. The on-chip transformer is used for impedance transformation in the output and converting signals from the differential to single ended. Fabricated in a 65-nm standard CMOS process, the operating carrier frequency range of the transmitter covers 3.2-5.8 GHz and the pulsewidth can be adjusted from 0.75 to 1.2 ns. The number of pulses varies from 4 to 1. At 10-MHz pulse repetition frequency (PRF), the maximum peak-to-peak voltage of the transmitter output pulse reaches 3.8 V with 50-Ω load, and the corresponding pulsewidth is 0.75 ns. The equivalent power is 17.7-dBm after calibration, and the average power consumption is only 22.5 mW.

Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.

A dual-mode controlled dc-dc controller with power over Ethernet (PoE) interface for power device (PD) is presented that is designed to support drawing power either from an Ethernet cable or from an external auxiliary supply support (ASS). PoE interface supports all the functions that comply with the IEEE802.3af/at standard. Based on bandgap reference structure, a detection comparator is provided to detect input voltage without extra voltage reference. Using a low offset voltage amplifier, a lowloss current-limiting technique is proposed to achieve a high-precision current-limit point. Based on a high-speed comparator and two timing capacitors, an oscillator (OSC) is implemented for better accuracy, and provides the maximum duty cycle (Dmax) and external frequency synchronization. The chip is fabricated in a 0.5-μm 65 V BCD process and occupies a die size (with pads) of 1.79 × 2.76 mm2. The experimental results are measured for an active clamp forward converter with a wide range of dc input voltages from 33 to 57 V, an output voltage of 12 V, and an output power of 30 W. The chip achieves peak power efficiency of 90% and 90.63% on DC and ASS, respectively. The load regulation at different input voltages can be measured to be within ±0.11%. Measurements further show that the peak-to-peak ripple voltage of the chip is 161 mV and the recovery time is less than 1.2 ms for the 2-A load step.

In this brief, a 14-bit 500 MS/s current-steering digital-to-analog converter (DAC) is proposed, which applies the novel grouped random rotation thermometer code (GRTC) and the differential-quad switching (DQS) and has good dynamic performance without calibrations. The GRTC suppresses the harmonics caused by element mismatches, while the DQS reduces the input-code transition-dependent distortion to achieve a high spurious-free dynamic range (SFDR). A unit current cell with an intrinsic precision of 12 bits rather than 14 bits is used to reduce the active area, and the simple diagonal structure with a common-centroid layout is adopted to reduce the gradient error. The measured SFDR of the proposed DAC is more than 80 dBc below 35 MHz and better than 68 dBc over the entire Nyquist bandwidth. The power consumption of the DAC core is only 67.7 mW at 500 MS/s. The proposed DAC has been implemented in the Semiconductor Manufacturing International Corporation (SMIC) 0.18-μm CMOS process and occupies an active area of only 0.55 mm2.