Computation-in-Memory (CiM) is a promising solution to reduce the energy and latency caused by frequent data transfers between the processor and memory, a problem commonly referred to as the memory wall. For instance, comparing binary patterns to measure similarity is a common and challenging task in today’s emerging artificial intelligence applications. This can be implemented efficiently using Content Addressable Memory (CAM), which is well-suited for CiM-based acceleration of such tasks. To improve energy efficiency and performance, non-volatile memories (NVM) such as ReRAM (Redox-based RAM) can be utilized for the realization of CiMbased CAM. However, ReRAM is highly susceptible to process variations (PV), due to the immaturity of its process and inherent stochasticity. Moreover, the analog realization of CAM functionality using NVMs makes it more sensitive to these non-idealities. Conventional March tests, originally designed for memory fault detection, become ineffective in the presence of PV, which can alter ReCAM behavior and lead to test escapes. To address these challenges, this work systematically analyzes the impact of PV on ReCAM functionality. It proposes a generalized PV-aware March test that optimizes test patterns for both hard and PV-induced soft defects, achieving 100% defect coverage.

The demand for next-generation flexible electronics (FE) is rapidly increasing, especially in cost-sensitive consumer markets such as smart packaging, smart bandages, drug delivery systems, RFID tags, and wearable devices. Traditional silicon based electronics, constrained by high manufacturing costs and rigid form-factor, are inadequate for these emerging applications. However, the lack of rigid packaging in FE, combined with their complex and variable operating conditions, makes them more susceptible to thermal issues, therby leading to significant performance degradation, abnormal heating, and potential risks to device reliability and safety. To address these thermal challenges, we propose a novel approach to design thermal-resilient (TR) flexible analog neuromorphic circuits (f-NCs) based on amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). This cross-layer approach integrates TR circuit design for activation functions (AFs) and evolutionary algorithm (EA) based TR training using Neural Architecture Search (NAS) optimizing both the circuit-level thermal resilience and the architecture level training, ensuring robust performance of $\boldsymbol{f}$-NCs under varying thermal conditions. Experiments on 13 benchmark datasets demonstrate that thermal variations result in up to its $\mathbf{5 0. 3} \boldsymbol{\%}$ accuracy loss and the proposed evolutionary algorithm-based thermal-resilient training fully recovers this accuracy at the expense of $1.81 \times$ area and $1.39 \times$ power overhead.

Brain-inspired Hyperdimensional Computing (HDC) is emerging as a compelling paradigm for learning at the edge because of its one-shot learning capability, inherent scalability, and exceptionally low computational overhead. While HDC is robust to noise, soft and hard memory faults in the memory components of HDC accelerator can still significantly degrade accuracy. Conventional error correction codes (ECC) are commonly used to mitigate such faults, but their associated overhead make them impractical for resource-constrained edge devices. In this paper, we present a novel memory-free error correction technique to enhance the fault tolerance of HDC systems without requiring any dedicated memory to store check-bits. This way, not only is the memory overhead and its associated constraints eliminated, but also the possibility of errors occurring within the Error-Correcting Code (ECC) check-bits themselves is omitted. Additionally, the proposed method is highly scalable, with minimal hardware overhead, and is therefore suitable for edge implementations. We validate the approach on an FPGA, demonstrating its practicality and effectiveness. Compared to the state-of-the-art correction methods, our memory-free design achieves $27 \times$ lower LUT utilization, more than $80 \times$ fewer registers and no DSP, BRAM, or latency at all. At the same time, it is capable of preserving inference accuracy under a $\mathbf{1 2} \boldsymbol{\times}$ higher fault possibility.

Edge AI accelerators are a critical building block of numerous AI-driven applications deployed in resource-constrained environments such as IoT, automotive systems, and wearable devices. Hyperdimensional Computing (HDC) has recently emerged as a promising lightweight AI model for these edge scenarios, offering efficiency, simplicity, and inherent robustness against random computational faults. However, despite its advantages, the security implications of deploying HDC accelerators, particularly their resilience against targeted fault injection attacks, remain insufficiently explored. Such attacks pose tangible security risks, including intentional misclassification leading to denial-of-service or reliability degradation in critical decision-making systems. In this work, we precisely attack FPGA-based HDC accelerators using profiling and advanced voltage-level fault injection methods to evaluate their vulnerability. Our experiments reveal significant susceptibility during the critical similarity computation phase of the HDC inference pipeline, achieving targeted misclassification rates of up to ≈89%. To address these security vulnerabilities, we propose XOR masking and query hypervector randomization as practical, hardware-friendly countermeasures. Extensive real hardware evaluations confirm that these defenses substantially reduce misclassification rates to ≈2%, significantly enhancing the security and reliability of edge-deployed accelerators.

Flexible Electronics (FE) have emerged as a promising alternative to silicon-based technologies, offering on-demand low-cost fabrication, conformality, and sustainability. However, their large feature sizes severely limit integration density, imposing strict area and power constraints, thus prohibiting the realization of Machine Learning (ML) circuits, which can significantly enhance the capabilities of relevant near-sensor applications. Support Vector Machines (SVMs) offer high accuracy in such applications at relatively low computational complexity, satisfying FE technologies’ constraints. Existing SVM designs rely solely on linear or Radial Basis Function (RBF) kernels, forcing a trade-off between hardware costs and accuracy. Linear kernels, implemented digitally, minimize overhead but sacrifice performance, while the more accurate RBF kernels are prohibitively large in digital, and their analog realization contains inherent functional approximation. In this work, we propose the first mixed-kernel and mixed-signal SVM design in FE, which unifies the advantages of both implementations and balances the cost/accuracy trade-off. To that end, we introduce a co-optimization approach that trains our mixed-kernel SVMs and maps binary SVM classifiers to the appropriate kernel (linear/RBF) and domain (digital/analog), aiming to maximize accuracy whilst reducing the number of costly RBF classifiers. Our designs deliver 7.7% higher accuracy than state-of-the-art single-kernel linear SVMs, and reduce area and power by 108× and 17× on average compared to digital RBF implementations.

Printed electronics (PE) enable lightweight, flexible, and low-cost devices for the Internet of Things (IoT) and wearable applications. Compared to conventional silicon-based electronics, PE trades peak performance for advantages in cost efficiency, mechanical flexibility, and large-area fabrication. However, its manufacturing processes remain unreliable and are prone to structural defects and variation due to inherent limited control in additive manufacturing. Printed neuromorphic circuits (pNCs) leverage the benefits of PE for on-demand analog edge computation in target applications but remain vulnerable to such defects. Diagnostic testing is therefore essential not only for detection but also for localizing faults to specific subcircuits and regions in the layout, a step critical for guiding yield improvement and reducing the cost of downstream inspection. We propose a diagnostic test pattern generation (DTPG) framework for fault localization in pNCs under black-box access. While ATPG is typically formulated as an optimization problem for fault detection, our approach extends this formulation by explicitly optimizing for fault distinguishability. On ten UCI datasets, the framework achieves up to 20.7% higher diagnostic coverage with a reduction of up to 3.6 times the number of undetectable subcircuits than detection-only test sets, while constraining the number of patterns to reduce storage overhead. These results demonstrate effective fault localization and establish a foundation for finer-grained, component-level diagnosis in future work.

As Neural Networks (NNs) are increasingly deployed in safety-critical edge and datacenter systems, ensuring reliable execution becomes essential. Runtime faults such as memory bit flips and faults in logic components can silently corrupt computations without triggering system-level alarms. Conventional detection methods often miss logic faults or incur significant overhead. We propose a lightweight, concurrent error detection method that monitors voltage fluctuation traces captured by on-chip sensors. Our hypothesis is that faults alter neuron activations and change the switching activity and thus the instantaneous voltage fluctuation profile during inference. These traces are classified using a threshold-based model, requiring no modifications to the NN hardware or inference pipeline. As our approach operates purely through side-channel observation, it functions as a non-intrusive wrapper applicable to a wide range of AI accelerators. We evaluate the method on two different FPGAs, demonstrating consistent efficiency across platforms and portability to cloud scenarios. It detects faults in under a second, making it suitable for real-time applications such as vision tasks running at 30–60 FPS. By repurposing voltage sensors as diagnostic tools, this work opens a new direction for functional safety in AI hardware.

Spin-Transfer Torque MRAM (STT-MRAM) is gaining popularity as a leading non-volatile memory (NVM) for embedded, IoT, and automotive systems, owing to its low leakage, high endurance, and compatibility with CMOS processes. However, its magnetic nature and non-volatility feature introduce unique fault behaviors that differ fundamentally from conventional volatile memories such as SRAM and DRAM. In particular, faults injected during MRAM write operations may persist across power cycles, enabling attackers to exploit stable key corruptions. In this work, we present a persistent fault analysis (PFA) framework targeting AES implementations where the round-key schedule is stored in STT-MRAM. We demonstrate how carefully timed voltage glitches during MRAM write cycles can create reproducible, persistent bit flips that propagate through the AES key schedule. These persistent corruptions significantly reduce the ciphertext requirements for differential fault analysis (DFA) and enable statistical persistent fault analysis (SPFA) with only 12–17 faulty ciphertexts. These findings highlight that MRAM-based systems are exposed to a persistent-fault threat model different from transient faults in volatile memories, with direct implications for secure key storage and cryptographic implementations.

Artificial Intelligence (AI) has demonstrated strong capabilities across various domains over the past decade. Edge and specifically mission-critical applications, such as automotive and aerospace, require both high performance and efficiency without compromises in security and reliability. This stems from tightly constrained power consumption, failures that can have catastrophic consequences and devices that may be physically accessible to malicious actors. AI algorithm deployment to hardware also presents significant barriers, requiring specialized knowledge and expensive development tools. The DI-EDAI project aims to offer a holistic approach for connecting high-level AI algorithms with hardware implementations while tackling the aforementioned issues. Unlike other approaches that address individual aspects of the AI deployment flow, we investigate solutions across multiple layers of the design stack. Through our work we develop efficient hardware, map AI algorithms to hardware while simultaneously ensuring security and reliability. Furthermore, we leverage AI-techniques to assist with Electronic Design Automation (EDA) workflows for design optimization, verification and implementation. Our open source approach aims to reduce entry barriers, promote transparency and education, and spark innovation. This paper presents the current state of the DI-EDAI project at midterm, highlighting our latest contributions, identifying limitations in existing state-of-the-art approaches, and outlining ongoing work to address these gaps.

Flexible electronics offer unique advantages for conformable, lightweight, and disposable healthcare wearables. However, their limited gate count, large feature sizes, and high static power consumption make on-body machine learning classification highly challenging. While existing bendable RISC-V systems provide compact solutions, they lack the energy efficiency required. We present a mechanically flexible RISC-V that integrates a bespoke multiply-accumulate co-processor with fixed coefficients to maximize energy efficiency and minimize latency. Our approach formulates a constrained programming problem to jointly determine co-processor constants and optimally map Multi-Layer Perceptron (MLP) inference operations, enabling compact, model-specific hardware by leveraging the low fabrication and non-recurring engineering costs of flexible technologies. Post-layout results demonstrate near-real-time performance across several healthcare datasets, with our circuits operating within the power budget of existing flexible batteries and occupying only 2.42mm2, offering a promising path toward accessible, sustainable, and conformable healthcare wearables. Our microprocessors achieve an average 2.35x speedup and 2.15x lower energy consumption compared to the state of the art.

Flexible electronics (FE) based on indium gallium zinc oxide thin-film transistors (IGZO-TFTs) are emerging for ultra-low-power wearable applications. However, lack of packaging, limited pins, and high device variability make conventional Automatic Test Equipment (ATE) impractical for testing analog/mixed-signal circuits in FE. This work presents a dual-purpose ring oscillator (RO) and voltage-controlled oscillator (VCO) serving as functional timing blocks and core structures for a distributed delay-based BIST framework. The oscillators achieve 1100x area reduction and 5600x lower power than previous IGZO-TFT designs. Lightweight digital BIST embedded within each RO stage enables stage-wise delay monitoring for defect detection. The BIST achieves 93% defect coverage for individual defects and 88% for multiple simultaneous defects, with only 3% power overhead

Uncertainty estimation in Neural Networks (NNs) is vital in improving reliability and confidence in predictions, particularly in safety-critical applications. Bayesian Neural Networks (BayNNs) with Dropout as an approximation offer a systematic approach to quantifying uncertainty, but they inherently suffer from high hardware overhead in terms of power, memory, and computation. Thus, the applicability of BayNNs to edge devices with limited resources or to high-performance applications is challenging. Some of the inherent costs of BayNNs can be reduced by accelerating them in hardware on a Computation-In-Memory (CIM) architecture with spintronic memories and binarizing their parameters. However, numerous stochastic units are required to implement conventional Dropout-based BayNN. In this paper, we propose the Scale Dropout, a novel regularization technique for Binary Neural Networks (BNNs), and Monte Carlo-Scale Dropout (MC-Scale Dropout)-based BayNNs for efficient uncertainty estimation. Our approach requires only one stochastic unit for the entire model, irrespective of the model size, leading to a highly scalable Bayesian NN. Furthermore, we introduce a novel Spintronic memory-based CIM architecture for the proposed BayNN that achieves more than 100× energy savings compared to the state-of-the-art. We validated our method to show up to 1% improvement in predictive performance and superior uncertainty estimates compared to related works.

Flexible Electronics (FE) offer distinct advantages, including mechanical flexibility and low process temperatures, enabling extremely low-cost production. To address the demands of applications such as smart sensors and wearables, flexible devices must be small and operate at low supply voltages. Additionally, target applications often require classifiers to operate directly on analog sensory input, necessitating the use of Analog to Digital Converters (ADCs) to process the sensory data. However, ADCs present serious challenges, particularly in terms of high area and power consumption, especially when considering stringent area and energy budget. In this work, we target common classifiers in this domain such as MLPs and SVMs and present a holistic approach to mitigate the elevated overhead of analog to digital interfacing in FE. First, we propose a novel design for Binary Search ADC that reduces area overhead 2× compared with the state-of-the-art Binary design and up to 5.4× compared with Flash ADC. Next, we present an in-training ADC optimization in which we keep the bare-minimum representations required and simplifying ADCs by removing unnecessary components. Our in-training optimization further reduces on average the area in terms of transistor count of the required ADCs by 5× for less than 1% accuracy loss.

For AI hardware, functional safety is crucial, especially for neural network (NN) accelerators used in safety-critical systems. A key requirement for maintaining this safety is the precise detection of out-of-distribution (OOD) instances, which are inputs significantly distinct from the training data. Neglecting to integrate robust OOD detection may result in possible safety hazards, diminished performance, and inaccurate decision-making within NN applications. Existing methods for OOD detection have been explored for full-precision models. However, the evaluation of methods on quantized neural network (QNN), which are often deployed on hardware accelerators such as FPGAs, and on-device hardware realization of concurrent OOD detection (COD) is missing in literature. In this paper, we provide a novel approach to OOD detection for NN FPGA accelerators using power measurements. Utilizing the power side-channel through digital voltage sensors allows on-device OOD detection in a non-intrusive and concurrent manner, without relying on explicit labels or modifications to the underlying NN. Furthermore, our method allows OOD detection before the inference finishes. Additionally to the evaluation, we provide an efficient hardware implementation of COD on an actual FPGA.

Super-TinyML aims to optimize machine learning models for deployment on ultra-low-power application domains such as wearable technologies and implants. Such domains also require conformality, flexibility, and non-toxicity which traditional silicon-based systems cannot fulfill. Printed Electronics (PE) offers not only these characteristics, but also cost-effective and on-demand fabrication. However, Neural Networks (NN) with hundreds of features ---often necessary for target applications--- have not been feasible in PE because of its restrictions such as limited device count due to its large feature sizes. In contrast to the state of the art using fully parallel architectures and limited to smaller classifiers, in this work we implement a super-TinyML architecture for bespoke (application-specific) NNs that surpasses the previous limits of state of the art and enables NNs with large number of parameters. With the introduction of super-TinyML into PE technology, we address the area and power limitations through resource sharing with multi-cycle operation and neuron approximation. This enables, for the first time, the implementation of NNs with up to 35.9× more features and 65.4× more coefficients than the state of the art solutions.

Brain-inspired architectures are increasingly favored for edge devices due to their efficient execution of cognitive tasks with limited energy and computational resources. A promising approach in this field is Hyper-Dimensional Computing (HDC), known for its robustness against noise and simple computational operations, despite being constrained by memory bandwidth. HDC is well-suited for computation in memory (CiM) using emerging resistive memory technologies. However, security concerns arise from potential attack vectors in HDC, spanning from computational algorithms to the underlying technology. Since HDC relies on unique data patterns, or class hypervectors, stored in memory, there is a risk of undetected data manipulation or poisoning. We demonstrate that power information from insensitive (public) outputs can expose secret data stored in memories. This study investigates side-channel vulnerabilities in Content Addressable Memory (CAM)-HDC implemented with resistive memory-based CiM. We develop a collision attack using side-channel information to recover predicted classes from all possible outputs accurately. Our findings highlight a security threat in HDC even with parallel computation between query and class hypervectors. To address this vulnerability, we propose an effective countermeasure based on a hiding technique for CiM implementation, mitigating the identified security risks.

Computation-in-Memory (CIM) has emerged as a promising solution to the memory bottleneck in data-intensive applications and AI accelerators; however, it introduces new testing challenges due to multi-row access patterns and higher sensitivity to variations. These challenges can cause marginal bitcells to fail under CIM operation even if they pass standard March tests, making existing approaches insufficient for ensuring reliable CIM operation. In this work, we propose March-CIM, a modified March test optimized for SRAM-based CIM, which overcomes this limitation. By using read current profiling and a trim-assisted sensing mechanism, our method identifies marginal bitcells that conventional tests miss and selectively subjects them to exhaustive CIM testing to verify their fault-free functionality. This method significantly reduces test time (and thus test cost) by eliminating unnecessary tests for the bitcells with reliable performance. We demonstrate the effectiveness of our CIM test approach using 22 nm FDSOI technology and confirm its compatibility with industrial memory built-in self-test (MBIST) tools with minor modifications, achieving a reduction of up to 67% in test time compared to exhaustive CIM testing. Our method is applicable for field testing to ensure reliable operation through periodically profiling bitcell behavior through MBIST under real-time infield conditions.

Memristor-based computation-in-memory (CiM) architectures address the growing computational demands of AI accelerators by enabling analog matrix-vector multiplication (MVM) directly within the memory array. Passive (selectorless) memristive crossbars are particularly attractive for such architectures due to their high density and compatibility with back-end-of-line fabrication. Here, AI model parameters are stored as memristor conductances, and MVM is performed in situ by activating multiple rows simultaneously and sensing the resulting column currents. As a result, column currents become the primary observable, making column-level fault detection more relevant for AI workloads than conventional March-based cell-level tests, which are specially time - and energy-intensive for passive crossbars due to specialized biasing methods. To address this, we propose a current-based testing methodology tailored to passive crossbars that detects and diagnoses faulty columns while accounting for non-idealities such as sneak-path currents, line resistance, and process variations. Faulty columns are detected by programming all cells to a uniform state and measuring column-current deviations, followed by targeted test patterns to estimate per-column fault density. On a $64 \times 64$ array, the proposed approach achieves 100% faulty column detection, 98% overall fault coverage, and a $2.3 \times$ speed-up in test time compared to conventional March tests. Hence, providing a fast and efficient solution for manufacturing screening of passive crossbars with sufficient diagnostic resolution to support systemlevel fault tolerance for AI applications.

Chip technologies are crucial for the digital transformation of industry and society. Machine Learning (ML) and Artificial Intelligence (AI) are increasingly shaping both daily life and industrial applications, with AI hardware playing a vital role in enabling efficient and scalable ML deployment. However, significant challenges remain in bridging the gap between ML algorithm development and hardware implementation, particularly for edge ML applications where efficiency, power constraints, and adaptability are critical. In such resource-constrained environments, hardware-software co-design becomes essential to achieve the necessary trade-offs between performance, energy efficiency, and system responsiveness. One of the key bottlenecks in ML hardware development is the lack of seamless integration between ML toolchains and electronic design automation (EDA) tools for hardware synthesis and mapping. Current solutions often require extensive manual optimization and costly proprietary software, limiting accessibility and innovation. Open-source tools can play a transformative role in democratizing ML hardware design, fostering collaboration, and addressing the growing shortage of skilled professionals. This paper covers key aspects of hardware-software co-design for ML systems, such as ML algorithms, hardware design, compiler technologies and system security, with a focus on open-source solutions. We highlight the critical need for open-source toolchains that connect ML model development with hardware synthesis and optimization and present solutions for custom hardware, as well as FPGA accelerators.

With the rising demand for ultra-low-cost and flexible electronics in applications like smart packaging and wearable health monitoring, printed electronics provide an affordable, adaptable, and customizable alternative to conventional silicon. However, these systems often rely on printed batteries or energy harvesters with limited power capacity, making strict power budgets critical. Printed neuromorphic circuits (pNCs) are promising for their analog signal processing, reduced circuit complexity, and energy efficiency in low-power environments. Nonetheless, maintaining robust performance under strict power constraints remains challenging, necessitating advanced optimization techniques. In this work, we propose an augmented Lagrangian approach to enforce task-specific power constraints in pNCs, validated across 13 benchmark datasets. Our method preserves accuracy within strict power budgets while achieving Pareto-optimal power-accuracy trade-offs in a single training run. In contrast, the penalty-based method, which serves as the baseline, requires up to 150 runs per dataset to generate the Pareto front. For low-power scenarios ($\approx 20 \%$ of the original power), our method demonstrates a $52 \times$ improvement in accuracy-to-power ratio over the baseline. At higher power budgets $(\approx 80 \%$ of the original power), it achieves a $59 \times$ improvement, maintaining competitive performance. Experimental results demonstrate that our approach achieves $\mathbf{8 1. 8 2 \%}$ accuracy with p-tanh activation function (AF) at high power budgets and excels with p-Clipped_ReLU AF under low power constraints. This highlights the computational efficiency and effectiveness of our approach for power-constrained circuit design.

The rise of the Internet of Things demands flexible, biocompatible, and cost-effective devices. Printed electronics provide a solution through low-cost and on-demand additive manufacturing on flexible substrates, making them ideal for IoT applications. However, variations in additive manufacturing processes pose challenges for reliable circuit fabrication. Adapting neuromorphic computing to printed electronics could address these issues. Printed neuromorphic circuits offer robust computational capabilities for near-sensor processing in IoT. One limitation of existing printed neuromorphic circuits is their inability to process temporal sensory inputs. To address this, integrating temporal components in printed neuromorphic circuit architectures enables the effective processing of time-series sensory data. Printed neuromorphic circuits face challenges from manufacturing variations such as ink dispersion, sensor noise, and temporal fluctuations, especially when processing temporal data and using time-dependent components like capacitors. To mitigate these challenges, we propose robustness-aware temporal processing neuromorphic circuits with low-pass second-order learnable filters (SO-LF). This approach integrates variation awareness by considering the variation potential of component values during training and using data augmentation to enhance adaptability against physical and sensor data variations. Simulations on 15 benchmark time-series datasets show our circuit effectively handles noisy temporal information under 10% process variations, achieving an average accuracy and power improvement of ≈24.7% and ≈91% respectively compared to models lacking variation with ≈1.9×more devices.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing memory technologies. However, STT-MRAM faces reliability challenges, primarily due to stochastic switching, process variation, and manufacturing defects. These reliability challenges become even worse due to interconnect parasitic resistive-capacitive effects, potentially compromising the reliability of memory cells located far from the write driver. This can severely impair the manu-facturing yield and large-scale industrial adoption. Toaddressthis, we propose an interconnect-aware error correction coding (InterA-ECC), which provides non-uniform error correction to a different zone of the memory subarray. The proposed InterA-ECC strategy selectively applies robust error-correction code (ECC) to specific rows within the subarray rather than uniformly across all rows, reducing ECC parity bits while enhancing bit error rate resiliency in the most vulnerable memory zone.

Chip technologies are crucial for the digital transformation of industry and society. Artificial Intelligence (AI) is playing an increasingly important role in both our daily lives and in industry. The development of advanced AI chip designs, essential for the successful deployment of AI, is of critical importance for innovation and competitiveness. However, challenges arise from the complexity of hardware development, expensive access to state-of-the-art design tools, and a global shortage of hardware experts. In addition to cost optimization, computational power, and energy consumption, security and trustworthiness are becoming increasingly important. This project aims to address these challenges in AI chip design by enabling efficient hardware development. We are developing a seamless transition between software-based AI model development and optimization, and efficient hardware implementation, while considering security, trustworthiness, and energy efficiency. An open-source approach plays a key role, facilitating access for small and medium-sized enterprises (SMEs) and expanding the community involved in AI chip design to help mitigate the shortage of skilled professionals.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

FPGAs, with their parallelism, low power consumption, and reconfigurability, offer an ideal solution for accelerating quantized deep neural networks (qDNNs) on resource-constrained edge devices. They enable enhanced latency, reduced energy consumption, and improved computational efficiency. However, existing frameworks to accelerate qDNN inference on FPGA face challenges in fine-tuning the deployed models on the FPGAs, as expensive re-synthesis and re-mapping of the accelerator is required. Additionally, the folding algorithm for DNN compute engines in these frameworks introduces substantial padding overheads to align with memory widths. This paper introduces a novel evolutionary algorithm-based hardware-in-the-loop (EvoHIL) framework. EvoHIL uses hardware-level weight bit-flip operations to activate neurons and improve accelerator accuracy without requiring DNN re-training and rebuilding the entire accelerator. We also propose a novel algorithmic optimization (Aopt) for folding across DNN accelerator layers. Aopt optimally aligns folding factors with memory width, eliminating excessive padding overheads and improving throughput while reducing memory and resource utilization. Experimental results demonstrate the effectiveness of these solutions. EvoHIL optimization enhanced the accuracy of a binarized convolutional neural network (BCNN) accelerator to nearly 86%. Aopt delivered significant improvements, including up to 96.77 % padding overhead reduction, 33.2 % increased throughput, and 25 % reduced runtime compared to FINN.

We propose to revisit the functional scaling paradigm by capitalizing on two recent developments in advanced chip manufacturing, namely 3D wafer bonding and backside processing. This approach leads to the proposal of the CMOS 2.0 platform. The main idea is to shift the CMOS roadmap from geometric scaling to fine-grain heterogeneous 3D stacking of specialized active device layers to achieve the ultimate Power-Performance-Area and Cost gains expected from future technology generations. However, the efficient utilization of such a platform requires devising architectures that can optimally map onto this technology, as well as the EDA infrastructure that supports it. We also discuss reliability concerns and eventual mitigation approaches. This paper provides pointers into the major disruptions we expect in the design of systems in CMOS 2.0 moving forward.

Over the past decade, AI has been rapidly integrated into our daily life, coming in every shape and size and working across systems from big clouds to IoT. As a result, AI systems are increasingly requiring enhancements in model efficiency, hardware acceleration, and memory systems to satisfy stringent constraints on efficiency, reliability, and security. However, advancing across these fronts is challenging as compute demand outpaces Moore’s-law efficiency, hardening into an AI compute wall and an AI energy wall. Breaking through requires a unified AI co-design loop that co-optimizes algorithms and hardware, including efficient AI-to-hardware mapping, so that ongoing goals (accuracy, sparsity, latency) align with concrete hardware choices (precision modes, interconnects, memory hierarchies) and AI-specific execution and memory-reuse patterns. This paper details the principal co-design challenges, presents complementary strategies, and outlines a practical roadmap toward highly optimized, efficient, reliable, and secure AI systems.

Biologically-inspired Spiking Neural Networks (SNNs) have emerged as a promising avenue toward energy-efficient neuromorphic computing, particularly in edge applications such as soft robotics, wearable health monitors, and IoT devices. Printed Electronics (PE), offering advantages of ultra-low cost fabrication and mechanical flexibility, present a viable platform to realize such neuromorphic systems at scale. However, designing adaptable and efficient spiking circuits that meet the unique constraints of PE applications remains a challenge. To address this, we propose a novel analog spiking neuromorphic circuit with a learnable spike generator (LSG). Unlike fixed-threshold models, our generator adapts spike timing dynamics during training, enabling better task-specific performance. To optimize for ultra-low power consumption on resource-constrained platforms, we further introduce a robustness-aware training framework that further minimizes the energy consumption adaptively. Simulation results across 13 benchmarks demonstrate an average 57.6% power reduction for the LSG while improving the average classification accuracy by 8%, area and energy reduction by 89% and 28.7% respectively compared to the state-of-the-art printed analog spiking neural networks (P-SNNs).

The rapid advancement of flexible electronics (FE) has driven significant innovation across diverse sectors, including healthcare, wearables, smart packaging, and IoT devices, owing to their adaptability, lightweight form factor, and cost-effectiveness compared to traditional silicon-based electronics. A key computing paradigm in this domain is bespoke classifiers, where model parameters are hardcoded in neuromorphic hardware to meet strict area, power, and cost constraints. By tailoring bespoke hardware to specific tasks, these circuits achieve significant accuracy under tight resource budgets but also introduce distinct security vulnerabilities. The intrinsic flexibility of substrates, unconventional manufacturing processes, and limited protective packaging make such systems particularly vulnerable to security threats, with side-channel attacks (SCAs) being a critical concern. In this work, we systematically investigate SCA vulnerabilities in bespoke TFT-based multilayer perceptron (MLP) classifiers, considering both analog (flexible analog multilayer perceptron (f-AMLP)) and digital (flexible digital multilayer perceptron (f-DMLP)) realizations. For digital classifiers, we apply correlation power analysis (CPA), leveraging well-established leakage models from silicon-based systems. For analog classifiers, where leakage is continuous, nonlinear, and strongly influenced by device-level variability, we develop a tailored convolutional neural network (CNN)-based regression attack capable of extracting inputs from noisy power traces. Experimental results across benchmark datasets show that f-DMLPs can be compromised with 70–85% cumulative attack success rate (ASR) after ≈ 4k–5k traces using CPA, while f-AMLPs, though slower to attack initially, reach up to 90–95% ASR after ≈ 8k–9k traces with CNN-based approach.

Hyperdimensional Computing (HDC) has emerged as a promising lightweight machine learning approach suitable for edge and Internet-of-Things (IoT) applications due to its inherent energy efficiency and robustness in noisy environments. Despite these advantages, recent research has shown that FPGA-based HDC accelerators are susceptible to model inversion and physical attacks. In this paper, we propose a specialized Convolutional Neural Network (CNN)-based side-channel analysis (SCA) designed to extract stored hypervector bits from FPGA-implemented HDC models. After identifying the location of CNN-extracted leakages, we introduce an adaptive Gradient-weighted Class Activation Mapping (Grad-CAM)-guided approach to achieve much more effective attack results. This adaptive technique iteratively highlights critical leakage regions, enabling a targeted and efficient improvement of the signal-to-noise ratio (SNR), accelerating the attack by rapidly narrowing down essential leakage intervals. Using approximately one million power traces obtained from a dedicated ChipWhisperer Pro measurement setup during HDC inference, our adaptive CNN-based method achieves a bit extraction accuracy of up to 93%, reaching nearly 2× the accuracy of the non-adaptive baseline with half as many traces, and ultimately providing 1.7× higher maximum bit extraction accuracy. We further analyze the robustness of the identified leakages across multiple FPGA architectures under different noise conditions. To counteract these vulnerabilities, we introduce a dynamic masking scheme that effectively reduces CNN bit extraction accuracy to ≈ 18%, with minimal overhead on FPGA resources (around 1.6× increase in LUT usage and 1.4× increase in latency). Furthermore, we validate the effectiveness of our protection scheme through a higher order test vector leakage assessment (TVLA), confirming a significantly reduced leakage with a t-value of ≈ 2.2.

Flexible Electronics (FE) offer a promising alternative to rigid silicon-based hardware for wearable healthcare devices, enabling lightweight, conformable, and low-cost systems. However, their limited integration density and large feature sizes impose strict area and power constraints, making ML-based healthcare systems–integrating analog frontend, feature extraction and classifier–particularly challenging. Existing FE solutions often neglect potential system-wide solutions and focus on the classifier, overlooking the substantial hardware cost of feature extraction and Analog-to-Digital Converters (ADCs)–both major contributors to area and power consumption. In this work, we present a holistic mixed-signal feature-to-classifier co-design framework for flexible smart wearable systems. To the best of our knowledge, we design the first analog feature extractors in FE, significantly reducing feature extraction cost. We further propose an hardware-aware NAS-inspired feature selection strategy within ML training, enabling efficient, application-specific designs. Our evaluation on healthcare benchmarks shows our approach delivers highly accurate, ultra-area-efficient flexible systems–ideal for disposable, low-power wearable monitoring.

Content Addressable Memory enables high-speed binary pattern matching and is widely used in various applications. Exploiting Resistive Random Access Memory (ReRAM) for CAM (ReCAM) realization offers advantages in terms of non-volatility, high density, and low power consumption using the Computation in Memory (CiM) concept. However, the unique defects of ReRAM combined with CMOS fabrication defects, introduce new faulty behaviors that complicate detection and diagnosis, thereby increasing the risk of test escapes and field failures. However, diagnosing faulty cells in ReCAM is crucial for analyzing failure mode, which helps improve manufacturing yield. It also promotes defect and fault tolerance both post-manufacturing and during runtime. Pinpointing faulty cells within the ReCAM array is particularly challenging, especially when all cells are connected to the same match-line (ML). Diagnosis also plays a critical role at runtime by enabling fault tolerance through mechanisms such as bypassing defective cells. This paper proposes a novel Design-for-Testability (DfT) approach for ReCAM diagnosis that utilizes infinitesimal voltage differences to identify the location of faulty cells. The proposed DfT circuitry and the accompanied diagnosis flow enhance diagnostic precision by enabling adjustable gain and sampling time in a multi-step process, effectively identifying faulty cells within the array. The simulation results of two distinct fault scenarios, applied to the binary patterns of all-match and all-mismatch conditions, demonstrate the effectiveness of the proposed DfT technique in achieving fine-grained fault detection across the ReCAM array. Furthermore, using this approach reduces the time complexity by more than half compared to the March-based approach with negligible overhead in area and power.

HyperDimensional Computing (HDC) is a brain-inspired machine learning (ML) approach for cognitive tasks, where input data is transformed and encoded as high dimensional hypervectors and are then compared to aggregated class hypervec-tors for classification. Due to its computationally lightweight operations and noise resilience, it is well suited for resource-constrained edge Artificial Intelligence (AI). A well-known problem in ML tasks is dealing with inputs that are significantly different from the training and test data, which is referred to as Out-of-Distribution (OOD) inputs. When AI models are faced with such inputs, they behave incorrectly which can lead to safety violations, when they are deployed in safety-critical applications. Therefore, detecting OOD inputs is essential for maintaining the functional safety of machine learning accelerators in practice. In this work, we propose an extremely lightweight concurrent OOD detection mechanism in HDC hardware accelerators. Our results not only demonstrate higher OOD detection compared to other state of the arts but also requires no retraining, minimal hardware overhead (2 LUT, 1 Register), and does not introduce additional latency.

Conventional stress monitoring relies on episodic, symptom-focused interventions, missing the need for continuous, accessible, and cost-efficient solutions. State-of-the-art approaches use rigid, silicon-based wearables, which, though capable of multitasking, are not optimized for lightweight, flexible wear, limiting their practicality for continuous monitoring. In contrast, flexible electronics (FE) offer flexibility and low manufacturing costs, enabling real-time stress monitoring circuits. However, implementing complex circuits like machine learning (ML) classifiers in FE is challenging due to integration and power constraints. Previous research has explored flexible biosensors and ADCs, but classifier design for stress detection remains underexplored. This work presents the first comprehensive design space exploration of low-power, flexible stress classifiers. We cover various ML classifiers, feature selection, and neural simplification algorithms, with over 1200 flexible classifiers. To optimize hardware efficiency, fully customized circuits with low-precision arithmetic are designed in each case. Our exploration provides insights into designing real-time stress classifiers that offer higher accuracy than current methods, while being low-cost, conformable, and ensuring low power and compact size.

Hyper-dimensional computing (HDC), a brain-inspired architecture, is gaining attention for edge AI due to its noise resilience and suitability for resource-constrained environments. However, its deployment in safety-critical domains exposes HDC to critical security vulnerabilities, including data poisoning and intellectual property (IP) theft. We demonstrate a practical side-channel attack on an FPGA-based binary HDC accelerator using voltage fluctuations captured by Time-to-Digital Converters (TDC) sensors to extract its IP, such as class hypervectors. By introducing collision analysis combined with an implicit triggering mechanism, we achieve a maximum of ≈83% bit recovery of a single class hypervector using a few hundred traces, even under parallel operations. We also discuss a randomization counter-measure that effectively reduces the recovery accuracy to ≈19% without sacrificing classification performance.

As artificial intelligence becomes integral in domains like healthcare and autonomous systems, dedicated hardware accelerators are becoming increasingly essential. These are structurally tested at manufacturing, independent of the AI model executed. However, in-field reliability demands model-based functional testing using the Deep Neural Networks (DNNs) deployed during inference. Faults in DNNs can degrade performance, making in-field testing critical under memory and time constraints. We propose a framework to generate a set of test patterns according to memory constraints while ensuring effective fault coverage of the fault distribution through joint optimization of patterns. Results show 100% coverage, outperforming random and adversarial inputs.

Compute-in-Memory (CiM) employing Non-Volatile Memory (NVM) technology is an emerging paradigm that promises higher power efficiency for important data-intensive computations. The performance, power, and resilience properties of emerging NVM technologies determine the efficiency of architectures built around processors and computational memories, and affect design decisions. Thus, fast exploration of the broad design space is necessary to assist decision-making. We present Sisyphus, the first cross-layer framework built to facilitate computer architecture research when such an exploration is required. Sisyphus incorporates detailed technology information for various CiM circuit designs based on STT-MRAM, ReRAM, and PCM technologies and integrates them in fast microarchitecture level system models in gem5 to evaluate performance, power, and resilience (through fault injection) across a large space of design options. Sisyphus’ holistic modeling enables the comprehensive evaluation of all efficiency aspects during the execution of actual workloads on the CPU-CiM architecture. This allows for comparisons to a baseline CPU-only system. In our experimental evaluation, we demonstrate how Sisyphus can derive conclusions regarding the prevalence of one NVM type over another, depending on the prioritized optimization aspect(s).

Measuring similarity between binary patterns is a key kernel in various data-intensive applications such as search engines and artificial intelligence (AI). However, due to the memory wall problem caused by frequent data transfers between processor cores and memory subsystems, executing these operations leads to high energy consumption and increased latency. One approach to mitigating this problem is to utilize Computing-in-Memory (CiM) architectures for the realization of Content-Addressable Memory (CAM) in such applications. Integrating Non-Volatile Memory (NVM) technologies can improve performance and energy efficiency. Redox-based Resistive Access Memory (ReRAM) is a promising candidate for implementation within NVM-based Content-Addressable Memory (CAM) due to its non-volatile nature, low power consumption, and highly distinct resistive levels. However, integrating NVM with conventional CMOS introduces unique fabrication challenges and failure mechanisms that are not seen in CMOS processes alone. Furthermore, the analog nature of CiM increases sensitivity to non-idealities in both ReRAM and CMOS, resulting in new fault behaviors that affect the quality of ReRAM-based CAM (ReCAM) blocks. Therefore, to ensure the high quality of the ReCAM functionality, this paper develops a March-like test algorithm tailored for the ReCAM array. The proposed March-like test algorithm is extendable and can achieve 100% fault coverage.

The demand for Artificial Intelligence (AI) and large AI models mandates high compute power, driving substantial increases in computational cost, both in terms of energy and hardware resources. From the hardware perspective, training these models typically relies on dataflow architectures such as Graphical Processing Unit (GPU) and dedicated AI accelerators. While performance and energy efficiency are essential, the reliability of these systems is equally critical. Given the time and energy requirements for training, in-field failures are extremely costly. At the same time, higher integration density and smaller feature sizes cause high chip activity and temperature. Combined with prolonged execution times, it increases the failure probabilities. This paper focuses on Electromigration (EM) issues in Static RAM (SRAM)-based register files, which act as the primary link between memory and processing cores in dataflow architectures. Our main contribution is a comprehensive EM analysis, revealing a significantly different EM profile compared to traditional SRAM-based caches. These findings highlight the cruciality of EM concern in the SRAM-based register files and open doors to new mitigation and prevention solutions.

HyperDimensional Computing (HDC) is a machine learning paradigm that is well suited for edge devices due to its low-overhead inference hardware and inherent robustness to bit-flips and noise. For safety-critical applications, reliability is paramount, with runtime failures posing a serious threat to HDC accelerators. While HDC is robust to several bit flops in memory without significant loss of accuracy, its performance degrades rapidly once a critical threshold is exceeded where hardware faults exceed the tolerance capacity of the algorithm. Ensuring reliable operation over the lifetime of the system remains a challenge, particularly with runtime hardware failures. Conventional concurrent error detection (CED) methods often only address a limited number of faults or incur significant hardware overhead, which either fall under the algorithmic robustness of HDC or contradict the lightweight nature of HDC implementations. In this work, we propose a lightweight CED method that is tailored to HDC systems. Our method can dynamically detect faults before they cause noticeable accuracy degradation. It introduces negligible hardware overhead (< 0.1%), no additional latency, and ensures 100% coverage of critical errors.

Printed Electronics (PE) set up a new path for the realization of ultra low-cost circuits that can be deployed in every-day consumer goods and disposables. In addition, PE satisfy requirements such as porosity, flexibility, and conformity. However, the large feature sizes in PE and limited device counts incur high restrictions and increased area and power overheads, prohibiting the realization of complex circuits. As a result, although printed Machine Learning (ML) circuits could open new horizons and bring “intelligence” in such domains, the implementation of complex classifiers, as required in target applications, is hardly feasible. In this paper, we aim to address this and focus on the design of battery-powered printed Multilayer Perceptrons (MLPs). To that end, we exploit fully-customized circuit (bespoke) implementations, enabled in PE, and propose a hardware-aware neural minimization framework dedicated for such customized MLP circuits. Our evaluation demonstrates that, for up to 3% accuracy loss, our co-design methodology enables, for the first time, battery-powered operation of complex printed MLPs.

Deep neural networks (DNNs) have emerged as an effective approach in many artificial intelligence tasks. Several specialized accelerators are often used to enhance DNN's performance and lower their energy costs. However, the presence of faults can drastically impair the performance and accuracy of these accelerators. Usually, many test patterns are required for certain types of faults to reach a target fault coverage, which in turn hence increases the testing overhead and storage cost, particularly for in-field testing. For this reason, compression is typically done after test generation step to reduce the storage cost for the generated test patterns. However, compression is more efficient when considered in an earlier stage. This paper generates the test pattern in a compressed form to require less storage. This is done by generating all test patterns as a linear combination of a set of jointly used test patterns (basis), for which only the coefficients need to be stored. The fault coverage achieved by the generated test patterns is compared to that of the adversarial and randomly generated test images. The experimental results showed that our proposed test pattern outperformed and achieved high fault coverage (up to 99.99%) and a high compression ratio (up to 307.2$\times$).

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising alternative to conventional CMOS memory technologies for on-chip cache replacement. Due to its superior access speeds, high endurance, and scalability, it is being extensively considered a promising candidate for last-level cache replacement. This technology has reached considerable industrial maturity, with several foundries now offering this emerging technology. Despite its advantages, STT-MRAM faces reliability challenges, primarily due to its asymmetric error characteristics during write and read operations, where the likelihood of a bit transitioning from$1\rightarrow 0$differs from that of$0\rightarrow 1$. Conventional Error Correcting Codes (ECCs) do not account for such asymmetry between these bit-flip types and fall short of providing balanced error correction. This article introduces an efficient asymmetric and adaptive error correction in STT-MRAM based on the Hamming weight of data bits that operates with negligible overhead alongside a standard ECC framework. Our simulation findings indicate that the proposed technique offers substantial enhancement in reliability, measured by a cache word/block error rate, tested across the last level cache data for various SPEC CPU2017 benchmarks. This enhancement in reliability is achieved without inserting excessive memory and hardware overhead, and without impacting system performance, presenting a compelling case for enhancing the operational reliability of STT-MRAM.

Printed electronics (PE) is an emerging additive manufacturing technology, enabling flexible and extremely lowcost computing devices for future pervasive computing systems. Given the form factor and limited device count in this technology, Unary Encoding (UE), which encodes values as a sequence of bits (1’s or 0’s) by utilizing the proportion of 1’s in the sequence to represent the corresponding probability, shows great promise for printed technologies targeting resource-constrained applications. However, while UE offers some resilience to noise and variability, explicit error correction is still required to address intrinsic defects and variations in printing technologies to deliver reliable and stable outputs. In this work, we propose an area-efficient analog error correction (AEC) method using UE techniques to deal with sporadic bit errors and environmental noise at runtime. This approach significantly reduces transistor count and area utilization compared to conventional error correction coding (ECC) implementations. For proof of concept, we have shown the applicability of this approach for printed physical unclonable functions (p-PUFs) which have significantly lower reliability than silicon-based counterparts. Moreover, the robustness of the proposed scheme against temperature and voltage fluctuations has also been reported. By applying AEC to the p-PUFs output bitstream, its reliability can be fully restored (statistically 100%) for up to 20% bit error rate.

Printed electronics (PEs) is an additive fabrication technology which not only allows for a highly flexible printing of circuit patterns, but also produce soft, nontoxic, and degradable electronics at an extremely low cost. These properties make PE an enabler of new application domains, e.g., fast moving consumer goods and disposable healthcare devices. A particularly promising class of circuits in this technology is the printed analog neuromorphic circuits, offering efficient and highly tailored computational functionalities. In this work, we leverage the highly flexible fabrication process of PE to address the bottleneck of PE, i.e., the large feature sizes and low device counts. This issue is crucial, as it impairs the integration of printed circuits into target applications with limited footprint, such as smart band-aids. We propose an evolutionary algorithm (EA) to improve the circuit compactness through circuit architecture optimization. As baseline, we compare the proposed EA method with a state-of-the-art pruning method and a modified area-aware pruning method. All of them are able to optimize circuit architecture. Experimental simulation reveals that the proposed EA approach can effectively achieve compact circuits and outperform the pruning method by$3.1\times $lower area with no loss of accuracy. As a byproduct, the power is reduced by$3.0\times $, paving the way to energy-harvested printed systems.

Feature size reduction of the front End of the Line (FEoL) and back End of the Line (BEoL) elements, i.e., transistors and interconnects, has been the main enabler of the next-generation computation systems. The decreasing trend of the cross-sectional area of the interconnect in advanced technology nodes, however, comes along with a drastic increase in the resistive parasitic, substantially impacting the overall energy efficiency and performance of the computer system. Mitigation of the high parasitic resistance within an advanced-node static RAM (SRAM)-based last-level cache (LLC) is the main target of this article. To achieve this target, we augment the LLC interconnect with some degree of reconfiguration by utilizing a dynamic segmented bus (DSB). With DSB, the interconnect segments that are most actively used for a given workload can be shortened, on average, contributing to a smaller capacitive load. Hence, the efficient reconfiguration of an LLC interconnect strongly depends on the LLC demands of the application. To account for this workload dependency, we design the required microarchitectural support in an end-to-end application-to-technology flow. By optimizing the overhead of DSB switches and additional hardware modules, the SRAM-based LLC with DSB-augmented intra-macro interconnect achieves 33% energy savings and 16% reduction in total access time across eight representative workloads, with a negligible area overhead of less than 0.4%.

The demand for next-generation flexible electronics in applications like smart packaging and smart bandages has driven the need for cost-effective solutions. Traditional silicon-based electronics struggle with high costs and rigidity, making them unsuitable for these emerging markets. In this regard, additive printed electronics (PE) offer a viable alternative with their flexibility and ultra-low-cost manufacturing. printed analog neuromorphic circuits (pNCs) are well-suited for these target applications, especially for classification tasks, as their low device count can efficiently meet the needs of the technology. However, low-cost additive manufacturing comes with higher defect rates, such as misprints, broken connections, and defective components, posing significant challenges to the reliability of printed circuits. This article presents a novel co-design of training algorithm and hardware for fault-tolerant pNCs using fault-aware training (FAT). The proposed method introduces a fault-tolerant version of printed nonlinear transformation circuits, combined with a bespoke training process that selects different types of printed activation functions (AFs) for different neurons to optimize both fault endurance and hardware costs. Experiments on benchmark datasets demonstrate an improvement in the accuracy of fault-tolerant (FT) pNCs from 62.1% to 79.4% under a 10% fault rate. Moreover, combining both normal and fault-tolerant versions of activation functions (AFs) using gumble-softmax distribution shows an acceptable accuracy drop with an average reduction in power and area of 54.5% and 6.54%, respectively, while reducing the training time significantly by 56.2%, compared to only using FT-AFs.

As technology scales down, the performance–power–area (PPA) of static random access memory (SRAM) is increasingly constrained by interconnects due to the presence of large parasitic capacitance and resistance within these structures. This article presents a co-optimization and co-design framework that integrates technology, interconnect, circuit, cache memory, and workload to optimize the overall PPA of the computing cache system through various emerging interconnect technologies under software and hardware conditions. Moreover, we present the differential transmission line (DTL), which is utilized as a hybrid with conventional wires with repeater insertion. The proposed methodology enables the identification of the optimal design, thereby facilitating the reduction of interconnect energy and delay, considering synthetic/realistic workloads and comparing DTL against traditional repeater insertion methods based on metrics of PPA, including the energy–delay–area product (EDAP) and energy–delay product (EDP), for the computing cache system. A thorough design space exploration is conducted, utilizing validated experimental subarrays at the deep scale across state-of-the-art technology nodes. Moreover, the case study assesses a range of cache system parameters, emphasizing the potential of DTL interconnect technologies to enhance cache memory PPA.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing CMOS memory technologies due to its non-volatility, fast read access, and scalability potential. This has reached the level of industrial maturity as several foundries now offer this technology. However, it is sensitive to various failure mechanisms, such as manufacturing defects in both CMOS and magnetic layers, temperature variation, repetitive writes, and oxide breakdown, which can cause early cell failure leading to hard errors. This can severely impair the manufacturing yield and its large-scale industrial adoption. To ensure high manufacturing yield and infield reliability, we propose a new block error correction pointer (BECP) as a hard error correction technique for STT-MRAM. The proposed method divides large word lengths into smaller sub-blocks and assigns a specific base value per sub-block to determine the offset location of the hard error. This allows storing only the offset value instead of the absolute address of the hard error for each sub-block. The results depict that the proposed method is storage efficient and has low decoding complexity compared to the existing state-of-the-art methods. We incorporate experimental measurement data obtained from manufactured STT-MRAM chips at different die locations to get the hard error distribution. The proposed method aligns well with our specific STT-MRAM error distribution measurements.

Computation-in-memory (CIM) is a promising solution to tackle the memory wall problem in big data and artificial intelligence applications. One possible approach to implement such a scheme is to use nonvolatile resistive memory technologies like spin transfer torque magnetic RAM (STT-MRAM) or resistive RAM (ReRAM). However, despite all the attractive features these technologies offer, they introduce new types of defects different from conventional SRAM technologies. Therefore, there is a need for dedicated testing algorithms that can detect such defects. In this paper, we proposed a testing scheme for CIM-capable memories that utilizes trim circuitry to dynamically switch between standard memory testing and CIM testing modes based on the speed and accuracy requirements, eliminating unnecessary testing overheads. This feature provides significant test time reduction while preserving the quality of the test. The proposed method is compatible with existing memory built-in self-test (MBIST) architecture and can be used for different types of emerging resistive memory technologies.

The modern trend of exploring Artificial Intelligence (AI) in various industries, such as big data, edge computing, automobile, and medical applications, has increased tremendously. As functionalities grow, energy-efficient hardware for AI devices becomes crucial. To address that, Computation-in-Memory (CiM) using Non-Volatile Memories (NVMs) offers a promising solution. However, security is also an important concern in this computation paradigm. In this work, we analyze the vulnerability for power side-channel attacks on Multiply-Accumulate (MAC) operations implemented in CiM architecture based on emerging NVMs. Our results show that peripheral devices such as Analog-to-Digital Converters (ADCs) leak much more sensitive information than the crossbar itself because of its significant power consumption. Therefore, we propose a circuit-level countermeasure based on hiding for the ADCs of memristive CiM architecture to mitigate the power attacks. The efficiency of our proposed countermeasure is shown by both attacks and leakage assessment methodologies using a maximum of one million measurement traces.

FPGAs are now ubiquitous in cloud computing infrastructures and reconfigurable system-on-chip, particularly for AI acceleration. Major cloud service providers such as Amazon and Microsoft are increasingly incorporating FPGAs for specialized compute-intensive tasks within their data centers. The availability of FPGAs in cloud data centers has opened up new opportunities for users to improve application performance by implementing customizable hardware accelerators directly on the FPGA fabric. However, the virtualization and sharing of FPGA resources among multiple users open up new security risks and threats. We present a novel fault attack methodology capable of causing persistent fault injections in partial bitstreams during the process of FPGA reconfiguration. This attack leverages powerwasters and is timed to inject faults into bitstreams as they are being loaded onto the FPGA through the reconfiguration manager, without needing to remain active throughout the entire reconfiguration process. Our experiments, conducted on a Pynq FPGA setup, demonstrate the feasibility of this attack on various partial application bitstreams, such as a neural network accelerator unit and a signal processing accelerator unit.

Bulk bitwise operations are commonplace in application domains such as databases, web search, cryptography, and image processing. The ever-growing volume of data and processing demands of these domains often result in high energy consumption and latency in conventional system architectures, mainly due to data movement between the processing and memory subsystems. Non-volatile memories (NVMs), such as RRAM, PCM and STT-MRAM, facilitate conducting bulk-bitwise logic operations in-memory (CIM). Efficient mapping of complex applications to these CIM-capable NVMs is non-trivial and can even lead to slowdowns. This paper presents Sherlock, a novel mapping and scheduling method for efficient execution of bulk bitwise operations in NVMs. Sherlock collaboratively optimizes for performance and energy consumption and outperforms the state-of-the-art by 10× and 4.6×, respectively.

Printed Electronics (PE) stands out as a promising technology for widespread computing due to its distinct attributes, such as low costs and flexible manufacturing. Unlike traditional silicon-based technologies, PE enables stretchable, conformal, and non-toxic hardware. However, PE are constrained by larger feature sizes, making it challenging to implement complex circuits such as machine learning (ML) classifiers. Approximate computing has been proven to reduce the hardware cost of ML circuits such as Multilayer Perceptrons (MLPs). In this paper, we maximize the benefits of approximate computing by integrating hardware approximation into the MLP training process. Due to the discrete nature of hardware approximation, we propose and implement a genetic-based, approximate, hardware-aware training approach specifically designed for printed MLPs. For a 5% accuracy loss, our MLPs achieve over 5 × area and power reduction compared to the baseline while outperforming state-of-the-art approximate and stochastic printed MLPs.

Bayesian Neural Networks (BayNNs) naturally provide uncertainty in their predictions, making them a suitable choice in safety-critical applications. Additionally, their realization using memristor-based in-memory computing (IMC) architectures enables them for resource-constrained edge applications. In addition to predictive uncertainty, however, the ability to be inherently robust to noise in computation is also essential to ensure functional safety. In particular, memristor-based IMCs are susceptible to various sources of non-idealities such as manufacturing and runtime variations, drift, and failure, which can significantly reduce inference accuracy. In this paper, we propose a method to inherently enhance the robustness and inference accuracy of BayNNs deployed in IMC architectures. To achieve this, we introduce a novel normalization layer combined with stochastic affine transformations. Empirical results in various benchmark datasets show a graceful degradation in inference accuracy, with an improvement of up to 58.11%.

Internet of Things (IoT) and smart wearable devices for personalized healthcare will require storing and computing ever-increasing amounts of data. The key requirements for these devices are ultra-low-power, high-processing capabilities, autonomy at low cost, as well as reliability and accuracy to enable Green AI at the edge. Artificial Intelligence (AI) models, especially Bayesian Neural Networks (BayNNs) are resource-intensive and face challenges with traditional computing architectures due to the memory wall problem. Computing-in-Memory (CIM) with emerging resistive memories offers a solution by combining memory blocks and computing units for higher efficiency and lower power consumption. However, implementing BayNNs on CIM hardware, particularly with spintronic technologies, presents technical challenges due to variability and manufacturing defects. The NeuSPIN project aims to address these challenges through full-stack hardware and software co-design, developing novel algorithmic and circuit design approaches to enhance the performance, energy-efficiency and robustness of BayNNs on sprintronic-based CIM platforms.

Printed electronics (PE) technology provides cost-effective hardware with unmet customization, due to their low non-recurring engineering and fabrication costs. PE exhibit features such as flexibility, stretchability, porosity, and conformality, which make them a prominent candidate for enabling ubiquitous computing. Still, the large feature sizes in PE limit the realization of complex printed circuits, such as machine learning classifiers, especially when processing sensor inputs is necessary, mainly due to the costly analog-to-digital converters (ADCs). To this end, we propose the design of fully customized ADCs and present, for the first time, a co-design framework for generating bespoke Decision Tree classifiers. Our comprehensive evaluation shows that our co-design enables self-powered operation of on-sensor printed classifiers in all benchmark cases.

Brain-inspired hyperdimensional computing (HDC) offers much more efficient computing compared to other classical deep learning and related machine learning algorithms. Unlike classical CMOS, emerging non-volatile memories (NVMs) used in the realization of HDC are susceptible to failures under voltage scaling, which is essential for energy saving. Although HDC is inherently robust against errors, this is only possible when hypervectors with a large dimension (e.g., 10,000 bits) are being used, resulting in significant energy consumption. This work demonstrates, for the first time, that different NVM technologies exhibit different error characteristics under voltage scaling. In contrast to conventional CMOS-based SRAM, we demonstrate that the error behavior is data-dependent and not captured by simple bit flips in emerging NVMs. We employ our cross-layer framework that starts from the underlying technology all the way up to the algorithm to develop the novel HDC training approach DropHD. DropHD considerably shrinks the size of hypervectors (e.g., from 10,000 bits down to merely 3000 bits), while maintaining a high inference accuracy. The use of aggressive voltage scaling reduces energy consumption by 1.6 x. DropHD further reduces it to up to 9.5 × while fully recovering the induced accuracy drop, i.e. without a tradeoff.

The increasing safety requirements for modern complex systems mandate Silicon Lifecycle Management (SLM) using various sensors for in-field test. In this work, we evaluate so-called Path Transient Monitors (PTMs), which are based on delay lines, to detect path delay increase caused by manufacturing defects or runtime degradation. These sensors are integrated into a RISC-V SoC on an FPGA, allowing software-controlled measurements and calibration. Additionally, we introduce means to emulate delay defects and degradations by injecting additional delay elements into a custom add instruction. Furthermore, by using power wasters, we provoke runtime voltage variations. Our evaluation in different temperatures shows the dependencies between different sources of delay variations and how the sensors can help in better detection of delay defects.

Hyperdimensional computing (HDC) has been recognized as an efficient machine learning algorithm in recent years. Robustness against noise and simple computational operations, while being limited by the memory bandwidth, make it a perfect fit for the concept of computation in memory (CiM) with emerging nonvolatile memory (NVM) technologies. For an HDC accelerator based on NVM-CiM, there are different parameters from the algorithm all the way down to the technology that interact with each other and affect the overall inference accuracy as well as the energy efficiency of the accelerator. Therefore, in this paper, we propose, for the first time, a full-stack co-optimization method and use it to design an HDC accelerator based on NVM-based content addressable memory (CAM). By incorporating the device manufacturing variability and co-optimizing the algorithm and hardware design, HDC inference on our proposed NVM-based CiM accelerator can reduce the energy consumption by 3.27x, while compared to the purely software-based implementation, the inference accuracy loss is merely 0.125%.

Accurate out-of-distribution (OOD) detection is crucial for ensuring the safety and reliability of neural network (NN) accelerators in real-world scenarios. This paper proposes a novel OOD detection approach for NN FPGA accelerators using remote power side-channel measurements. We assess different methods for distinguishing power measurements of in-distribution (ID) samples from OOD samples, comparing the effectiveness of simple power analysis and OOD sample identification based on the reconstruction error of an autoencoder (AE). Leveraging on-chip voltage sensors enables non-intrusive and concurrent remote OOD detection, eliminating the need for explicit labels or modifications to the underlying NN.

Biologically-inspired Spiking Neural Networks have emerged as a promising avenue for energy-efficient, high-performance neuromorphic computing. With the demand for highly-customized and cost-effective solutions in emerging application domains like soft robotics, wearables, or IoT-devices, Printed Electronics has emerged as an alternative to traditional silicon technologies leveraging soft materials and flexible substrates. In this paper, we propose an energy-efficient analog printed spiking neuromorphic circuit and a corresponding learning algorithm. Simulations on 13 benchmark datasets show an average of 3.86 x power improvement with similar classification accuracy compared to previous works.

Hyper-Dimensional Computing (HDC), a brain-inspired computing paradigm for cognitive tasks, is especially suited for resource-constrained edge devices due to its hardware-efficient and fault-resistant inference. However, existing HDC approaches require large amounts of memory, resulting in high power consumption, limiting their use in edge devices. We offer a hardware-aware encoding where computation parameters in hardware implementations can be reproduced on-the-fly through low-overhead cyclic digital circuits, significantly reducing memory utilization and subsequently power consumption.

Bayesian Neural Networks (BayNNs) can inherently estimate predictive uncertainty, facilitating informed decision-making. Dropout-based BayNNs are increasingly implemented in Spintronics-based computation-in-memory architectures for resource-constrained yet high-performance safety-critical applications. Although uncertainty estimation is important, the reliability of Dropout generation and BayNN computation is equally important for target applications but is overlooked in existing works. However, testing BayNNs is significantly more challenging compared to conventional NNs, due to their stochastic nature. In this paper, we present for the first time the model of the non-idealities of the Spintronics-based Dropout module and analyze their impact on uncertainty estimates and accuracy. Furthermore, we propose a testing framework based on repeatability ranking for Dropout-based BayNN with up to 100% fault coverage while using only 0.2% of training data as test vectors.

Complex systems are subject to various hardware and software defects and faults through the entire design and deployment lifecycle. Many of such defects originate at the electrical or circuit levels, but manifest as functional failures in the field. In this study, we present a methodology for embedding and employing software-controlled runtime variation and degradation sensors on a RISC-V SoC to enable system-level and functional testing in the field. We demonstrate the effectiveness of the entire platform through an FPGA implementation. Delay defects and path degradations are emulated by injecting artificial delay elements into the critical path of a specific instruction. We also emulate the effect of workload-induced runtime stress with tunable software-controlled power wasters. Combining various sensors, we show that transient fluctuations, which are caused by temperature or workload, can be effectively separated from persistent delay increase, which is caused by latent manufacturing defects or aging.

In recent years, Artificial Intelligence (AI) systems have achieved revolutionary capabilities, providing intelligent solutions that surpass human skills in many cases. However, such capabilities come with power-hungry computation workloads. Therefore, the implementation of hardware acceleration becomes as fundamental as the software design to improve energy efficiency, silicon area, and latency of AI systems. Thus, innovative hardware platforms, architectures, and compiler-level approaches have been used to accelerate AI workloads. Crucially, innovative AI acceleration platforms are being adopted in application domains for which dependability must be paramount, such as autonomous driving, healthcare, banking, space exploration, and industry 4.0. Unfortunately, the complexity of both AI software and hardware makes the dependability evaluation and improvement extremely challenging. Studies have been conducted on both the security and reliability of AI systems, such as vulnerability assessments and countermeasures to random faults and analysis for side-channel attacks. This paper describes and discusses various reliability and security threats in AI systems, and presents representative case studies along with corresponding efficient countermeasures.

Printed Electronics (PE) is an emerging technology with flexible substrates and ultra-low-cost manufacturing, providing an appealing alternative to traditional wafer-scale silicon fabrication. With the increasing integration of various printed neural network (NN) architectures in diverse applications, the reliability of printed circuits has become a critical concern. This work provides a comprehensive analysis of the fault sensitivity on a variety of classification tasks for various digital and analog realizations of printed multilayer perceptrons (MLPs). We further evaluate different digital architectures, i.e., generic, bespoke, and approximate, to provide a comprehensive fault analysis on different benchmark datasets.

Magnetoresistive random access memory (MRAM) is an attractive option to replace eFlash. The recent demonstration of a nano-second write speed and a 10e14 endurance are compelling performances even as an embedded MRAM for cache replacement. Both eFlash and cache applications often use large array sizes, which require tight defect control. The unique defects in MRAMs that are not easily detectable with traditional memory test algorithms can potentially cause test escapes. Test escapes will not only delay the manufacturing process but also cause reliability issues, which is fatal for safety-critical applications such as automotive. This paper presents effective ways of screening hard-to-find defects related to oxide surface quality. The devices with minor oxide degradation have properties in the grey zone, which spec out some of the properties, although they pass the functional test. We introduce a new test method to screen those spec out cells using read reference trimming.

With the rise of AI, end of Moore's law, and the digitization of public services, the demand for accelerated computing is growing. To address this demand, major cloud service providers like Amazon Web Services, Microsoft Azure, and Google Cloud Platform have incorporated FPGA instances into their infrastructure with efficient and adaptable resource allocation models. Interest is increasing in multi-tenant FPGAs, which enable multiple users to utilize FPGA resources concurrently, while the FPGA can be split into smaller sections, one per tenant. Nevertheless, it introduces significant security vulnerabilities. For instance, by configuring a malicious circuit in one tenant's section of the FPGA, attacks that cause faults or crash the entire FPGA become feasible, affecting other tenants. By splitting an FPGA into smaller fractions, a single tenant has less potential to cause catastrophic outcomes. However, in this paper, we propose another threat, which is to perform an attack where several malicious tenants coordinate an attack using an unintended covert channel. We practically verify this possibility and introduce such a synchronized and coordinated voltage drop attack from multiple malicious tenants. For synchronization, the malicious tenants use a voltage-based covert channel. Our results show that the communication is robust reaching less than 1% packet error rate and that the attack is successful and avoids state-of-the-art countermeasures.

Hyper-Dimensional Computing (HDC) as a brain-inspired computational model for cognitive tasks is suitable for edge devices due to its hardware-friendly and fault-resistant computations. Despite this potential, HDC has a large memory footprint, resulting high power consumption. In this work, we propose a hardware-aware encoding where parameters are generated on-the-fly without any large memory block requirements. Moreover, the hardware mapping of the trained HDC model is optimized to make it suitable for resource-constraint edge devices. In this work we propose an end-to-end flow from HDC training to FPGA mapping. We demonstrate the efficiency of this method compared to other state-of-the-art HDC implementations in terms of hardware usage and power consumption.

The applications of artificial intelligence (AI) are rapidly evolving, and they are also commonly used in safety-critical domains, such as autonomous driving and medical diagnosis, where functional safety is paramount. In AI-driven systems, uncertainty estimation allows the user to avoid overconfidence predictions and achieve functional safety. Therefore, the robustness and reliability of model predictions can be improved. However, conventional uncertainty estimation methods, such as the deep ensemble method, impose high computation and accordingly hardware (latency and energy) overhead because they require the storage and processing of multiple models. Alternatively, Monte Carlo dropout (MC-dropout) methods, although having low memory overhead, necessitate numerous (~ 100) forward passes, leading to high computational overhead and latency. Thus, these approaches are not suitable for battery-powered edge devices with limited computing and memory resources. In this paper, we propose the Tiny-Deep Ensemble approach, a low-cost approach for uncertainty estimation on edge devices. In our approach, only normalization layers are ensembled M times, with all ensemble members sharing common weights and biases, leading to a significant decrease in storage requirements and latency. Moreover, our approach requires only one forward pass in a hardware architecture that allows batch processing for inference and uncertainty estimation. Furthermore, it has approximately the same memory overhead compared to a single model. Therefore, latency and memory overhead are reduced by a factor of up to ~ M ×. Nevertheless, our method does not compromise accuracy, with an increase in inference accuracy of up to ~ 1% and a reduction in RMSE of 17.17% in various benchmark datasets, tasks, and state-of-the-art architectures.

Printed electronics offer ultra-low manufacturing costs and the potential for on-demand fabrication of flexible hardware. However, significant intrinsic constraints stemming from their large feature sizes and low integration density pose design challenges that hinder their practicality. In this work, we conduct a holistic exploration of printed neural network accelerators, starting from the analog-to-digital interface---a major area and power sink for sensor processing applications---and extending to networks of ternary neurons and their implementation. We propose bespoke ternary neural networks using approximate popcount and popcount-compare units, developed through a multi-phase evolutionary optimization approach and interfaced with sensors via customizable analog-to-binary converters. Our evaluation results show that the presented designs outperform the state of the art, achieving at least 6× improvement in area and 19× in power. To our knowledge, they represent the first open-source digital printed neural network classifiers capable of operating with existing printed energy harvesters.

The adoption of FPGA instances by major cloud service providers (CSPs) reflects the growing demand for accelerated and heterogeneous computing across various applications, e.g., AI. To improve the efficiency, utilization and virtualization, multi-tenant FPGAs allow multiple users to utilize FPGA resources concurrently, with each FPGA partition assigned to a separate tenant. However, this introduces significant security vulnerabilities, such as the potential for attacks by configuring a malicious circuit in one tenant's FPGA partition. One notable vulnerability is disrupting the FPGA's power distribution network, leading to faults or even crashing the entire FPGA, affecting other tenants. Usually, such an attack requires a considerable amount of resources. A naive solution would be splitting an FPGA into smaller fractions to reduce the potential for successful Power-Hammering by individual tenants and enhance the security. However, our paper demonstrates that even with smaller fractions per tenant, attacks can still occur. We propose the threat of coordinated attacks, where malicious tenants use an unintended covert channel between them. We practically validate this threat in a real cloud computing environment by introducing a synchronized and coordinated power-hammering attack from multiple malicious tenants. These tenants synchronize their actions using a voltage-based covert channel. Our results reveal the success of the attack, surpassing state-of-the-art countermeasures and detection mechanisms with a success rate exceeding 90%, compared to 30% for uncoordinated attacks.

The market demand for next-generation flexible electronics is experiencing a significant upsurge, particularly in cost-sensitive consumer applications like smart packaging and smart bandages. These products are beyond the reach of traditional silicon-based electronics due to their high production cost and rigid form factor. Printed electronics (PE), with its adaptable and ultra-low-cost solutions, essentially meet the unique needs of these emerging application areas. This work presents a novel approach using an evolutionary algorithm (EA) to design highly bespoke printed analog neuromorphic circuits (pNCs) offering robustness against variability inherent in the printing process. By leveraging this algorithm and designing robust activation circuits, not only the resistances (weights) in the crossbar and parameters in the activation circuits, but also the types of nonlinear circuits (i.e., functional forms of activation functions) as well as the circuit topologies (neural architecture) can be learned to enhance the circuit robustness against printing variations. Experiments on 13 benchmark datasets demonstrate that, compared to the baseline, the proposed methodology can further outperform the normalized classification error rate by ≈ 55.38% and ≈ 25.11% under high-precision (±5%) and low-precision (±10%) printing scenarios, respectively. Moreover, the algorithm suggests the ReLU as the most robust activation function (AF) circuit family with only ≈ 21% susceptible to low precision (±10%) printing variation.

The inherent limitations of traditional processor-centric architectures have led to the emergence of Computationin-Memory (CiM), offering an energy-efficient hardware solution for diverse applications such as deep learning and cryptography. However, CiM’s analog domain computations, relying on curren sensing for output, expose potential vulnerabilities to glitch-based fault injections. These are still unexplored in CiM and can prevent their widespread adoption. Our work investigates side-channel vulnerabilities in scouting logic CiM, revealing that an attacker can extract sensitive information with minimal measurements through side-channel analysis based on an effective Fault Sen sitivity Analysis (FSA). We demonstrate that with access to data-dependent delays at the transient output level, correlation analysis between fault sensitivity and transient output characteristics facilitates input data recovery. To counter these threats, we propose a power- and area-efficient circuit-level countermeasure tailored for CiM architectures, proving its effectiveness through comprehensive assessments, including correlation attacks and Test Vector Leakage Analysis (TVLA) with one million traces.

Testing magnetoresistive random access memory (MRAM) presents several challenges, particularly in scaled technology nodes. One major challenge is the increased interconnect resistance from the bitline and sourceline, which leads to issues like the near-far effect, where bitcells farther from the sensing circuit exhibit higher resistance. Additionally, the fabrication process can result in defects that may not be easily detectable using conventional testing methods. Another factor that makes the screening process more difficult is the presence of process variation. This paper proposes a memory-built-in self-test (MBIST) compatible method that compensates for the interconnect resistance effect using multi-level references and memory partitioning. In addition, the proposed method aims to find the location in the memory array that is less affected by process variation and use it to adjust the screening boundaries for the entire memory to detect defective bitcells more effectively. On average, the proposed method shows around 50% defect coverage improvement and 76% weak bitcell coverage improvement over its previous counterparts. The detected defects will be further evaluated for repair by ECC or other redundancy schemes to maximize product quality and yield.

The Memory Wall represents a significant performance and energy bottleneck in conventional computer architecture, caused by the frequent and costly data transfers between memory and processor cores. Computation in Memory (CiM) offers a promising solution, particularly benefiting similarity computation—a key component in various computer science applications—through the use of emerging non-volatile memory (NVM) technologies. However, intrinsic non-idealities of NVM technologies coupled with noise-sensitivity of analog circuitry can impair the reliability and correct functionality of the applications. This paper performs a cross-layer technology to application reliability and performance analysis of NVM-based similarity computation in memory. We consider various NVM technologies, different CiM-based similarity computation modules, and different real-world applications that are accurately simulated in a full-system environment. The results demonstrate significant improvements in both latency (up to 12x) and energy efficiency (up to 6.7x) of NVM-CiM compared to traditional architectures. Importantly, the study finds that latency and energy are largely unaffected by the specific NVM technology used, though reliability varies significantly—up to 28% in terms of architectural vulnerability factor (AVF).

The long-term reliability of Static Random Access Memory (SRAM) is crucial for safety-critical applications, such as those in the automotive industry. In the front-end-of-line (FEoL), the transistor elements are susceptible to negative bias temperature instability (NBTI), while in the back-end-of-line (BEoL) the interconnects are susceptible to electromigration (EM), especially in scaled technology nodes. To meet safety-critical standards, it is essential to investigate the combined aging mechanisms within the SRAM array and to develop effective testing methodologies during the operational lifetime of the system. Such methodologies are also crucial for enabling the early detection of in-field failures. In this paper, a precise aging model is presented that extends the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model and includes physical modeling for EM. This approach provides insights into the combined effects of NBTI and EM on the degradation of SRAM writability, considering the entire SRAM subarray, including the bit-cell array and peripheral circuits in Fin Field-Effect Transistors (FinFET) technology.

Neural networks (NNs) have shown outstanding performance in various domains, leading to widespread deployment on various hardware devices. They require large memories to store the NN weight parameters, which are susceptible to numerous permanent and transient faults. Therefore, error detection and correction mechanisms with certain guarantees should be provided to ensure reliable NN operation, especially in safety-critical applications. Error Correction Codes (ECCs) are a common approach to protecting memories against these failures, but they impose significant memory overheads. This work proposes NN-ECC, a multi-task learning objective that integrates linear block ECC into the NN parameters during training. The proposed NN-ECC does not increase the total number of NN parameters and eliminates all storage requirements for parity bits of different ECCs. Unlike existing methods, which selectively eliminate the storage overhead with limited error correction and necessitate specific weight distributions to utilize redundant weight bits for ECC parity, our approach is versatile and can accommodate various ECC schemes with different correction capabilities without imposing constraints on weight distributions. Moreover, the proposed NN-ECC does not deteriorate the baseline accuracy due to ECC encoding.

As technology scales down, the interconnect parasitic resistance more dominantly affects performance degradation and test escapes. The wire resistance increase is especially a great challenge in resistive-based non-volatile memories (NVM) such as magnetic random access memory (MRAM) and resistive RAM (ReRAM) because it can cause faulty reading of the data. The resistive-based NVMs perform the read operation by sensing the bitcell resistance relative to a reference value. Therefore, additive parasitic resistances along the read path, including the bitline (BL) and sourceline (SL) resistances, may cause incorrect read operation. The additive path resistance also makes defect screening harder. A defect screening method designed to detect faulty bitcells located near the sensing circuit may not effectively screen out a bitcell located far from the sensing circuit with the same defectivity level and lead to test escapes. Utilizing a multi-level reference, the proposed new testing scheme compensates for the additive line resistance effect and improves coverage for local defect screening. The detected fault will be further evaluated for correction by ECC or repaired to maximize field coverage. The proposed method is applicable to existing industrial memory built-in self-test (MBIST) solutions with minor modifications.

The computation-in-memory (CiM) paradigm is widely acknowledged to tackle the memory wall problem. Additionally, leveraging non-volatile resistive memory (NVM) technologies enhances the energy efficiency of the CiM by enabling analog computation. However, the reliability of the NVM-CiM is challenged due to the inherent device and circuit imperfections, the technology-level process variation, the sensing offset, and the analog nature of the computation. In this paper, we perform comprehensive reliability analysis and mitigation from the technology all the way to the CiM application. For this aim, we accurately model the NVM device variability and imperfection and effectively model the consequent errors at the circuit level by considering crossbar parasitic and sensing offset. Subsequently, we inject these modeled faults into the CiM-enabled full-system architecture. The study quantitatively assesses the masking capability of CiM applications and explores potential mitigation techniques to enhance the overall reliability of NVM-CiM.

The growing complexity and size of hardware designs necessitates novel, scalable approaches to verification, as latent bugs and security flaws have devastating impact. This is especially critical since bugs in hardware designs cannot be patched after manufacturing. Currently, dynamic verification is the predominant methodology for detecting hardware design flaws, where detection efficiency is primarily determined by the choice of (random) inputs to the design under test. More elaborate recent methods adapt principles from greybox software fuzzing to achieve high coverage in short time. However, these existing greybox methods rely on heavy instrumentation or software conversion, which requires access to the design source code. Fuzing of blackbox hardware designs has only been possible with random, undirected input generation up until now, which requires a long time to cover the majority of possible hardware states. In this work, we propose FUZZ-E, a novel scalable method for coverage-guided hardware design fuzzing, where coverage is indirectly estimated through on-chip voltage measurements on FPGAs. The side-channel-based FUZZ-E approach enables testing blackbox hardware designs without requiring access to any internal signals. We provide an extensive analysis of the correlation between hardware design coverage and voltage fluctuations, and show how FUZZ-E significantly reduces the verification time required to achieve desirable design coverage.

The long-term reliability of the Static Random Access Memory (SRAM) module, as an important component of computing architectures, is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistor elements are vulnerable to negative bias temperature instability (NBTI), while the back end of the line (BEoL) interconnect is prone to electromigration (EM). Complying with safety-critical standards as part of silicon lifecycle management (SLM) infrastructure requires an understanding of the combined aging mechanisms of transistors and interconnects in SRAM. Moreover, a precise aging model is a prerequisite for effective aging testing and mitigation strategies. For this aim, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model at the FEoL, and use measurement-calibrated physical modeling of EM at the BEoL, to create an integrated analysis that can provide deeper insights into the individual and combined effects of NBTI and EM for SRAM operation. Our findings reveal the mutual acceleration of delay faults and hard stuck-at faults caused by NBTI and EM in SRAM, offering a precise methodology for estimating the time to failure under these conditions.

Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

Neural networks (NNs) are capable of learning complex patterns and relationships in data to make predictions with high accuracy, making them useful for various tasks. However, NNs are both computation-intensive and memory-intensive methods, making them challenging for edge applications. Hence, hardware AI accelerators architectures based on computation-in-memory (CiM) architectures with non-volatile memristive crossbars are gaining attention. Although memristive devices offer benefits such as power efficiency, parallelism, and nonvolatility, they suffer from non-idealities, leading to various faults and parameter variations, both during manufacturing and lifetime operations. This can lead to faulty computations and, in turn, degradation of post-mapping inference accuracy, which is unacceptable for many applications, including safety-critical applications. Therefore, proper testing of NN hardware accelerators is of utmost importance for functional safety. In this paper, we propose a one-shot testing approach that can test NNs accelerated on memristive crossbars with only one test vector, making it very suitable for online testing applications. Our approach can consistently achieve 100% fault coverage across several large topologies with up to 201 layers and challenging tasks like semantic segmentation. Nevertheless, compared to existing methods, the fault coverage is improved by up to 24%, the memory overhead is only 0.0123 MB, a reduction of up to 19980× and the number of test vectors is reduced by 10000×.

With the rise of the big data, processing in the cloud has become more significant. One method of accelerating applications in the cloud is to use field programmable gate arrays (FPGAs) to provide the needed acceleration for the user-specific applications. Multitenant FPGAs are a solution to increase efficiency. In this case, multiple cloud users upload their accelerator designs to the same FPGA fabric to use them in the cloud. However, multitenant FPGAs are vulnerable to low-level denial-of-service attacks that induce excessive voltage drops using the legitimate configurations. Through such attacks, the availability of the cloud resources to the nonmalicious tenants can be hugely impacted, leading to downtime and thus financial losses to the cloud service provider. In this article, we propose a tool for the offline classification to identify which FPGA designs can be malicious during operation by analysing the metadata of the bitstream generation step. We generate and test 475 FPGA designs that include 38% malicious designs. We identify and extract five relevant features out of the metadata provided from the bitstream generation step. Using ten-fold cross-validation to train a random forest classifier, we achieve an average accuracy of 97.9%. This significantly surpasses the conservative comparison with the state-of-the-art approaches, which stands at 84.0%, as our approach detects stealthy attacks undetectable by the existing methods.

The computation-in nonvolatile memory (NVM-CiM) approach addresses the growing computational demands and the memory-wall problem faced by traditional processor-centric architectures. Computation-in-memory (CiM) capitalizes on the parallel nature of memory arrays enabling effective computation through multirow memristor reading and sensing. In this context, the conventional design of memory decoders needs to be accordingly modified for efficient multirow activation and parallel data processing. This article presents the design and optimization of address decoders for NVM-CiM system architectures, employing a cross-layer co-optimization approach that integrates circuit and architecture design with application requirements. Our methodology starts at the circuit level, examining various decoder designs, including cascaded, hierarchical, latched, and hybrid models. An in-depth application-level characterization follows, utilizing an extended NVM-CiM-capable gem5 simulator to assess the impact of these decoders on the mapping of CiM-friendly applications and the resulting system performance, particularly in facilitating rapid and efficient activation of multirow memory configurations. This holistic analysis allows us to identify the bottlenecks and requirements from the application side and adjust the design of the decoder accordingly. Our analysis reveals that Hybrid Decoders significantly decrease latency and power consumption compared to other decoder designs within NVM-CiM systems. This highlights the crucial role of the decoder’s row selection flexibility, reducing additional system-level data movement even at the expense of its performance, can substantially improve the overall efficiency of NVM-CiM systems.

SRAM performance is highly dominated by interconnects as technology scales down because of the significant parasitic resistance and capacitance in the interconnect. This paper introduces a framework for the co-design of technology, interconnect, and cache memory with tag array overhead, to optimize the performance of cache memory using a variety of emerging interconnect technologies. In addition, we introduce an innovative E-Tree interconnect aimed at further decreasing the average interconnect length with the consideration of realistic workloads and benchmark against its traditional H-Tree counterparts in terms of various performance metrics, such as energy-delay-area product (EDAP) or energy-delay product (EDP) in the SRAM cache memory system. A comprehensive investigation of design space is conducted, employing realistic, deeply scaled subarray designs across a range of cutting-edge technology nodes. Furthermore, the case study examines various cache memory system design parameters to assess the true potential of emerging interconnect technologies in achieving optimal performance at the cache memory system.

FPGA as general-purpose accelerators can greatly improve system efficiency and performance in cloud and edge devices alike. However, they have recently become the focus of remote attacks, such as fault and side-channel attacks from one to another user of a part of the FPGA fabric. In this work, we consider system-on-chip platforms, where an FPGA and an embedded processor core are located on the same die. We show that the embedded processor core is vulnerable to voltage drops generated by the FPGA logic. Our experiments demonstrate the possibility of compromising the data transfer from external DDR memory to the processor cache hierarchy. Furthermore, we were also able to fault and skip instructions executed on an ARM Cortex-A9 core. The FPGA based fault injection is shown precise enough to recover the secret key of an AES T-tables implementation found in the mbedTLS library.

Deep Neural Networks (DNNs) have gained considerable attention lately due to their excellent performance on a wide range of recognition and classification tasks. Accordingly, fault detection in DNNs and their implementations plays a crucial role in the quality of DNN implementations to ensure that their post-mapping and infield accuracy matches with model accuracy. This paper proposes a functional-level automatic test pattern generation approach for DNNs. This is done by generating inputs which causes misclassification of the output class label in the presence of single or multiple faults. Furthermore, to obtain a smaller set of test patterns with full coverage, a heuristic algorithm as well as a test pattern clustering method using K-means were implemented. The experimental results showed that the proposed test patterns achieved the highest label misclassification and a high output deviation compared to state-of-the-art approaches.

This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for machine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in-memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technologies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in resistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to reliability and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory layouts and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications.

Typical neural networks are incapable of effectively estimating prediction uncertainty, leading to overconfident predictions. Estimating uncertainty is crucial for safety-critical tasks such as autonomous vehicle driving and medical diagnosis and treatment. Bayesian Neural Networks (BayNNs), which combine the capabilities of neural networks and Bayesian inference, are an effective approach for uncertainty estimation. However, BayNNs are computationally demanding and necessitate substantial memory resources. Computation-in-memory (CiM) architectures uti-lizing emerging resistive non-volatile memories such as Spin- Orbit Torque (SOT) have been proposed to increase the resource efficiency of traditional neural networks. However, training scalable and efficient BayNNs and implementing them in the CiM architecture presents its own challenges. In this paper, we propose a scalable Bayesian NN framework via Subset-Parameter inference and its Spintronic-based CiM implementation. Our method is evaluated on large datasets and topologies to show that it can achieve comparable accuracy while still being able to estimate uncertainty efficiently at up to 70 × lower power consumption and 158.7× lower storage memory requirements.

The demand of many application domains for flexibility, stretchability, and porosity cannot be typically met by the silicon VLSI technologies. Printed Electronics (PE) has been introduced as a candidate solution that can satisfy those requirements and enable the integration of smart devices on consumer goods at ultra low-cost enabling also in situ and on-demand fabrication. However, the large features sizes in PE constraint those efforts and prohibit the design of complex ML circuits due to area and power limitations. Though, classification is mainly the core task in printed applications. In this work, we examine, for the first time, the impact of neural minimization techniques, in conjunction with bespoke circuit implementations, on the area-efficiency of printed Multilayer Perceptron classifiers. Results show that for up to 5 % accuracy loss up to 8× area reduction can be achieved.

As we move toward the commercialization of Spin-Transfer Torque Magnetic Random Access Memories (STT -MRAM), cost-effective testing and in-field reliability have become more prominent. Among STT-MRAM manufacturing defects, pinholes are one of the important ones. Pinholes are defects on the surface of the oxide layer which degrade the resistive values and, in some cases, cause an oxide breakdown. Some moderate levels of pinhole defects can remain undetected during standard functional tests and may cause a field failure. A stress test of the whole memory, including multiple cycles of long writes, has been suggested to detect candidate pinhole defects. However, this test not only causes extra costs but also degrades the reliability of MRAM for the entire array. In this paper, we have statistically studied the behavior of pinholes and proposed a cost-effective testing scheme to capture pinhole defects and increase the reliability of the end product. Our method limits the number of test candidate cells that need to be hammered, providing a reduced test time of up to 96.42% for our case studies compared to existing methods. This is while the advantages of standard tests are all preserved with our method. The proposed approach is compatible with memory-built-in self-test (MBIST) schemes.

Static RAM (SRAM) is one of the critical components in advanced VLSI systems whose performance, capacity, and reliability have a decisive impact on the entire system. It offers the fastest memory in the storage hierarchy of modern computer systems. By moving toward the smaller CMOS technology nodes, the back end of the line (BEoL) interconnects are also fabricated in tighter pitch size. Hence, besides the power lines, SRAM word- and bit-line (WL and BL) are also susceptible to electromigration (EM). Therefore, EM reliability of SRAM's WL and BL needs to be analyzed during design technology co-optimization (DTCO) cycle. In this work, we investigate the impact of technology scaling on SRAM designs and perform a detailed analysis on the trend of their EM reliability and energy consumption. Our analysis shows that although scaling down the CMOS technology can result in a 2.68x improvement in the energy efficiency of the SRAM module, it increases the EM-induced hydrostatic stress by 2.53x.

Deep neural networks (DNNs) have achieved record-breaking performance in various applications. To reduce the energy footprint and increase performance, DNNs are often implemented on specific hardware accelerators, such as Tensor Processing Units (TPU) or emerging Memristive technologies. Unfortunately, the presence of various hardware faults can threaten these accelerators' performance and degrade the inference accuracy. This necessitates the development of efficient testing methodologies to unveil hardware faults in DNN accelerators. In this work, we propose a test pattern generation approach to detect fault patterns in DNNs for a common type of hardware fault, namely, faulty weight value representations on the bit level. Contrary to most related works which reveal faults via output deviations, our test patterns are constructed to reveal faults via misclassification which is more realistic for black-box testing.

Printed and flexible electronics promises smart devices for application domains, such as smart fast moving consumer goods and medical wearables, which are generally untouchable by conventional rigid silicon technologies. This is due to their remarkable properties such as flexibility, non-toxic materials, and having low-cost per area. Combined with neuromorphic computing, printed neuromorphic circuits pose an attractive solution for these application domains. Particularly, the additive printing technologies can reduce large amount of fabrication complexities and costs. On the one hand, high-throughput additive printing processes, such as roll-to-roll printing, can reduce the per-device fabrication time and cost. On the other hand, jet-printing can provide point-of-use customization at the expense of lower fabrication throughput. In this work, we propose a machine learning based design framework, that respects the objective and physical constraints of split additive manufacturing for printed neuromorphic circuits. With the proposed framework, multiple printed neural networks are trained jointly with the aim to sensibly combine multiple fabrication techniques (e.g., roll-to-roll and jet-printing). This should lead to a cost-effective fabrication of multiple different printed neuromorphic circuits and achieve high fabrication throughput, lower cost, and point-of-use customization.

With the rapid growth of the Internet of Things, smart fast-moving consumer products, and wearable devices, requirements such as flexibility, non-toxicity, and low cost are desperately required. However, these requirements are usually beyond the reach of conventional rigid silicon technologies. In this regard, printed electronics offers a promising alternative. Combined with neuromorphic computing, printed neuromorphic circuits offer not only the aforementioned properties, but also compensate for some of the weaknesses of printed electronics, such as manufacturing variations, low device count, and high latency. Generally, (printed) neuromorphic circuits express their functionality through printed resistor crossbars to emulate matrix multiplication, and nonlinear circuitry to express activation functions. The values of the former are usually learned, while the latter is designed beforehand and considered fixed in training for all tasks. The additive manufacturing feature of printed electronics allows the design of highly-bespoke designs. In the case of printed neuromorphic circuits, the circuit is optimized to a particular dataset. Moreover, we explore an approach to learn not only the values of the crossbar resistances, but also the parameterization of the nonlinear components for a bespoke implementation. While providing additional flexibility of the functionality to be expressed, this will also allow an increased robustness against printing variation. The experiments show that the accuracy and robustness of printed neuromorphic circuits can be improved by 26% and 75% respectively under 10% variation of circuit components.

Neural networks (NNs) are a widely-used problem-solving tool, but their high computational and power consumption makes them expensive. Computation-in-Memory (CiM) architecture, which uses resistive non-volatile memories, is a promising solution due to its high energy efficiency. However, manufacturing defects and in-field faults can reduce the reliability and inference accuracy of CiM-implemented neural networks. Existing sophisticated fault detection and tolerance techniques require long downtime for testing and repair. In certain applications, e.g., "always on" NN applications, such downtime may not be acceptable. Thus, in this paper, a low-cost online fault tolerance technique based on local approximations is proposed to ensure continuous neural network operation with acceptable accuracy. Our approach reduces hardware overhead by up to 99.37% compared to conventional redundancy-based approaches while still achieving accuracy within 2% of the trained NNs.

The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead.

To overcome the bottleneck of the classical processor-centric architectures, Computation-in-Memory (CiM) is a promising paradigm where operations are performed directly in memory. Recent works propose the use of CiM to accelerate neural networks or hyperdimensional computing, but also for memory encryption solutions. As CiM facilitates the computation in the analog domain and the output is driven through current sensing, CiM could potentially be highly vulnerable to power side-channel attacks. In this work, we analyze the vulnerability for power side-channel attacks in various CiM implementations based on Static Random Access Memory (SRAM) and emerging nonvolatile memristive technologies. Our results show that a side-channel attacker can recover secret data used in an XOR operation with only a few hundred measurements, where CiM architectures based on emerging memristive technologies are more vulnerable than SRAM-based CiM. Therefore, we propose two different types of countermeasures based on hiding and masking, which are tailored to CiM architectures. The efficiency of our proposed countermeasures is shown by both attacks and leakage assessment methodologies using one million measurement traces.

Artificial neural networks pervade almost all areas of today's life, being used for both simple image classification tasks as well as highly complex decision making in mission-critical tasks. This makes artificial neural networks an attractive target for attackers to recover the model architecture or user inputs and outputs through either classical software vulnerabilities or hardware side-channel and fault attacks. With increasing complexity of the models, smaller companies now often opt for pre-trained public models, which are then used with potentially sensitive inputs, for instance, in medical applications. In this work, we present a novel remote side-channel attack methodology to steal neural network inputs using generative convolutional neural networks. After measuring voltage fluctuations using on-chip sensors, we are able to recover the original inputs to image classifiers on different FPGA platforms. Our results prove the effectiveness of our attack, as we are able to recover inputs from networks running on different devices, with different datasets, and under different operating conditions.

Neural networks are becoming increasingly utilized in a range of real-world applications, often involving privacy-sensitive or safety-critical tasks like medical image analysis or autonomous driving. Despite their usefulness, designing and training neural networks (NNs) can be costly, both in terms of financial and energy expenses [4]. Gathering and labeling training data, actual training, and fine-tuning require considerable resources. The network models themselves are also considered confidential intellectual property (IP). Additionally, the carbon footprint of model training and development has a significant impact on the environment [5].

FPGAs have become a popular choice for machine learning acceleration for both cloud and edge devices. While traditional neural networks show impressive performance in classification tasks, Hyperdimensional Computing (HDC) is rapidly emerging as a promising novel machine learning approach for its hardware-friendly inference. In HDC, classes are embedded into high-dimensional vectors during training, and inputs can be classified by computing similarity metrics between class-vectors during inference. HDC inference is especially promoted in terms of its resiliency against errors, attributed to the large inherent redundancy. In this work, we perform a thorough experimental investigation of the fault resiliency of various FPGA-based machine learning implementations under different aspects of stress, comparing HDC with classical neural network approaches. We explore both the amount of faulty classifications as well as system crashes while subjecting the designs to timing stress using overclocking, voltage stress with excessive switching activity, and thermal stress.

Machine learning acceleration has become increasingly popular in recent years, with machine learning-as-a-service (MLaaS) scenarios offering convenient and efficient ways to access pre-trained neural network models on devices such as cloud FPGAs. However, the ease of access and use also raises concerns over model theft or misuse through model manipulation. To address these concerns, this paper proposes a method for identifying neural network models in MLaaS scenarios by their unique power consumption. Current fingerprinting methods for neural networks rely on input/output pairs or characteristic of the decision boundary, which might not always be accessible in more complex systems. Our proposed method utilizes unique power characteristics of the black-box neural network accelerator to extract a fingerprint by measuring the voltage fluctuations of the device when querying specially crafted inputs. We take advantage of the fact that the power consumption of the accelerator varies depending on the input being processed. For evaluation of our method we conduct 200 fingerprint extraction and matching experiments and the results confirm that the proposed method can distinguish between correct and incorrect models in 100% of the cases. Furthermore, we show that the fingerprint is robust to environmental and chip-to-chip variations.

Due to the importance of FPGAs for secure systems, dealing with private data, protection against side-channel analysis attacks is a must. Although masking is a widely-deployed countermeasure, its application - particularly in hardware - is costly and error-prone. Therefore, generating masked hardware automatically with publicly-available tools such as AGEMA is attractive. As AGEMA was introduced to generate ASIC designs, its direct application on FPGAs is inefficient. In this work, we present AGEMA_FPGA to automatically generate highly-efficient masked circuits for FPGAs. Compared to the original AGEMA designs, our masked FPGA-based circuits utilize up to 64% fewer LUTs and at most 22% fewer FFs while the power consumption is reduced by at most 59%. We further provide an experimental side-channel security analysis of our designs confirming their provable security nature.

For on-chip SRAM, a major portion of delay and energy is contributed by the H-Tree interconnects. In this paper, we propose an E-Tree interconnect technology to minimize the H-Tree delay and energy overheads based on an efficient interconnect technology/memory co-design framework for nonuniform workloads. Various array- and interconnect-level design parameters are co-designed for optimal performance using three emerging interconnect materials with a realistic cell library.

Printed Electronics (PE) feature distinct and remarkable characteristics that make them a prominent technology for achieving true ubiquitous computing. This is particularly relevant in application domains that require conformal and ultra-low cost solutions, which have experienced limited penetration of computing until now. Unlike silicon-based technologies, PE offer unparalleled features such as non-recurring engineering costs, ultra-low manufacturing cost, and on-demand fabrication of conformal, flexible, non-toxic, and stretchable hardware. However, PE face certain limitations due to their large feature sizes, that impede the realization of complex circuits, such as machine learning classifiers. In this work, we address these limitations by leveraging the principles of Approximate Computing and Bespoke (fully-customized) design. We propose an automated framework for designing ultra-low power Multilayer Perceptron (MLP) classifiers which employs, for the first time, a holistic approach to approximate all functions of the MLP's neurons: multiplication, accumulation, and activation. Through comprehensive evaluation across various MLPs of varying size, our framework demonstrates the ability to enable battery-powered operation of even the most intricate MLP architecture examined, significantly surpassing the current state of the art.

There is an increasing demand for next-generation flexible electronics in emerging low-cost applications such as smart packaging and smart bandages, where conventional silicon electronics cannot enter due to cost and form factor. In these domains, ultra-low-cost, high flexibility, and customizability are required. In this regard, printed electronics emerge as a complementary solution offering the aforementioned properties. To respect the constraints in those application scenarios and equip printed devices with the fundamental capability to process information, analog printed neuromorphic circuits offer multiple advantages, including strong expressiveness, streamlined circuit primitives, and a highly efficient machine learning-based design process. In this work, we focus on designing low-power printed neuromorphic circuits at the algorithmic level. By developing accurate power models for the circuit primitives, the power consumption can be considered into the design process. Subsequently, Pareto analysis is employed to examine the relationship between accuracy and power consumption. Experimental results reveal that, with the proposed approach, 2 x reduction of the power consumption can be realized while maintaining 95 % of classification accuracy. This approach has significant implications for the future development of energy-efficient printed neuromorphic circuits and their potential applications in IoT and AI intersections.

Nowadays, RISC-V processors have attracted much attention due to their extendability, for targeting high performance applications with strict demands on functional safety. Silicon Lifecycle Management (SLM) is a new emerging concept aiming at functional safety among other features such as availability, maintainability, and lifetime extension. This concept helps to monitor the system health during its lifecycle, in the various timespans, to ensure that safety margins while running critical applications are not exceeded. Hence, enabling both the collection of chip parametrics as well as in-field testing will provide the means to fulfill this concept. In this work, we propose instruction set extensions for enabling SLM in a RISC-V based system. For this purpose, we introduce Path Transient Monitors (PTM) and Voltage Fluctuations Monitors (VFM) for monitoring path delay and voltage fluctuations. Using power wasters as a mean to inject voltage fluctuations in the FPGA system, we evaluate the abilities of this system to monitor chip degradation in early stages before system failure.

Pass transistor logic (PTL) has emerged recently in advanced high-speed optical communication system due to its higher speed and lower power consumption compared to traditional CMOS logic. However, the sensitivity to radiation-induced soft errors of PTL implementations is significant different from CMOS circuitry, which emphasizes the need for understanding the mechanism of soft error propagation in PTL. Due to the non-conventional logic structure in PTL, previous approaches of pulse width modelling in CMOS logic are no more applicable since they are not always measurable. Hence, in this paper, we propose a learning-based structural regression modeling approach to explore the soft error propagation mechanism in PTL at transistor level. Our models can be easily mapped onto higher level to analyze soft error propagation in any complex PTL designs. The experimental results on a 4-bit ripple carry adder demonstrate that our models can achieve high accuracy compared with SPICE simulation.

Memristive devices offer energy and area efficient non-volatile data storage for data-intense Ternary Content Ad-dressable Memory (TCAM) architectures. However, depending on the storage implementation in the bitcell design, the matching functionality shows multiple undesired discharge effects leading to false look-up results. In particular, the ternary storage suffers during the look-up operation from a poor resistance ratio, match-line leakage and device variabilities. In this paper, we investigate the inherent, design-dependent limitations in the ternary state storage capability due to different memristive TCAM bitcell design parameters and device variabilities. We test these limits based on variability-aware device simulations and isolate crucial parameters for the optimization of memristive TCAMs.

Recently, RISC-V processors have been proposed in domains with high demand on both performance as well as functional safety, such as autonomous driving or medical devices. Therefore, enabling in-field test and measurement methods to ensure correct functionality over the entire chip lifecycle has become a necessity. In this paper, we propose an instruction set extension for RISC-V cores to enable on-chip telemetry for software-controlled in-field parametric testing. To that end, we introduce a so-called Path Transient Monitor (PTM) sensor, which is connected to the critical path of the core. Through custom instructions, the PTM is able to measure output transients with a timing resolution 1000 times (∼11.5 ps) higher than the rated clock period (few ns) of the RISC-V core, allowing thorough assessment of the device health state during in-field operation. As a case study, we implement our proposed setup as an FPGA-based hardware prototype and investigate the impact of process and design variation, temperature, and input data, to evaluate the usefulness of the collected sensor data.

The matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning hardware accelerators. The crossbar array structure with memristive devices as a building block has an inherent capability to perform energy-efficient MVM. However, the memristive devices suffer from various non-idealities as well as limited number of stable levels. Therefore, the reliability and in turn inference accuracy of the deep learning application is negatively impacted. Thus, this paper presents a low overhead checksum-based error correction method for memristive crossbars for MVM computation. The proposed methodology alleviates the problem of storing the checksum value into multiple columns of the crossbar due to the limited number of stable levels of memristive devices. The number of extra columns required for storing the checksum value is reduced, resulting in a significant reduction in the memory overhead by up to 75%. The proposed method scales the checksum value of trained neural networks (NNs) and then performs checksum-aware retraining, and results show negligible impact (∼3%) on the inference accuracy of the NNs on MNIST, Fashion-MNIST, CIFAR-10, and Veg-15 datasets.

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking and signal processing, among many others. Unfortunately, fine-grained programmability also makes FPGAs a security risk. Here, we review the current scope of attacks on cloud FPGAs and their remediation. Many of the FPGA security limitations are enabled by the shared power distribution network in FPGA devices. The simultaneous sharing of FPGAs is a particular concern. Other attacks on the memory, host microprocessor, and input/output channels are also possible. After examining current attacks, we describe trends in cloud architecture and how they are likely to impact possible future attacks. FPGA integration into cloud hypervisors and system software will provide extensive computing opportunities but invite new avenues of attack. We identify a series of system, software, and FPGA architectural changes that will facilitate improved security for cloud FPGAs and the overall systems in which they are located.

Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that feature ultra-low cost, conformity, and non-toxicity requirements that silicon-based systems cannot deliver. Nevertheless, large feature sizes in PE prohibit the realization of complex printed ML circuits. In this work, we present, for the first time, an automated printed-aware software/hardware co-design framework that exploits approximate computing principles to enable ultra-resource constrained printed multilayer perceptrons (MLPs). Our evaluation demonstrates that, compared to the state-of-the-art baseline, our circuits feature on average 6x (5.7x) lower area (power) and less than 1% accuracy loss.

Neuromorphic computation-in-memory fabric based on emerging nonvolatile memories considered an attractive option to accelerate neural networks (NNs) in hardware as they provide high-performance, low-power, and reduced data movement. Although nonvolatile resistive memories (NVMs) offer many benefits, they are susceptible to data retention faults, where previously stored data are not retained after a certain amount of time due to external influence. These faults are more likely to happen unidirectional and severely impact the inference accuracy of the hardware implementation of NNs since the synaptic weights stored in the NVMs are subject to retention faults. In this work, we propose an approximate scrubbing technique for NVM-based neuromorphic fabric to mitigate unidirectional retention faults with virtually zero storage overhead depending on the definition of scrub area for multilayer perceptron (MLP) and convolutional NNs (CNNs). The training of the NNs is adjusted accordingly to meet the requirements of the proposed approximate scrubbing scheme. On different benchmarks, the proposed scrubbing approach can improve the inference accuracy up to 85.51% for MLP and 87.76% for CNN over the expected device operational time with negligible storage overhead.

Printed electronics (PEs) promises on-demand fabrication, low nonrecurring engineering costs, and subcent fabrication costs. It also allows for high customization that would be infeasible in silicon, and bespoke architectures prevail to improve the efficiency of emerging PE machine learning (ML) applications. Nevertheless, large feature sizes in PE prohibit the realization of complex ML models in PE, even with bespoke architectures. In this work, we present an automated, cross-layer approximation framework tailored to bespoke architectures that enable complex ML models, such as multilayer perceptrons (MLPs) and support vector machines (SVMs), in PE. Our framework adopts cooperatively a hardware-driven coefficient approximation of the ML model at algorithmic level, a netlist pruning at logic level, and a voltage overscaling at the circuit level. Extensive experimental evaluation on 12 MLPs and 12 SVMs and more than 6000 approximate and exact designs demonstrates that our model-to-circuit cross-approximation delivers power and area optimal designs that, compared to the state-of-the-art exact designs, feature on average 51% and 66% area and power reduction, respectively, for less than 5% accuracy loss. Finally, we demonstrate that our framework enables 80% of the examined classifiers to be battery-powered with almost identical accuracy with the exact designs, paving thus the way toward smart complex printed applications.

The state-of-the-art test infrastructure security is based on the assumption of preventing access to the sensitive information and the (publicly) accessible outputs or test infrastructure subset are supposed to not leak any secret information. In addition, for achieving functional safety requirements, the on-chip test infrastructure is reused in-field and cannot be completely disabled after the manufacturing test phase. Therefore, the access to the scan chains or similar test access ports which can lead to sensitive information needs to be restricted or encrypted to guarantee the security of the test infrastructure. However, in this work we show that having access to (small delay) test results on insensitive (public) outputs can in fact reveal secret data. Using real hardware, we have performed template attacks using the results of delay testing on the output of cryptographic circuits and were able to retrieve the key with very few test inputs. This template attack requires only a few random patterns on the victim device, which could be different from the device used for template building. In addition, the attack is also resilient against runtime variation and noise, as well as inaccuracies and down sampling of delay testing measurements.

Recent development in neural networks (NNs) has led to their widespread use in critical and automated decision-making systems, where uncertainty estimation is essential for trustworthiness. Although conventional NNs can solve many problems accurately, they do not capture the uncertainty of the data or the model during optimization. In contrast, Bayesian neural networks (BNNs), which learn probabilistic distributions for their parameters, offer a sound theoretical framework for estimating uncertainty. However, traditional hardware implementations of BNNs are expensive in terms of computational and memory resources, as they (i) are realized with inefficient von Neumann architectures, (ii) use a significantly large number of random number generators (RNGs) to implement the distributions of BNNs, and (iii) have a substantially greater number of parameters than conventional NNs. Computing-in-memory (CiM) architectures with emerging resistive non-volatile memories (NVMs) are promising candidates for accelerating classical NNs. In particular, spintronic technology, which is distinguished by its low latency and high endurance, aligns very well with these requirements. In the specific context of Bayesian neural networks (BNNs), spintronics technologies are very valuable, thanks to their inherent potential to act as stochastic or as deterministic devices. Consequently, BNNs mapped on spintronic-based CiM architectures could be a highly efficient implementation strategy. However, the direct implementation on CiM hardware of the learned probabilistic distributions of BNN may not be feasible and can incur high overhead. In this work, we propose a new Bayesian neural network topology, named SpinBayes , that is able to perform efficient sampling during the Bayesian inference process. Moreover, a Bayesian approximation method, called in-memory approximation , is proposed that approximates the original probabilistic distributions of BNN with a distribution that can be efficiently mapped to spintronic-based CiM architectures. Compared to state-of-the-art methods, the memory overhead is reduced by 8× and the energy consumption by 80×. Our method has been evaluated on several classification and semantic segmentation tasks and can detect up to 100% of various types of out-of-distribution data, highlighting the robustness of our approach, without any performance sacrifice.

Memory cells in emerging non-volatile resistive memories often have asymmetric switching properties, where reliable write operations are achieved by setting the write period to a fixed value. To improve their performance and energy efficiency, self-terminating write schemes have been proposed, in which the write signal is stopped after the required state change has been observed. In this work, we show how this data-dependent write latency can be exploited as a side-channel in multiple ways to unveil restricted memory content. Moreover, we discuss and evaluate potential approaches to address the issue.

Printed electronics (PE) feature low non-recurring engineering costs and low per unit-area fabrication costs, enabling thus extremely low-cost and on-demand hardware. Such low-cost fabrication allows for high customization that would be infeasible in silicon, and bespoke architectures prevail to improve the efficiency of emerging PE machine learning (ML) applications. However, even with bespoke architectures, the large feature sizes in PE constraint the complexity of the ML models that can be implemented. In this work, we bring together, for the first time, approximate computing and PE design targeting to enable complex ML models, such as Multi-Layer Perceptrons (MLPs) and Support Vector Machines (SVMs), in PE. To this end, we propose and implement a cross-layer approximation, tailored for bespoke ML architectures. At the algorithmic level we apply a hardware-driven coefficient approximation of the ML model and at the circuit level we apply a netlist pruning through a full search exploration. In our extensive experimental evaluation we consider 14 MLPs and SVMs and evaluate more than 4300 approximate and exact designs. Our results demonstrate that our cross approximation delivers Pareto optimal designs that, compared to the state-of-the-art exact designs, feature 47% and 44% average area and power reduction, respectively, and less than 1% accuracy loss.

Printed electronic (PE) can meet the requirements of many application domains with requirements on cost, conformity, and non-toxicity which silicon-based computing systems cannot achieve. A typical computational task to be performed in many of such applications is classification. Therefore, printed Neural Networks (pNNs) have been proposed to meet these requirements. However, PE suffers from high process variations due to low resolution printing in low-cost additive manufacturing. This can severely impact the inference accuracy of pNNs. In this work, we show how a unique feature of PE, namely additive printing can be leveraged to perform in-situ tuning of pNNs to compensate accuracy losses induced by device variations. The experiments show that, even under 30 % variation of the conductances, up to 90 % of the initial accuracy can be recovered.

Analog Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency. Spin-Transfer Torque Magnetic Memory (STT-MRAM) is one of the promising technologies for CiM architectures. Although STT-MRAM has various benefits, it does not have the potential to be used directly in analog multi-value CiM operations due to its limited levels of cell resistance states. In this paper, we propose a novel flexible multi-value design for STT-MRAM (MVSTT) with the potential to be used for multi-value CiM. In the multi-value CiM, we are able to have various 2sresistive state combinations from$s$selected MTJs, which is not possible in the normal STT-MRAM CiM. The size of the MVSTT can be adjusted at run-time depending on the application's requirements. The benefits of the proposed scheme are quantified in representative applications such as multi-value matrix multiplications, which is the basic computation of Neural Networks applications. For the multi-value matrix multiplication, the energy, and delay gain is up to 9.7 × and 13.3 ×, respectively, to non-CiM matrix-vector-multiplication. Also, for the neural network, the proposed design allows up to a 32 × reduction in the STT-MRAM cells per crossbar to achieve a similar inference accuracy as the binarized neural network.

Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.

Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.

Functional safety is considered as a prominent dependability attribute in today’s automotive world. It is extremely important to ensure safe operation of different automotive parts. An alternator unit is an electric generator used in modern automobiles to charge the battery and to power the electrical system when its engine is running. Therefore, its correct operation is crucial for the overall automobile safety. In this work, we predict the health of an alternator on-the-fly using machine learning approaches for efficient yet accurate failure detection. We make use of inexpensive time domain features of alternator voltage waveform to achieve 97% prediction accuracy with no false positives. The correctness and usability of the proposed approach has been validated using realistic testing environment.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

Specialized hardware accelerators in the form of FPGAs are widely being used for neural network implementations. By that, they also become the target of power analysis attacks that try to reverse engineer the embedded secret information, in the form of model parameters. However, most of these attacks assume rather simple implementations, not realistic frameworks. Layer folding is used in such accelerators to optimize the network under given area constraints with various degrees of parallel and sequential operations. In this paper, we show that folding does mislead existing power side-channel attacks on frameworks such as FINN. We show how we can extract the folding parameters successfully and use that information to subsequently also recover the number of neurons–something not reliably possible without knowing the folding information. Following the methodologies of both profiling side-channel attacks and machine learning, our approach can extract the amount of neurons with 98% accuracy on a test device, compared to 44-79% accuracy based on related work under the same test conditions and datasets. Furthermore, we show how a classifier that is based on regression can detect previously unknown parameters, which has not been shown before. To verify our results under different environmental conditions, we test the target device in a climate chamber under various temperature ranges and still reach accuracies of at least 93%.

Practical cryptographic systems rely on a true random number generator (TRNG), which is a necessary component in any hardware Root-of-Trust (RoT). Hardware trust anchors are also integrated into larger chips, for instance as hard-IP cores in FPGAs, where the remaining FPGA fabric is freely programmable. To provide security guarantees, proper operation of the TRNG is critical. By that, adversaries are interested to tamper with the ability of TRNGs to produce unpredictable random numbers. In this paper, we show that an FPGA on-chip attack can reduce the true randomness of a TRNG integrated as a hard-IP module in the FPGA. This module is considered to be an immutable security module, compliant with NIST SP 800– 193 Platform Firmware Resilience Guidelines (PFR), which is a well known guideline for system resilience, and it is also certified by the Cryptographic Algorithm Validation Program (CAVP). By performing an on-chip voltage drop-based fault attack with user-programmable FPGA logic, the random numbers produced by the IP core fail NIST SP 800–22 and BSI AIS31 tests, meaning they are not truly random anymore. By that, this paper shows that new attack vectors can break even verified IP cores, since on-chip attacks are usually not considered in the threat model, which can still affect highly integrated systems.

Approximate computing (AxC) has been long accepted as a design alternative for efficient system implementation at the cost of relaxed accuracy requirements. Despite the AxC research activities in various application domains, AxC thrived the past decade when it was applied in Machine Learning (ML). The by definition approximate notion of ML models but also the increased computational overheads associated with ML applications-that were effectively mitigated by corresponding approximations-led to a perfect matching and a fruitful synergy. AxC for AI/ML has transcended beyond academic prototypes. In this work, we enlighten the synergistic nature of AxC and ML and elucidate the impact of AxC in designing efficient ML systems. To that end, we present an overview and taxonomy of AxC for ML and use two descriptive application scenarios to demonstrate how AxC boosts the efficiency of ML systems.

Printed electronics allow for ultra-low-cost circuit fabrication with unique properties such as flexibility, non-toxicity, and stretchability. Because of these advanced properties, there is a growing interest in adapting printed electronics for emerging areas such as fast-moving consumer goods and wearable technologies. In such domains, analog signal processing in or near the sensor is favorable. Printed neuromorphic circuits have been recently proposed as a solution to perform such analog processing natively. Additionally, their learning-based design process allows high efficiency of their optimization and enables them to mitigate the high process variations associated with low-cost printed processes. In this work, we address the aging of the printed components. This effect can significantly degrade the accuracy of printed neuromorphic circuits over time. For this, we develop a stochastic aging-model to describe the behavior of aged printed resistors and modify the training objective by considering the expected loss over the lifetime of the device. This approach ensures to provide acceptable accuracy over the device lifetime. Our experiments show that an overall 35.8% improvement in terms of expected accuracy over the device lifetime can be achieved using the proposed learning approach.

Matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning and big data applications. On the other hand, the Memory wall problem in traditional processor-centric architectures limits the performance of these applications. The crossbar array of emerging non-volatile memristive devices (memristive crossbar) provides an energy-efficient hardware implementation of MVM for deep learning accelerators and edge computing hardware. However, non-idealities as well as manufacturing and runtime defects of the memristive devices may severely impact the reliability of target applications. This paper presents a new online block error correction technique for memristive crossbars. It enables reliable MVM computation by combining the idea of checksum and Hamming code-based linear coding scheme. The proposed method can correct any number of errors in one particular array block containing multiple columns. An adaptive error correction coding strategy is also presented, so that the ratio of data columns to the parity checksum columns can be adjusted at runtime based on the fault rate, enabling the optimum use of data and parity checksum columns.

Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency, which is a promising approach to address so-called memory wall of conventional von Neumann architectures. Redox-based Random access memory (ReRAM) is an appropriate candidate for the realization of CiM concepts in CMOS co-integrated crossbar structures. However, ReRAM devices suffer from inherent variability in fabrication and operation. In this paper, we propose a statistical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on this, a comprehensive reliability analysis is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture has a high failure probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

Deep learning has been applied in many fields such as autonomous driving, medical imaging, and sensor data processing to solve complex computational problems. Hardware implementation of deep learning applications can be accelerated with Memristive devices such as Resistive Random-Access Memory (ReRAM), Phase Change Memories (PCM), and Spin Transfer Torque-Magnetic RAM (STT-MRAM) via utilizing compute-in-memory (CiM) architectures. They offer many benefits compared to conventional charge-based memories including non-volatility, zero leakage power, and low power consumption. However, memristors suffer from various manufacturing and runtime defects and variations due to their immature fabrication process, inherent device properties, and external environmental factors such as temperature. Those faults can negatively impact the performance and reliability of the implemented deep learning applications. Therefore, detection of such faults before they catastrophically affect the accuracy of deep learning applications is very important. In this paper, we proposed a simple and non-invasive functional test generation method with a black-box approach that samples a small subset of the training data as the test vectors based on their approximate gradient ranking. The proposed method requires only up to 0.128% of training data stored in hardware as test vectors and achieves test coverage up to 100% on the Fashion-MNIST, CIFAR-10, and CIFAR-100 benchmark datasets.

Moving to more advanced CMOS technologies can improve the performance and energy efficiency of the VLSI systems, including the static RAM (SRAM) as one of the most demanding memory elements of the modern computer systems. However, the long-term reliability of the SRAM is also important and needs to be carefully considered. This is particularly of utmost importance in safety critical systems, including automotive, with stringent requirements for in-field testing. In advanced technology nodes, the interconnects are designed in a tighter pitch-size, which result in an increase in the current density. Moreover, due to the higher chip complexity, the operating temperature is typically higher. Both the high current density and high temperature exacerbate the electromigration (EM) phenomenon in interconnects, which eventually leads to resistance increase and timing faults. This negatively influences the long-term reliability of the system. Because of the EM, SRAM-based memory modules may undergo field failure, such as read or write faults. To avoid functional safety violation, early detection and prediction of the EM is crucial. In this work, we propose an optimized EM test methodology which is able to predict the effect of EM up to 9.7 months earlier before it leads to failures in normal functional mode.

Performing the computation in memory (CiM) based on the resistive non-volatile memories can significantly improve the energy efficiency and performance of data-intensive and deep learning applications. Activating multiple rows of the memories at the same time is required in Multiply and Accumulation (MAC) operation of neural networks. This simultaneous activation, however, increases the current density of the shared interconnect, which exacerbates the Electromigration (EM) risk. This paper analyzes the EM phenomenon in CiM-oriented MAC paradigms based on emerging non-volatile resistive memories including Spin Transfer Torque Magnetic RAM (STT-MRAM), Redox-based RAM (ReRAM), and Phase Change Memory (PCM). We show how EM is exacerbated compared to normal memory architectures. For EM analysis in CiM, we modify the existing EM models, and consider different interconnect and array dimensions. We also propose the EM-aware row activation pattern as effective means to mitigate the EM degradations in the analog MAC paradigms.

Neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Resistive Random Access Memory (ReRAM), Phase Change Memories (PCM) and Spin Transfer Torque (STT) is a promising approach for efficient hardware implementation of Neural Networks (NNs) due to their low power consumption and latency. However, NVMs suffers from manufacturing process variations and manufacturing defects resulting in a shift in the distribution of NN activations and can lead to degradation of inference accuracy. The shifted distribution can be tracked and re-calibrated by re-calculating the statistics of the batch normalization layer of NN. However, such re-calibration and re-calculation have high overhead in terms of memory, power, and latency. In this paper, we proposed a low overhead post-manufacturing calibration of NVM-based neuromorphic fabric by approximating batch normalization to reduce re-calibration overhead. The proposed method requires only 0.2% of training data as re-calibration input and can regain inference accuracy by up to 72.32% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets.

STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. This paper addresses different aspects of STT-MRAM; it will cover state-of-the-art, some new results and future challenges related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process-induced damage on device performance at CD < 100 nm. In addition, the paper discusses the design of reliable read mechanism considering the variability effects. Moreover, the failure of traditional fault modeling and test approaches in model STT-MRAM unique defects for appropriate test solutions is demonstrated in this paper based on silicon data.

Emerging non-volatile memories facilitate the Computation in Memory (CiM) paradigm. Performing operations with the concept of CiM plays a crucial role in the efficiency improvement of data-intensive applications. Resistive switching RAM (ReRAM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) are promising candidates for the CiM implementation. Reliable CiM implementation with these resistive non-volatile memories (memristive devices) is challenging and error-prone since the manufacturing process of both the memristive components and the CMOS components are susceptible to the temperature- and voltage-dependent variation. Moreover, the small distance between the distinct resistive levels of the STT-MRAM, and time-dependent resistance drift in ReRAM, exacerbates the reliability of CiM implementations. In this paper, we perform a detailed study on the impact of the temperature and voltage biasing on the variation in both the STT-MRAM and ReRAM technologies as well as propose a voltage tuning scheme to significantly improve the sensing reliability of CiM implementations based on these technologies. We also investigate the impact of our proposed voltage tuning scheme on the power consumption and performance of the CiM circuitry.

Spin-Transfer-Torque Random Access Memories (STT-MRAM) offer attractive features such as high-density, low power consumption and non-volatility. Process variations (PV) are one of the critical problems during the manufacturing process. To mitigate PV, reference trimming is used, to compensate for the offset of the tested array based on their functional behavior. However, additional tests can increase the manufacturing test budget. In this paper, we present a novel approach based on address skipping during the trim search step of the memory test, by accessing only a small sub-array. This enables a significant reduction in trim search time. We perform a progressive skip test flow to improve the overall test time for binary search based trim search by up to 29% while ensuring to capture any failing bits with our proposed skip search.

Electromigration (EM) has been known as a reliability threatening factor for back-end-of-the-line interconnects. Spin-transfer torque magnetic RAM (STT-MRAM) is an emerging nonvolatile memory that has gained a lot of attention in recent years. However, relatively large operational current magnitude is a challenge for this technology, and hence, EM can be a potential reliability concern, even for the signal lines of this memory. A workload-aware EM modeling needs to capture time-dependent current density in the memory signal lines and to be able to predict the effect of the EM phenomenon on the interconnect for its entire lifetime. In this work, we present methods to effectively model the workload-dependent EM-induced meantime to failure (MTTF) in typical STT-MRAM arrays under a variety of realistic workloads. This allows performing the design-space exploration to co-optimize reliability and other design metrics.

With ever-increasing transistor density in nanoscale-integrated circuits, the impact of process variations on circuit performance and chip yield becomes dominant. To prevent failures in the field, simulation-based circuit optimization tools are performed during design time as a countermeasure. However, the efficiency of these tools requires accurate modeling of failure probabilities. Especially, for high-sigma problems such as yield estimation of memory cells, which require very high production yield, the failure rate assessment must be highly accurate. Importance sampling (IS) methods are deployed in this context to uncover very rare failure events, which cannot be revealed by standard Monte Carlo methods. Besides a highly accurate yield prediction model, the limited time budget of the simulation-based analysis tools has to be taken into account. Especially in conjunction with yield optimization techniques, the required number of circuit simulations for the failure rate estimation has to be substantially reduced. In this article, we propose a yield optimization method, which is based on a Bayesian optimization (BO) failure rate estimation technique for high-sigma yield extraction. The BO-based IS method is combined with a kernel density estimator for finding the most probable failure events, which have significant contribution to the chip yield. By integration into a global optimization framework, we show how the proposed yield optimization method can be applied to high-sigma yield optimization problems, such as memory cells. The experimental results indicate that the proposed method consumes only 5% circuit simulations to achieve the same optimization effect as the state-of-the-art yield optimizer techniques.

FPGAs have been used in the cloud since several years, for workloads such as machine learning, database processes and security tasks. As for other cloud services, a highly desired feature is virtualization in which multiple tenants share a single FPGA to increase utilization and by that efficiency. By solely using standard FPGA logic in the untrusted tenant, on-chip logic sensors have recently been proposed, allowing remote power analysis side-channel and covert channel attacks on the victim tenant. However, such sensors are implemented by unusual circuit constructions, such as ring oscillators or delay lines, which might be easily detected by bitstream and/or netlist checking. In this paper we show that such structural checking methods are not universal solutions as the attacks can make use of “benign-looking” circuits. We demonstrate this by showing a successful Correlation Power Analysis attack on the Advanced Encryption Standard.

The increasing amount of resources per FPGA chip makes virtualization and multi-tenancy a promising direction to improve utilization and efficiency of these flexible accelerators in the cloud. However, the freedom given to untrusted parties on a multi-tenant FPGA can result in severe security issues. Side-channel, fault, and Denial-of-Service attacks are possible through malicious use of FPGA logic resources. In this work, we perform a detailed analysis of fault attacks between logically isolated designs on a single FPGA. Attacks were often based on mapping a massive amount of Ring Oscillators into FPGA logic, which naturally induce a high current and subsequent voltage drop. However, they are easy to detect as combinational loops and can be prevented by a hypervisor. Here, we demonstrate how even elaborate fault attacks to recover a secret key of an AES encryption module can be deployed using seemingly benign benchmark circuits or even AES modules themselves to generate critical voltage fluctuations.

Single Event Upset (SEU) is one of the most susceptible reliability issues for CMOS circuits in a harsh environment, such as space or even a sea-level environment. Especially in the advanced nanoscale node, the phenomenon of Multi-node-upset (MNU) becomes more prominent. Although a lot of work has been proposed to solve this problem, most of them ignored the need for low power consumption. Particularly, most existing solutions are not effective anymore when operating in low supply voltage. Therefore, this paper proposes a novel Flip-Flop called TRIGON based on a single-phase-clocking structure to achieve low power consumption while being able to tolerate Double-node-upset (DNU), even when operating at lower supply voltages. The experimental results show that TRIGON has a significant reduction in the area and Power-delay-area-product (PDAP). Particularly, it achieves about 80% energy saving on average when the input is static compared with the state-of-the-art circuits.

Neuromorphic architectures based on emerging resistive memories are in the spotlight of today's research as they are able to solve complex problems with an unmatched efficiency. In particular, resistive approaches offer multiple advantages over CMOS-based designs. Most prominently they are non-volatile and offer small device footprints in addition to very low power operation. However, regular memory testing used for conventional resistive Random Access Memory (RAM) architectures cannot detect all possible faults in the synaptic operations done in a resistive neuromorphic architecture. At the same time, testing all neuromorphic operations from the logic testing perspective is infeasible. In this paper we propose to use reference resistance trimming for the test phase and derive a generic test sequence to detect all the faults impacting the neuromorphic operations based on an extensive defect injection analysis. By exploiting the resistive nature of the underlying architecture, we are able to reduce the testing time from an exponential complexity necessary for a conventional logic testing approach to a linear complexity and reduce this by another 50% with the help of resistance trimming.

Printed electronics (PE) offers flexible, extremely low-cost, and on-demand hardware due to its additive manufacturing process, enabling emerging ultra-low-cost applications, including machine learning applications. However, large feature sizes in PE limit the complexity of a machine learning classifier (e.g., a neural network (NN)) in PE. Stochastic computing Neural Networks (SC-NNs) can reduce area in silicon technologies, but still require complex designs due to unique implementation tradeoffs in PE. In this paper, we propose a printed mixed-signal system, which substitutes complex and power-hungry conventional stochastic computing (SC) components by printed analog designs. The printed mixed-signal SC consumes only 35% of power consumption and requires only 25% of area compared to a conventional 4-bit NN implementation. We also show that the proposed mixed-signal SC-NN provides good accuracy for popular neural network classification problems. We consider this work as an important step towards the realization of printed SC-NN hardware for near-sensor-processing.

Neuromorphic computation-in-memory fabric based on emerging non-volatile memories (NVM) is considered an attractive option to accelerate neural networks (NNs) in hardware as they provide high-performance, low-power, and reduced data movement. Although NVMs offer many benefits, they are susceptible to data retention faults, where previously stored data is not retained. This severely impacts the inference accuracy of mapped NNs. Traditionally, memory scrubbing with error-correcting codes (ECC) is employed to mitigate retention faults in conventional CMOS memories. This is not feasible in NVM-based neuromorphic fabric due to high overhead and inability to represent encoding or decoding in analog computing. In this work, we propose an approximate scrubbing technique for NVM-based neuromorphic fabric to mitigate uni-directional retention faults with minimal storage overhead. The training of the NNs adjusted accordingly to meet the requirements of the scrubbing scheme. On different benchmarks, the proposed scrubbing approach can improve the inference accuracy up to 85.51% over the lifetime with virtually zero storage overhead.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chip. In addition to process variation, thermal variations reduce the operating margin of STT-MRAM even further and impose a tighter limit on the operating temperature range than CMOS technology. Defects that relate to marginal thermally behavior are especially difficult, because it is very costly to test across the entire operating temperature range at the tester, and can even reduce the lifetime of the chip. Therefore, we propose a Memory Built-in Self Test (MBIST) supported screening method to accurately predict the failure behavior of a device under test at high temperatures solely from lower temperature test. By adding five more BIST runs at 85°C, we are able to predict MRAM failures at 125°C with 99.11% accuracy. This prediction can then be used to define a reference trim adjust value to optimize the read operation across the entire operating temperature range of the MRAM.

FPGAs are being offered in the cloud as accelerator resources that can be shared among multiple users (i.e. tenants). Recently, various approaches have shown that fault attacks launched from one tenant region to another are possible, leading to timing faults or crashes of the FPGA. It is, therefore, important that malicious tenants are limited in their ability to cause such security problems. So far, the existing countermeasures against such attacks check the configuration bitstreams before they are reconfigured. Such offline approaches have various practical limitations, e.g. they may force the tenants to unveil their design secrets. In this paper, we present LoopBreaker, a novel runtime solution that can disable the entire activity of a malicious tenant region, in order to rapidly stop a potential attack before it results in a crash (i.e. Denial-of-Service). We implemented and tested multiple attack types and found that realistic attacks demand at least 12–26 µs to be successful. A partial reconfiguration to overwrite the malicious tenant region demands 200 µs in our realworld implementation, which is too slow to prevent the attack from leading to a crash. Instead, our proposed LoopBreaker method only needs 1.5 µs to stop a malicious tenant, which makes it the first online approach that can successfully stop challenging voltage drop-based attacks from causing a crash.

Computation in Memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the implementation of CiM architectures. However, the much smaller off/on ratio of resistance states compared to other non-volatile memories makes CiM implementation challenging in this technology. This is further exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction (MTJs) and CMOS components, resulting in erroneous CiM operations. In this paper, we perform a detailed technology-aware statistical failure analysis of CiM operation and design the optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations. Our results show that using a simpler model of CiM array is sufficient for the optimization of the sensing circuitry. However, it may lead to over-optimistic estimation of failure rates. Therefore, a more comprehensive model is utilized for accurate estimation of CiM failure rates.

The existing work on securing test infrastructure is based on the assumption of restricting or encrypting access to the sensitive information, which otherwise can be accessed by the scan chains or similar test access ports. Hence, the (publicly) accessible outputs or test infrastructure subset supposedly do not leak secret information. Since the on-chip test infrastructure is reused in-field for achieving functional safety requirements, disabling them completely after manufacturing test phase is not an option. In this work we invalidate this assumption by showing that having access to (small delay) test results on insensitive (public) outputs can in fact reveal secret data. Using real hardware, we have performed template attacks using the results of delay testing on the output of cryptographic circuits and were able to retrieve the key with very few test inputs. This template attack requires only few random patterns on the victim device, which could be different from the device used for template building.

Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed so far for various MRAM technologies. The last part of this article gives some perspectives on this hot topic.

Brain-inspired deep neural networks such as Convolutional Neural Network (CNN) have shown great potential in solving difficult cognitive problems such as object recognition and classification. However, such architectures have high computational energy demand and sensitivity to variation effects, making them inapplicable for energy-constrained embedded learning platforms. To address this issue, we propose a learning and mapping approach that utilizes approximate computing during early design phases for a layer-wise pruning and fault tolerant weight mapping scheme of reliable and energy-efficient CNNs. In the proposed approach, approximate CNN is prepared first by layer-wise pruning of approximable neurons, which have high error tolerance margins using a two-level approximate learning methodology. Then, the pruned network is retrained to improve its accuracy by fine-tuning the weight values. Finally, a fault-tolerant layer-wise neural weight mapping scheme is adopted to aggressively reduce memory operating voltage when loading the weights of error resilient layers for energy-efficiency. Thus, the combination of approximate learning and fault tolerance aware memory operating voltage downscaling techniques enable us to implement robust and energy-efficient approximate inference engine for CNN applications. Simulation results show that the proposed fault tolerant and approximate learning approach can improve the energy-efficiency of CNN inference engines by more than 50% with less than 5% reduction in classification accuracy. Additionally, more than 26% energy-saving is achieved by using the proposed layer-wise mapping-based cache memory operating voltage down-scaling.

Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logical connection between the transmitter and receiver blocks. Compared to a recently published covert channel with an estimated 4.8 Mbit/s transmission speed, we show 8 Mbit/s transmission and reduced errors from around 3% to less than 0.003%. Furthermore, we demonstrate proper transmissions of word-size messages and test the channel in the presence of noise generated from other residing tenants’ modules in the FPGA. When we place and operate other co-tenant modules that require 85% of the total FPGA area, the error rate increases to 0.02%, depending on the platform and setup. This error rate is still reasonably low for a covert channel. Overall, the transmitter and receiver work with less than 3–5% FPGA LUT resources together. We also show the feasibility of other types of covert channel transmitters, in the form of synchronous circuits within the FPGA.

Printed electronics (PE) is an emerging technology that provides attractive and complementary features compared to traditional wafer-scale silicon fabrication, such as flexible substrate and point-of-use ultralow-cost manufacturing. The low-cost manufacturing and larger feature sizes mandate reduced complexity in circuit size and also limited and transparent printing layers. This enables optical inspection for manufacturing defect detection, eliminating the need for electrical testing for gross defect detection. Therefore, the traditional problem of controllability and observability in logic testing can completely be alleviated. In this article, we present a learning-based method for optical inspection to detect defective transistors in transparent PE. The method leverages domain-specific as well as common inspection features extracted from optical images to detect defective transistors using supervised learning algorithms trained with real fabricated transistor images. The results show that the proposed method detects 95% of the defective transistors, which can significantly reduce the cost of the overall test flow.

In recent years, computation is shifting from conventional high performance servers to Internet of Things (IoT) edge devices, most of which require the processing of cognitive tasks. Hence, a great effort is put in the realization of neural network (NN) edge devices and their efficiency in inferring a pretrained Neural Network. In this paper, we evaluate the retention issues of emerging resistive memories used as non-volatile weight storage for embedded NN. We exploit the asymmetric retention behavior of Spintronic based Magnetic Tunneling Junctions (MTJs), which is also present in other resistive memories like Phase-Change memory (PCM) and ReRAM, to optimize the retention of the NN accuracy over time. We propose mixed retention cell arrays and an adapted training scheme to achieve a trade-off between array size and the reliable long-term accuracy of NNs. The results of our proposed method save up to 24% of inference accuracy of an MNIST trained Multi-Layer-Perceptron on MTJ-based crossbars.

Neuromorphic computing systems have demonstrated many advantages for popular classification problems with significantly less computational resources. We present in this paper the design, fabrication and training of a programmable neuromorphic circuit, which is based on printed electrolytegated field-effect transistor (EGFET). Based on printable neuron architecture involving several resistors and one transistor, the proposed circuit can realize multiply-add and activation functions. The functionality of the circuit, i.e. the weights of the neural network, can be set during a post-fabrication step in form of printing resistors to the crossbar. Besides the fabrication of a programmable neuron, we also provide a learning algorithm, tailored to the requirements of the technology and the proposed programmable neuron design, which is verified through simulations. The proposed neuromorphic circuit operates at 5V and occupies 385mm2of area.

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.

Due to the aggressive technology downscaling, process variations are becoming pre-dominent, causing performance fluctuations and impacting the chip yield. Therefore, individual circuit components have to be designed with very small failure rates to guarantee functional correctness and robust operation. The assessment of high-sigma failure rates however cannot be achieved with conventional Monte Carlo (MC) methods due to the huge amount of required time-consuming circuit simulations. To this end, Importance Sampling (IS) methods were proposed to solve the otherwise intractable failure rate estimation problem by focusing on high-probable failure regions. However, the failure rate could largely be underestimated while the computational effort for deriving them is high. In this paper, we propose an eXtended Bayesian Optimized IS (XBOIS) method, which addresses the aforementioned shortcomings by deployment of an accurate surrogate model (e.g. delay) of the circuit around the failure region. The number of costly circuit simulations is therefore minimized and estimation accuracy is substantially improved by efficient exploration of the variation space. As especially memory elements occupy a large amount of on-chip resources, we evaluate our approach on SRAM cell failure rate estimation. Results show a speedup of about 16x as well as a two orders of magnitude higher failure rate estimation accuracy compared to the best state-of-the-art techniques.

The emerging Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is seen as a promising candidate to replace conventional on-chip memories. It has several advantages such as high density, non-volatility, scalability, and CMOS compatibility. With this technology becoming ubiquitous, it also becomes interesting as a target for security attacks. As the fabrication process of STT-MRAM evolves, it is susceptible to various fault mechanisms which are different from those of conventional CMOS memories. These unique fault mechanisms can be exploited by an adversary to deploy hardware Trojans, which are deliberately introduced design modifications. In this work, we demonstrate how a particular stealthy circuit modification to inject a fault mechanism, namely dynamic fault, can be exploited to implement a hardware Trojan trigger which cannot be detected by standard memory testing methods. The fault mechanisms can also be used to design new payloads specific to STT-MRAM. We illustrate this by proposing a new payload by utilizing coupling faults, which leads to degraded performance and data corruption.

The goal of the GREAT RIA project is to cointegrate multiple functions like sensors ("Sensing"), RF emitters or receivers ("Communicating") and logic/memory ("Process- ing/Storing") together within CMOS technology by adapting the Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ), elementary constitutive cell of the MRAM memories, to a single baseline technology. Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the lessons learned in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT.

Today's von Neumann computing systems are facing major challenges making them not suitable for evolving ultralow power (e.g., edge computing) applications. Therefore, alternative architectures that make use of post-CMOS devices are under investigation. One of these architectures is computation-in-memory (CIM) based on memristive devices; it performs (parallel) computing within the memory core, which prevents data-movement and results in low energy consumption, at the cost of some modification in memory design. Hence, a CIM die can work either in memory configuration or in computation configuration. One implementation of this architecture is based on Scouting logic; it allows the execution of logic operations within the memory. This paper discusses fault modeling and testing of CIM architectures, applied to a Scouting logic-based architecture. It demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration, thus leading to test escapes. The paper demonstrates how an efficient test can be developed that detects all faults in both configurations. Moreover, it shows that testing the die in the computation configuration reduces the overall test time while improving the outgoing product quality.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.

Deep neural networks (DNNs) are gaining increasing attention and usage in many fields related to artificial intelligence and cognitive processing. Due to challenges associated with the implementation of DNNs using traditional computing architectures, there is a growing interest for brain-inspired, aka Neuromorphic computing platforms and paradigms for direct and hence more efficient implementation of DNNs. The building blocks and operation mode of circuitry and the architectures for Neuromorphic computing bring new challenges, since the implementation and operation of neural networks is fundamentally different from traditional Boolean logic. From the technology point of view, they are based on emerging non-volatile resistive memories, which have new fabrication processes and steps, and hence subject to new types of defects and failures. This paper addresses technology-specific defect characterization for spintronic-based neuromorphic circuits.

Printed electronics holds the promise of meeting the cost and conformality needs of emerging disposable and ultra-low cost margin applications. Recent printed circuits technologies also have low supply voltage and can, therefore, be battery-powered. In this paper, we explore the design space of microprocessors implemented in such printing technologies - these printed microprocessors will be needed for battery-powered applications with requirements of low cost, conformality, and programmability. To enable this design space exploration, we first present the standard cell libraries for EGFET and CNT-TFT printed technologies - to the best of our knowledge, these are the first synthesis and physical design ready standard cell libraries for any low voltage printing technology. We then present an area, power, and delay characterization of several off-the-shelf low gate count microprocessors (Z80, light8080, ZPU, and openMSP430) in EGFET and CNT-TFT technologies. Our characterization shows that several printing applications can be feasibly targeted by battery-powered printed microprocessors. However, our results also show the need to significantly reduce area and power of such printed microprocessors. We perform a design space exploration of printed microprocessor architectures over multiple parameters - datawidths, pipeline depth, etc. We show that the best cores outperform pre-existing cores by at least one order of magnitude in terms of power and area. Finally, we show that printing-specific architectural and low-level optimizations further improve area and power characteristics of low voltage battery-compatible printed microprocessors. Program-specific ISA, for example, improves power, and area by up to 4.18x and 1.93x respectively. Crosspoint-based instruction ROM outperforms a RAM-based design by 5.77x, 16.8x, and 2.42x respectively in terms of power, area, and delay.

A large number of application domains have requirements on cost, conformity, and non-toxicity that silicon-based computing systems cannot meet, but that may be met by printed electronics. For several of these domains, a typical computational task to be performed is classification. In this work, we explore the hardware cost of inference engines for popular classification algorithms (Multi-Layer Perceptrons, Support Vector Machines (SVMs), Logistic Regression, Random Forests and Binary Decision Trees) in EGT and CNT-TFT printed technologies and determine that Decision Trees and SVMs provide a good balance between accuracy and cost. We evaluate conventional Decision Tree and SVM architectures in these technologies and conclude that their area and power overhead must be reduced. We explore, through SPICE and gate-level hardware simulations and multiple working prototypes, several classifier architectures that exploit the unique cost and implementation tradeoffs in printed technologies - a) Bespoke printed classifers that are customized to a model generated for a given application using specific training datasets, b) Lookup-based printed classifiers where key hardware computations are replaced by lookup tables, and c) Analog printed classifiers where some classifier components are replaced by their analog equivalents. Our evaluations show that bespoke implementation of EGT printed Decision Trees has 48.9× lower area (average) and 75.6× lower power (average) than their conventional equivalents; corresponding benefits for bespoke SVMs are 12.8× and Decision outperform 12.7× respectively. Lookup-based Trees their non-lookup bespoke equivalents by 38% and 70%; lookup-based SVMs are better by 8% and 0.6%. Analog printed Decision Trees provide 437× area and 27× power benefits over digital bespoke counterparts; analog SVMs yield 490× area and 12× power improvements. Our results and prototypes demonstrate feasibility of fabricating and deploying battery and self-powered printed classifiers in the application domains of interest.

Emerging memristor-based architectures are promising for data-intensive applications as these can enhance the computation efficiency, solve the data transfer bottleneck and at the same time deliver high energy efficiency using their normally-off/instant-on attributes. However, their storing devices are more susceptible to manufacturing defects compared to the traditional memory technologies because they are fabricated with new materials and require different manufacturing processes. Hence, in order to ensure correct functionalities for these technologies, it is necessary to have accurate fault modeling as well as proper test methodologies with high test coverage. In this paper, we propose technology specific cell-level defect modeling, accurate fault analysis and yield improvement solutions for memristor-based memory as well as Computation-In-Memory (CIM) architectures. Our overall contributions cover three abstraction levels, namely, device, architecture and system. First, we propose a device-aware test methodology in which we have introduced a key device-level characteristic to develop accurate defect model. Second, we demonstrate a yield analysis framework for memristor arrays considering reliability and permanent faults due to parametric variations and explore fault-tolerant solutions. Third, a lightweight on-line test and repair schemes is proposed for emerging CIM devices in machine learning applications.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging non-volatile memory technology, as a leading candidate to replace conventional on-chip memories due to its various advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. However, read and write operations in STT-MRAM are extremely vulnerable to manufacturing variations. In particular, the read operation is becoming more susceptible to failures since the read timing and read-disturb failures have conflicting requirements of read period. To overcome this issue, we propose a technique to reduce the read period without sacrificing the target reliability requirements. The reduced read period, in turn, results in improved read performance and reduced read-disturb rates. The results show that using this technique, the read period can be reduced by 50%, and the read-disturb probability by 51%.

Printed Electronics technology is a key-enabler for smart sensors, soft robotics, and wearables. The inkjet printed electrolyte-gated field effect transistor (EGFET) technology is a promising candidate for such applications due to its low-power operation, high field-effect mobility, and on-demand fabrication. Unlike conventional silicon-based technologies, inkjet printed electronics technology is an additive manufacturing process where multiple layers are printed on top of each other to realize functional devices such as transistors and their interconnections. Due to the additive manufacturing process, the technology has limited routing layers. For routing of complex circuits, insulating crossovers are printed at the intersection of routing paths to isolate them. The crossover can alter the electrical properties of a circuit based on specific location on a routing path. In this work, we propose a crossover-aware placement and routing (COPnR) methodology for inkjet-printed circuits by integrating the crossover constraints in our design framework. Our proposed placement methodology is based on a state-of-the-art evolutionary algorithm while the routing optimization is done using a genetic algorithm. The proposed methodology is compared with the industrial standard placement and routing (PnR) tools. On average, the proposed methodology has 38% fewer crossovers and 94% fewer failing paths compared to the industrial PnR tools applied to printed circuit designs.

Various applications, such as multimedia, machine learning, and signal processing, have a significant intrinsic error resilience. This makes them preferable for approximate computing as they have the ability to tolerate computations and data errors along with producing acceptable outputs. From the technology perspective, emerging technologies with inherent non-determinism and high failure rates are candidates for the realization of approximate computing. Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM due to its high density, scalability, and zero-leakage. The write operation in this technology is inherently stochastic and increases the rate of write errors. Moreover, this technology is associated with other failure mechanisms such as read-disturb and failures due to data retention. These errors are highly dependent on the STT-MRAM parameters (i.e., thermal stability, read/write current, and read/write latency), which varies with the operating temperature and the process variation effects. Fast and energy-efficient STT-MRAM designed for on-chip memories can be easily achieved by relaxing the device parameters at the cost of increased error rate, which can be addressed by approximating memory accesses. In this work, a detailed study of reliability and gains (i.e., performance and energy) tradeoff at the device and system-level of the STT-MRAM-based data cache system is presented in the scope of approximate memories.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate as a universal on-chip memory technology due to its non-volatility, high density, and scalability. However, high write energy and latency are its major shortcomings, particularly for fast cache applications. High write costs can efficiently be reduced by relaxing the STT-MRAM non-volatility requirements at the expense of significant increase in retention failure and read disturb rates resulting in data corruption. Hybrid STT-MRAM architecture combining non-volatile (NVM) and semi-volatile (SVM) STT-MRAM blocks has been proposed recently, which provides energy-efficiency, high storage capacity, better performance, and high reliability. However, a key and challenging requirement is efficient data mapping and migration between NVM and SVM sub-arrays to maximize the benefits of such hybrid caches. On-the-fly data migration decisions usually depend on the last seen data behavior, as it is assumed to be identical to the next one, which has very limited accuracy for rapidly varying workload behavior. In this article, we propose a simple but effective on-the-fly data management policy, which mainly relies on the supervised learning data-pattern classification for quick and highly accurate prediction of the data behavior in the oncoming execution time. Three prediction approaches are proposed and compared for a maximum and average achieved accuracy of 86% and 75%, respectively. Our data management policies aim to optimally leverage the specific features of NVM (high reliability) and SVM blocks (fast and energy-efficient write) of hybrid STT-MRAM memory with minimal migration costs (i.e., energy and performance overheads). Our experimental evaluation reports that for a hybrid STT-MRAM cache with the proposed prediction techniques, the total energy consumption can be reduced around 10.5%, on average, in comparison to the state-of-the-art.

Runtime variability sources, such as bias temperature instability (BTI) and supply voltage fluctuation affect both timing and functionality of the flip-flops inside a VLSI circuit. In this paper, we propose a method to improve the timing and reliability of the VLSI circuits by optimizing the flip-flops for resiliency against aging and supply voltage fluctuation. In the proposed selective reliability optimization method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe BTI impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop-critical flip-flops (VC) of the circuit with the reliability-optimized versions to improve the timing and the reliability of the entire circuit in a cost-effective way. The simulation results show that incorporating the optimized flip-flops in a processor can prolong the lifetime of the processor by 36.9% compared to the original design, which translates into better reliability. This is achieved with negligible leakage overhead (less than 0.1% on the processor) and no area overhead which facilitates the integration of the proposed method in the standard VLSI design flow.

In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo (MC) simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, MC methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, importance sampling (IS) methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this article, we fill this gap by presenting an efficient mixture IS approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and the higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master-slave latch based on a 28-nm FDSOI process. The results show an improvement in accuracy, resulting in up to 63× better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28-nm technology node.

Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes.

As the globalization of chip design and manufacturing process becomes popular, malicious hardware inclusions such as hardware Trojans pose a serious threat to the security of digital systems. Advanced Trojans can mask many architectural-level Trojan signatures and adapt against several detection mechanisms. Runtime Trojan detection techniques are considered as a last line of defense against Trojan inclusion and activation. In this article, we propose an offline analysis to select a subset of flip-flops as surrogates and build an anomaly detection model based on the activity profile of flip-flops. These flip-flops are monitored online, and the anomaly detection model implemented online analyzes the flip-flop data to detect any anomalous Trojan activity. The effectiveness of our approach has been tested on several Trojan-inserted designs of the Leon3 processor. Trojan activation is detected with an accuracy score of above 0.9 (ratio of the number of true predictions to total number of predictions) with no false positives by monitoring less than 0.5% of the total number of flip-flops.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising nonvolatile memory technology for various applications from low power to high-density memory. However, STT-MRAM is prone to power analysis attacks due to its asymmetric resistive states and switching behavior. This noninvasive class of attacks is a serious threat to system security. To reduce the correlation between the data and the power consumption of the memory, a countermeasure based on a resilient cell design with a symmetrical structure is proposed in this article. The standard cell and the proposed cell have been attacked and their resiliencies are compared. When attacked with a correlation power analysis (CPA), the proposed bit cell attacked with the hamming weight (HW) model is 100 times more resilient compared to the standard STT-MRAM cell. The proposed bit cell attacked with the hamming distance (HD) or the STT power models is more than 500 times more resilient compared to the standard STT-MRAM cell.

Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.

Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead.

Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V.

Scaling supply voltage to the near-threshold voltage (NTV) region is an effective approach for energy-constrained circuit design at the cost of acceptable performance reduction. However, by operating in the NTV region, the sensitivity of circuits to process and runtime variations significantly aggravates. Therefore, the performance and power consumption of a circuit is largely impacted by the variabilities, which affects the operating voltage for the most efficient computation, i.e., the minimum energy point (MEP). Accordingly, finding an optimum operating voltage for near-threshold computing (NTC) to account for variabilities is very challenging. In this article, we propose an MEP calibration and adaptation approach based on machine learning to tune for minimal energy operation on a per-chip basis by considering process and runtime variations. In the proposed approach, the optimal supply voltage of each chip is determined during manufacturing tests by characterizing dynamic and leakage power and at runtime by considering the impact of temperature variation. The presented method does not require costly power measurement circuitry on chip. The simulation results show that the proposed method has high MEP prediction accuracy and achieves near-optimal operation by only 1.2% higher energy consumption compared with the optimal operation.

Recently Spin Transfer Torque Random Access Memory (STT-MRAM) technology has drawn a lot of attention for the direct implementation of neural networks, because it offers several advantages such as near-zero leakage, high endurance, good scalability, small foot print and CMOS compatibility. The storing device in this technology, the Magnetic Tunnel Junction (MTJ), is developed using magnetic layers that requires new fabrication materials and processes. Due to complexities of fabrication steps and materials, MTJ cells are subject to various failure mechanisms. As a consequence, the functionality of the neuromorphic computing architecture based on this technology is severely affected. In this paper, we have developed a framework to analyze the functional capability of the neural network inference in the presence of the several MTJ defects. Using this framework, we have demonstrated the required memory array size that is necessary to tolerate the given amount of defects and how to actively decrease this overhead by disabling parts of the network.

Printed electronics (PE) is a fast growing technology with promising applications in wearables, smart sensors and smart cards since it provides mechanical flexibility, low-cost, on-demand and customizable fabrication. To secure the operation of these applications, True Random Number Generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of PE circuits results in high intrinsic variation due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this paper, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field effect transistors (EGFETs). The proposed memory-based TRNG circuit can operate at low voltages (≤ 1 V ), it is hence suitable for low-power applications. We also propose a flow which tunes the printed resistors of the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behaviour. The results show that the overall process variation of the TRNGs is mitigated by 110 times, and the simulated TRNGs pass the National Institute of Standards and Technology Statistical Test Suite.

Approximate computing has gained growing attention as it provides trade-off between output quality and computation effort for inherent error tolerant applications such as recognition, mining, and media processing applications. As a result, several approximate hardware designs have been proposed in order to harness the benefits of approximate computing. While these circuits are subjected to manufacturing defects and runtime failures, the testing methods should be aware of their approximate nature. In this paper, we propose an automatic test pattern generation methodology for approximate circuits based on boolean satisfiability, which is aware of output quality and approximable vs non-approximable faults. This allows us to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output quality or test coverage. Experimental results show that, the proposed approach can reduce the fault list by 2.85× on average while maintaining high fault coverage.

Printed Electronics is perceived to have a major impact in the fields of smart sensors, Internet of Things and wearables. Especially low power printed technologies such as electrolyte gated field effect transistors (EGFETs) using solution-processed inorganic materials and inkjet printing are very promising in such application domains. In this paper, we discuss a modeling approach to describe the variations of printed devices. Incorporating these models and design flows into our previously developed printed design system allows for robust circuit design. Additionally, we propose a reliability-aware routing solution for printed electronics technology based on the technology constraints in printing crossovers. The proposed methodology was validated on multiple benchmark circuits and can be easily integrated with the design automation tools-set.

Due to aggressive technology downscaling, process and runtime variations have a strong impact on the correct functionality in the field as well as manufacturing yield. The assessment of the yield and failure rate is extremely crucial for design optimization. The common practice is to use Monte Carlo simulations in order to account for device variations and estimate failure rate. However, Monte Carlo methods are infeasible for estimating rare events such as high sigma failure rates, and hence, various importance sampling methods have been proposed. In this paper, we present an efficient importance sampling approach based on Bayesian optimization. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate. We evaluated the approach on a 6T SRAM cell based on a 28nm FDSOI process. The results show significant speedup and more than two orders of magnitude better accuracy in failure rate estimation, compared to the best state-of-the-art technique.

Dynamic and partial reconfiguration together with hardware parallelism make FPGAs attractive as virtualized accelerators. However, recently it has been shown that multi-tenant FPGAs are vulnerable to remote side-channel attacks (SCA) from malicious users, allowing them to extract secret keys without a logical connection to the victim core. Typical mitigations against such attacks are hiding and masking schemes, to increase attackers' efforts in terms of side-channel measurements. However, they require significant efforts and tailoring for a specific algorithm, hardware implementation and mapping. In this paper, we show a hiding countermeasure against voltage-based SCA that can be integrated into any implementation, without requiring modifications or tailoring to the protected module. We place a properly mapped Active Fence of ring oscillators between victim and attacker circuit, enabled as a feedback of an FPGA-based sensor, leading to reduced side-channel leakage. Our experimental results based on a Lattice ECP5 FPGA and an AES-128 module show that two orders of magnitude more traces are needed for a successful key recovery, while no modifications to the underlying cryptographic module are necessary.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) offers high density, non-volatility, scalability, high endurance and CMOS compatibility, making it a promising non-volatile memory (NVM) technology. However, due to the unique magnetic fabrication processes, different bit-cell architecture and periphery circuitry, they are susceptible to different manufacturing defects and faults compared to conventional CMOS-based memories. In this paper, a detailed variation-aware defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults.

This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.

Deep neural networks have shown great potential in solving difficult cognitive problems such as object recognition and classification. As a result, several neuromorphic circuits are designed and fabricated to perform various cognitive tasks. While these circuits are subjected to manufacturing defects and runtime failures, a proper testing method for neuromorphic circuits should exploit their inherent tolerance to inaccuracies in order to reduce the cost and complexity of post-manufacturing testing. This paper investigates structural and functional testing methodologies for neuromorphic circuits. The proposed test methodologies allow to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output accuracy or fault coverage.

The papers in this special section focus on emerging non-volatile memory technologies (NVM). Emerging NVM technologies have attracted significant interest in recent years because of the fast-growing performance and capacity demands on memory and storage in the big data era. Well known examples include the 3D XPoint memory and various NVDIMM hybrid memory technologies. They have shown potential towards larger memory and storage capacities with nearly zero leakage power, while extending memory/ system architecture design approaches. The unique characteristics of NVM technologies not only introduce new opportunities, but simultaneously create challenges to the designs at multiple levels of abstraction in computer systems, including those of device management, CPU cache management, memory/storage architecture, and system design. Furthermore, emerging NVM technologies also drive the development of techniques which perform computing operations in memory, i.e., processing-in-memory (PIM), by taking advantage of crossbar-based accelerators using NVMs. Thus, for the emerging NVM technologies, there is an urgent need for technology innovation, modeling, analysis, design, and application, ranging from the device-level to the system-level.

Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is 2.5× higher than in the super threshold domain while SER is 8× higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.

The manufacturing yield challenge of 3-D integrated circuit is one of the key obstacles in the industry adoption of 3-D integration based on through-silicon-vias (TSVs). The addition of spare TSVs to repair faulty functional TSVs (f-TSVs) is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a “dual-uniform” scenario in which both the placement and the defect probabilities of f-TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with nonuniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect-distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer-linear-programming formulation, respectively. By considering the tradeoff between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate for large on-chip memories as a zero-leakage, high-density and non-volatile alternative to the present SRAM technology. Since memories are the dominating component of a System-on-Chip, the overall performance of the system is highly dependent on that memories. Nevertheless, the high write energy and latency of the emerging STT-MRAM are the most challenging design issues in a modern computing system. By relaxing the non-volatility of these devices, it is possible to reduce the write energy and latency costs, at the expense of reducing the retention time, which in turn may lead to loss of data. In this article, we propose a hybrid STT-MRAM design for caches with different retention capabilities. Then, based on the application requirements (i.e., execution time and memory access rate), program data layout is re-arranged at compilation time for achieving fast and energy-efficient hybrid STT-MRAM on-chip memory design with no reliability degradation. The application requirements have been defined at function granularity based on profiling and compiler-level analysis, which estimate the required retention time and memory access rate, respectively. Experimental results show that the proposed hybrid STT-MRAM cache combined with profiling-based and compiler-level analysis for the data re-arranging, on average, reduces the write energy per access by 49.7%. At system level, overall static and dynamic energy of the cache are reduced by 8.1% and 44%, respectively, whereas, the system performance has been improved up to 8.1%.

In recent years, high availability and reliability of data storage systems (DSS) have been significantly threatened by soft errors occurring in storage controllers. Due to their specific functionality and hardware-software stack, error propagation and manifestation in DSS is quite different from general-purpose computing architectures. To the best of our knowledge, no previous study has examined the system-level effects of soft errors on the availability and reliability of DSS. In this paper, we first analyze the effects of soft errors occurring in the server processors of storage controllers on the entire storage system dependability. To this end, we implement the major functions of a typical data storage system controller, running on a full stack of storage system operating system, and develop a framework to perform fault injection experiments using a full system simulator. We then propose a new metric, storage system vulnerability factor (SSVF), to accurately capture the impact of soft errors in storage systems. By conducting extensive experiment, it is revealed that depending on the controller configuration, up to 40% of cache memory contains end-user data in which any unrecoverable soft errors will result in data loss (DL) in an irreversible manner. However, soft errors in the rest of cache memory filled by operating system and storage applications will result in data unavailability (DU) at the storage system level. Our analysis also shows that detectable unrecoverable errors on the cache data field are the major cause of DU in storage systems, while silent data corruptions in the cache tag and data fields are mainly the cause of DL in storage systems.

A rising trend is the use of multi-tenant FPGAs, particularly in cloud environments, where partial access to the hardware is given to multiple third parties. This leads to new types of attacks in FPGAs, which operate not only on the logic level, but also on the electrical level through the common power delivery network. Since FPGAs are configured from the software-side, attackers are enabled to launch hardware attacks from software, impacting the security of an entire system. In this article, we show the first attempt of a countermeasure against attacks on the electrical level, which is based on a bitstream checking methodology. Bitstreams are translated back into flat technology mapped netlists, which are then checked for properties that indicate potential malicious runtime behavior of FPGA logic. Our approach can provide a metric of potential risk of the FPGA bitstream being used in active fault or passive side-channel attacks against other users of the FPGA fabric or the entire SoC platform.

With the widespread use of electronic devices in embedding or processing sensitive information, new hardware security primitives have emerged to improve the shortcomings of traditional secure data storage. One of these solutions, the physically unclonable function (PUF), which is widely used for authentication and cryptography applications, extracts the unique and unclonable value from the circuit physical properties. However, a cloning attack on memory-based PUF has been demonstrated from the circuit back-side tampering, questioning its unclonable property and opening counterfeiting vulnerability in an untrusted supply chain. Spin transfer torque-magnetic random-access memory (STT-MRAM) is a promising technology due to its nonvolatility, scalability, and CMOS compatibility, therefore envisioned to be used in many embedded secure devices. In this paper, we reveal the vulnerability of existing STT-MRAM PUF solutions to back-side attacks by modeling different levels of tampering and their impact at electrical and logical levels. We propose a tamper resilient methodology for the STT-MRAM PUF design based on its switching properties. The resilience of the proposed solution to different levels of tampering and a 100% detection are confirmed with simulation results.

There has been a growing trend in recent years to outsource various aspects of the semiconductor design and manufacturing flow to different parties spread across the globe. Such outsourcing increases the risk of adversaries adding malicious logic, referred to as hardware Trojans, to the original design. The increased complexity of modern microprocessors increases the difficulty in detecting hardware Trojans at early stages of design and manufacturing. Therefore, there is a need for run-time detection techniques to capture Trojans that escape detection at these stages. In this paper, we introduce a machine learning-based run-time hardware Trojan detection method for microprocessor cores. This approach uses changepoint-based anomaly detection algorithm to detect the activation of Trojans that introduce abnormal patterns in the data streams obtained from performance counters. It does not modify the original microprocessor design to integrate on-chip monitoring sensors. We evaluate our method by detecting the activation of Trojans that cause denial-of-service, the degradation of system performance, and change in functionality of a microprocessor core. Results obtained using the OpenSPARC T1 core and an field-programmable gate array (FPGA) prototyping framework show that the Trojan activation is detected with a true positive rate of above 99% and a false positive rate of 0% for most of the implemented Trojans.

The spin-transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology with several distinctive advantages such as nonvolatility, high density, scalability, and almost unlimited endurance. It is, therefore, seen as a promising candidate to replace conventional on-chip memory technologies. However, as the technology scales, yield loss due to extreme parametric variations is becoming increasingly important for STT-MRAM because of its higher sensitivity to process variation as compared to CMOS memories. In addition, the parametric variations in STT-MRAM exacerbate its stochastic switching behavior, leading to both test time fails and reliability failures in the field. Since an STT-MRAM memory array consists of both CMOS and magnetic components, the system-level failures in STT-MRAM depend on variations in both these components. In this paper, we model the system-level parametric failures of STT-MRAM considering the spatial correlation among bit cells as well as the impact of peripheral components. The proposed approach provides realistic fault distribution maps and equips the designer to investigate the efficacy of different combinations of defect tolerance techniques for an effective design-for-yield exploration. The results show that the fault distribution and yield depend on the correlation coefficient and the temperature, which, in turn, determine the correct choice of defect tolerance scheme to be adopted to mitigate them to improve the yield.

Spin-transfer torque magnetic random access memory (STT-MRAM) is an emerging nonvolatile memory technology and a potential candidate to replace CMOS-based on-chip memories. However, the bit-cell switching behavior is stochastic, which is further exacerbated due to the temperature and the process variation (PV) effects, leading to reliability failures. The conventional solution to mitigate such errors is to define the write margin based on the worst case conditions, however, this results in an excessive margin that prevents the usage of STT-MRAM in fast memories. This paper proposes to significantly reduce the write margin of STT-MRAM with no impact on the read latency, which is achieved by clustering the cache lines based on the manufactured STT-MRAM parameters and then exploiting the proposed opportunistic write approach (i.e., terminating the write process before all bit switchings are completed). This approach is supported by a novel Lazy error correcting code (Lazy-ECC), which is based on the fact that error detection is much faster than correction. Hence, the errors can be detected quickly and all erroneous data can be reverted before they arrive critical parts of the system (e.g., commit stage or memory ports). A nonuniform adaptive ECC approach to manage PV and temperature-dependent retention and read disturb failures at runtime has also been proposed. The proposed approach enables a reliable use of STT-MRAM technology for fast cache applications.

A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.

For applications with stringent power budget, such as ultra low power systems and Internet of the things (IoT), power and energy are the most important constraints. It is shown that when the supply voltage is close to the threshold voltage of transistor, known as near threshold computing (NTC), the energy consumption is at its minimum range. However, by reducing the supply voltage not only the circuit performance decreases significantly, but aggravates various reliability mechanisms. Moreover, the performance variation due to process and runtime variation increases exponentially which makes the traditional margining, to address variability, very inefficient. In this paper, we address energy-efficient countermeasures to combat reliability challenges at NTC in order to guarantee resilient and energy-efficient system operation. We propose to partition a functional unit such as Arithmetic Logic Unit (ALU) into multiple smaller and faster functional units and power-gate them whenever they are not used for long time. Simulation results show that by applying the proposed method the energy efficiency of an ALU can be improved by up to 43.4% at NTC with multiple fold reliability improvements due to timing failures.

Printed electronics offers certain technological advantages over its silicon based counterparts, such as mechanical flexibility, low process temperatures, maskless and additive manufacturing process, leading to extremely low cost manufacturing. However, to be exploited in applications such as smart sensors, Internet of Things and wearables, it is essential that the printed devices operate at low supply voltages. Electrolyte gated field effect transistors (EGFETs) using solution-processed inorganic materials which are fully printed using inkjet printers at low temperatures are very promising candidates to provide such solutions. In this paper, we discuss the technology, process, modeling, fabrication, and design aspect of circuits based on EGFETs. We show how the measurements performed in the lab can accurately be modeled in order to be integrated in the design automation tool flow in the form of a Process Design Kit (PDK). We also review some of the remaining challenges in this technology and discuss our future directions to address them.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology, which is seen as a promising replacement for CMOS based on-chip memories. It has several distinctive advantages such as nonvolatility, high endurance, high density, CMOS compatibility and scalability among others. However, retention failure has emerged as a major reliability concern for this technology due to the large variations in retention time because of process variations and temperature effects. The conventional solution to mitigate retention failures is to use scrubbing at regular intervals to prevent accumulation of errors, based on the worst case retention time of the memory array. But this leads to large performance and energy overheads. In this work, we propose a process variation and temperature aware scrubbing technique, where we cluster the cache lines into different groups based on their retention times and use different scrubbing intervals for each of these groups. In addition, the scrubbing interval is adjusted at run-time based on the operating temperature, to guarantee target error rate requirements. Our results show that for a 512KB cache, a group size of 4 can reduce the performance and dynamic energy overheads of scrubbing by 97%, under the same error rate constraint.

Energy-constrained Systems-on-Chips (SoC) are becoming major components of many emerging applications, especially in the Internet of Things (IoT) domain. Although the best energy efficiency is achieved when the SoC operates in the near-threshold region, the best operating point for maximum energy efficiency could vary depending on operating temperature, workload, and the power-gating state (power modes) of various SoC components at runtime. This paper presents a lightweight machine-learning based scheme to predict and tune the SoC to the most energy efficient supply voltage at the firmware level during runtime, considering the impacts of temperature variation and power-gating of SoC components while meeting the performance and reliability requirements. Simulation results indicate that the proposed method can determine the most energy efficient supply voltage of a circuit with high-accuracy (RMSE = 7mV), while considering the runtime performance and reliability constraints.

One of the major challenges in device down-scaling is the increase in the leakage power, which becomes a major component in the overall system power consumption. One way to deal with this problem is to introduce the concept of normally-off instant-on computing architectures, in which the system components are powered off when they are not active. An associated challenge is the back-up and restoration of system states, which in turn can introduce additional costs that erode some of the gains. A promising alternative is the use of non-volatile storage elements in the System-on-Chip (SoC) design which can instantly power-down and retain their values. In this work, we show how we can design a normally-off SoC by exploiting non-volatile latches, flip-flops and registers. The idea is to design a hybrid architecture containing conventional CMOS bistables as well as different flavors of spintronic-based non-volatile storage elements, to balance performance, area, and energy efficiency.

As leakage increases proportionally with the technology downscaling, it becomes extremely challenging to manage to meet the total power budget. This is because, CMOS-based logic blocks can not be completely power-gated as their flip-flops always require a retention supply to hold the system states. Alternatively, their data can be stored in a separate memory during the standby mode, however, that results in a huge area and energy overhead. Spin Transfer Torque (STT) based nonvolatile flip-flops can offer normally-off/instant-on computing features to reduce leakage by complete power shut-down without the need to transfer and restore system states separately. The non-volatile component of such flip-flops can be easily shared for the overall design optimizations. In this paper, we design a unique multi-bit non-volatile flip-flop architecture using STT devices to reduce the area and energy costs associated with nonvolatile components. This architecture is developed based on the resource sharing principle using a custom design that enables the optimization for the area and energy consumption. Moreover, we have developed a framework in which we have replaced the conventional neighbor flipflops in the layout with our proposed multi-bit non-volatile designs. Results show that using our multi-bit flip-flop architecture, we improve the system-level area and energy by 26% and 14% in average, respectively, compared to the standard single-bit non-volatile flip-flop design.

The emerging Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate to replace conventional on-chip memory technologies due to its advantages such as non-volatility, high density, scalability and unlimited endurance. However, as the technology scales, yield loss due to extreme parametric variations is becoming a major challenge for STT-MRAM because of its higher sensitivity to process variations as compared to CMOS memories. In addition, the parametric variations in STT-MRAM exacerbates its stochastic switching behavior, leading to both test time fails and reliability failures in the field. Since an STT-MRAM memory array consists of both CMOS and magnetic components, it is important to consider variations in both these components to obtain the failures at the system level. In this work, we model the parametric failures of STT-MRAM at the system level considering the correlation among bit-cells as well as the impact of peripheral components. The proposed approach provides realistic fault distribution maps and equips the designer to investigate the efficacy of different combinations of defect tolerance techniques for an effective design-for-yield exploration.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate as a universal on-chip memory technology due to non-volatility, high density and scalability. However, high write energy and latency are major challenges in this memory technology due to the asymmetry and stochastic nature of the write operation. Typically, the write current is set for the minimum energy point, which can further impact the write latency. To mitigate these issues, we propose an adaptive write current scaling technique that adjusts the write current, and hence the write latency and energy based on the performance needs at run-time. Using this technique, optimal energy and performance points for write current are obtained using detailed device and system level analysis. Furthermore, we use runtime adaptation of write current by predicting the write access rate for the next execution phase. We evaluate the efficiency of the proposed approach on SPEC2000 applications for STT-MRAM-based L1 and L2-cache levels. The results show that the effective write latency of L1 and L2 is reduced by 52.4% and 55.7% with 7.6% and 1.4% area overheads, respectively, corresponding to the overall system performance optimization of 15.5% while the total memory energy consumption is increasing by only 3.2%.

Hardware Trojans have gained increasing interest during the past few years. Undeniably, the detection of such malicious designs needs a deep understanding of how they can practically be built and developed. In this work we present a design methodology dedicated to FPGAs which allows measuring a fraction of the dynamic power consumption. More precisely, we develop internal sensors which are based on FPGA primitives, and transfer the internally-measured side-channel leakages outside. These are distributed and calibrated delay sensors which can indirectly measure voltage fluctuations due to power consumption. By means of a cryptographic core as a case study, we present different settings and parameters for our employed sensors. Using their side-channel measurements, we further exhibit practical key-recovery attacks confirming the applicability of the underlying measurement methodology. This opens a new door to integrate hardware Trojans in a) applications where the FPGA is remotely accessible and b) FPGA-based multi-user platforms where the reconfigurable resources are shared among different users. This type of Trojan is highly difficult to detect since there is no signal connection between targeted (cryptographic) core and the internally-deployed sensors.

For monolithic heterogeneous integration, fast yet low-power processing and storage, and high integration density, the objective of the EU GREAT project is to co-integrate multiple digital and analog functions together within CMOS by adapting the Magnetic Tunneling Junctions (MTJs) into a single baseline technology enabling logic, memory, and analog functions, particularly for Internet of Things (IoT) platforms. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the progress in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT.

Multi-tenant FPGAs, in which 3rd parties have partial access to the FPGA fabric, are a rising usage trend in cloud and reconfigurable SoCs. This gives rise to new types of attacks in FPGAs, as shown in recent studies. These attacks can operate on the electrical level through the common power delivery network, making them very hard to isolate. Thus, software-controlled FPGA configuration can be exploited to insert hardware trojans, impacting the security of the entire system. The attacks can be separated into fault and side-channel attacks to either actively manipulate a system or quietly extract secret information. In this paper, we show the first attempt of countermeasures against these voltage fluctuation based attacks, by analyzing FPGA bitstreams for malicious logic, basically implementing an FPGA antivirus. We provide a way to check bitstreams for potentially malicious structures, by extending a combination of commercial and open-source tools.

The current practice in board-level integration is to incorporate chips and components from numerous vendors. A fully trusted supply chain for all used components and chipsets is an important, yet extremely difficult to achieve, prerequisite to validate a complete board-level system for safe and secure operation. An increasing risk is that most chips nowadays run software or firmware, typically updated throughout the system lifetime, making it practically impossible to validate the full system at every given point in the manufacturing, integration and operational life cycle. This risk is elevated in devices that run 3rd party firmware. In this paper we show that an FPGA used as a common accelerator in various boards can be reprogrammed by software to introduce a sensor, suitable as a remote power analysis side-channel attack vector at the board-level. We show successful power analysis attacks from one FPGA on the board to another chip implementing RSA and AES cryptographic modules. Since the sensor is only mapped through firmware, this threat is very hard to detect, because data can be exfiltrated without requiring inter-chip communication between victim and attacker. Our results also prove the potential vulnerability in which any untrusted chip on the board can launch such attacks on the remaining system.

Supply voltage scaling is an effective technique to reduce the power consumption of modern VLSI circuits. However, the scaling extent is often limited by variation-induced failures of on-chip memories, such as cache units. Hence, the memory components dictate the minimum voltage for the entire system below which reliable operation is not guaranteed. These failures can be permanent, which reduce the yield, or transient, such as soft-errors, impacting runtime operation. Both permanent and transient failures will significantly affect the overall energy-efficiency and hence, need to be addressed in order to achieve reliable low-voltage cache operation. This issue is more pronounced in the design of devices with a stringent energy budget, such as IoT applications. This paper studies different memory failure mechanisms across wide supply voltage range, and evaluates the disposable counter-measures such as error correcting codes and architectural techniques as well as the extent of their applicability for reliable and energy-efficient cache operation.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative technology for on-chip memories due to several advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Due to the emerging fabrication processes of magnetic layers in the fabrication of STTMRAM devices, they are more susceptible to manufacturing defects and have different failure mechanisms compared to conventional CMOS memories. This mandates specific fault modeling and development of proper test algorithms for high coverage testing of these memories in order to ensure correct functionality in the field. In this paper, a detailed defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults.

Automotive has become one of the most prevailing sectors of the modern semiconductor industry. Due to strict requirements for safety, reliability, and security the proposed test & repair solutions for automotive applications undergo a circumstantial verification before exploitation. Traditionally production defects and soft errors occurring in the operation mode were considered to be the main source of failures for System-on-Chips (SoC). Nevertheless, aging-induced faults especially in modern technology nodes also pose certain challenges for SoC lifetime and impact the overall Failure in Time (FIT) rate of the system. Meanwhile keeping hold of low FIT rate is one of the main criteria for reliability. In this paper, a comprehensive study on aging faults is conducted for FinFET memories and an efficient test & repair methodology is proposed that meets the automotive requirements and allows decreasing the FIT rate of the system.

Spin transfer torque magnetic random access memory is a promising candidate to replace CMOS based on-chip memories due to its advantages, such as nonvolatility, high density, and scalability. However, its stochastic switching and higher sensitivity to process variation compared to CMOS memories can significantly affect its performance, energy, and reliability. Although a few works exist which analyze the impact of process variation at the bit-cell level, such analysis at the system-level is missing. We have bridged this gap by developing a tool which can quantify the effect of stochasticity and process variations from the cell level to the overall memory system. The tool can perform a variation-aware design space exploration and memory configuration optimization for energy or performance while meeting reliability constraints. It also reports various failure rates and can evaluate the effectiveness of different error correcting code schemes. The results show that our framework can provide more realistic margins and the optimized variation-aware memory configuration could be significantly different from the conventional framework.

Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power overhead to predict the soft-error vulnerability of on-chip memory arrays as well as logic cores. The vulnerability prediction is based on signal probabilities (SPs) of a small set of flip-flops, chosen at design time, by studying the correlation between the soft-error vulnerability and the flip-flop SPs for representative workloads. We exploit machine learning to develop a predictive model that can be deployed in the system in software form. Simulation results on two processor designs show that the proposed technique can accurately estimate the soft-error vulnerability of on-chip logic core, such as sequential pipeline logic and functional units as well as memory arrays that constitute the instruction cache, the data cache, and the register file.

Run-time solutions based on online monitoring and adaptation are required for resilience in nanoscale integrated circuits, as design-time solutions and guard bands are no longer sufficient. Bias temperature instability-induced transistor aging, one of the major reliability threats in nanoscale very large scale integration, degrades path delay over time and may lead to timing failures. Chip health monitoring is, therefore, necessary to track delay changes on a per-chip basis over the chip lifetime operation. However, direct monitoring based on actual measurement of path delays can only track a coarse-grained aging trend in a reactive manner, not suitable for proactive fine-grain adaptations. In this paper, we propose a low cost and fine-grained workload-induced stress monitoring approach, based on machine learning techniques, to accurately predict aging-induced delay. We integrate space and time sampling of selective flip-flops into the runtime monitoring infrastructure in order to reduce the cost of monitoring the workload. The prediction model is trained offline using support-vector regression and implemented in software. This approach can leverage proactive adaptation techniques to mitigate further aging of the circuit by monitoring aging trends. Simulation results for realistic open-source benchmark circuits highlight the accuracy of the proposed approach.

In advanced technology nodes, bias temperature instability (BTI) has emerged as a prominent reliability concern. The worst-case effects of BTI occur during specific workload phases in which flip-flops (FFs) on a critical path do not switch their logic values for a long duration. These inactive FFs in the circuit experience accelerated workload-dependent static-BTI (S-BTI) stress. The aging effect of S-BTI for a few hours has been shown to be equivalent to one year of aging due to dynamic BTI, which can eventually cause circuit failure. The techniques available to mitigate S-BTI stress during standby mode of circuits are pessimistic, thereby limiting the performance of the circuit. To address this problem, we propose a runtime monitoring method to raise a flag when a timing-critical FF experiences severe S-BTI stress. To reduce the monitoring costs, we select a small representative set of FFs offline based on workload-aware correlation analysis and these selected FFs are monitored online for static aging phases. Our experiments conducted on two processors show that less than 0.5% of the total number of FFs is required to be selected as representative FFs for S-BTI stress monitoring. We also propose a low-overhead mitigation scheme to relax critical FFs by executing a software subroutine that is designed to exercise critical FFs.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a major challenge to test 2.5D ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this article, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. By considering the trade-off between test-application time, test-power budget, and test quality, the proposed technique provides test schedules with minimum test-application time under constraints on power consumption and fault coverage. Compared to previous work, the proposed technique can reduce test-application time by up to 53.4 for benchmark designs while achieving higher fault coverage. Since the loss in fault coverage due to multicast testing is extremely small, we can use top-off patterns to achieve full fault coverage for the dies at negligible additional cost.

Printed electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication and the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things. To use printed batteries or printed energy harvesters in the future, electrolyte-gated field-effect transistors (EGFETs) based on inorganic materials enable printed circuits requiring small supply voltage and low power. Since these applications need secure communication and/or authentication, it is imperative to embed security primitives for cryptographic key and identification purposes into the applications. Physical unclonable functions (PUFs) have been adopted widely to provide secure keys. In this paper, we present the design, simulation, fabrication, and measurements of a PUF based on EGFETs using inorganic inkjet PE. A comprehensive framework, including Monte Carlo simulations calibrated on real device measurements, is developed. Moreover, a multibit PE-PUF design is proposed to optimize area usage. Our simulation results show that the PE-PUF has ideal uniqueness (50.1%) and good reliability (89%). In addition, the proposed multibit PE-PUF reduces the area usage around 30%. The proposed PE-PUF was fabricated and the experimental results confirm that the PE-PUF can operate reliably as low as 0.5 V, and hence, it is a remarkable candidate to be utilized in low-power applications.

Energy-constrained microprocessor design plays an important role in many emerging Internet of Things platforms operating on harvested or limited energy budget. For this purpose, operating at the supply voltage corresponding to the minimum energy point (MEP) can achieve significant energy savings. However, the MEP voltage is highly dependent on the threshold voltage, the structure, and the activity rate of the circuit. This is more pronounced in pipelined processors as different pipeline stages have different structure with huge intrinsic activity rate variations. Therefore, the energy-saving is limited when only a single MEP voltage is chosen for the entire microprocessor. To address this issue, we propose a fine-grained MEP tuning technique, in which the individual pipeline stages are designed to operate at their MEPs, through per pipeline stage supply and threshold voltage tuning, by considering their activity rates. The proposed optimization is applied to two processors, FabScalar and OpenSPARC, and simulation results show that the proposed technique can improve the energy efficiency of both the cores by almost 50%. The improvement in energy efficiency is obtained at the cost of 6% performance and <; 2% area overhead.

Electromigration (EM) becomes a major reliability concern in 3-D integrated circuits (3-D ICs). To mitigate this problem, a typical solution is to use through-silicon via (TSV) redundancy in a reactive manner, maintaining the operability of a 3-D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this paper, we explore an alternative, more preferred approach to enhance the EM-related lifetime reliability of TSV grid, in which redundancy is used proactively to allow nonfaulty TSVs to be temporarily deactivated. In this way, EM wear-out can be extended by exploiting its recovery property. The proposed solution is based on two consecutive stages, in which TSV redundancy allocation and TSV repair are finalized at both design-time and runtime, respectively. Applied to 3-D benchmark designs, the recovery-aware proactive repair approach increases EM-related lifetime reliability (measured in mean-time-to-failure) of the entire TSV grid by up to 12× relative to the conventional reactive method, with similar area overhead. In addition, a runtime dynamic recovery approach is proposed to further improve EM-related lifetime reliability to account for stress variation across different chips and over the operational lifetime.

In advanced technology nodes, Bias Temperature Instability (BTI) has emerged as a prominent reliability concern. The worst-case effects of BTI occur during specific workload phases in which flip-flops on a critical path do not switch their logic values for a long duration. These inactive flip-flops in the circuit experience accelerated workload-dependent static-BTI stress. The aging effect of static BTI for a few hours has been shown to be equivalent to one year of aging due to dynamic BTI, which can eventually cause circuit failure. The techniques available to mitigate static-BTI stress during standby mode of circuits are pessimistic, thereby limiting the performance of the circuit. To address this problem, we propose a runtime monitoring method to raise a flag when a timing-critical flip-flop experiences severe static-BTI stress. To reduce the monitoring costs, we select a small representative set of flip-flops offline based on workload-aware correlation analysis and these selected flip-flops are monitored online for static aging phases. Our experiments conducted on two processors show that, less than 0.5% of the total number of flip-flops is required to be selected as representative flip-flops for S-BTI stress monitoring.

Post-silicon debug is the task of finding the bugs that could not be found before manufacturing. Electrical bugs are an important category of post-silicon bugs that are typically hard to debug due to complex interdependence of layout and netlist as well as their dependency to the running workload and environment. In this paper, we tackle the problem of debugging electrical bugs using trace buffers. Given an erroneous values captured in the trace buffer due to occurrence of an electrical bug, we try to identify the spatial and temporal location of the error. We have formulated the problem of debugging electrical bugs as a SAT problem and proposed a debugging method based on that. Moreover, we have shown that the existing signal selection methods for logical bugs that are typically trying to maximize signal restoration ratio (SRR) metric, do not perform better than random selection when debugging electrical bugs. On the other hands, utilizing a more sophisticated signal selection that is considering propagation of bit-flips due to electrical bugs is more effective.

Near threshold computing (NTC) through aggressive supply voltage scaling has the potential to significantly improve energy-efficiency. However, the increase in variation-induced timing errors is a major challenge in NTC. This can be addressed in the scope of approximate computing by selectively embracing non-important variation-induced timing errors. In this paper, we propose a framework to leverage the error tolerance potential of approximate computing for energy-efficient NTC designs. In our framework, statistical timing error analysis as well as structural and functional error propagation analysis is performed to identify the approximable portion of a design. Then, a mixed-timing logic synthesis is employed to improve energy-efficiency by embracing errors in the approximable portion of the design. Experimental results show that the proposed approach can improve the energy-efficiency of NTC designs by more than 30%.

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and can be fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. First two work packages of the project are presented in this paper. These packages are on logic synthesis that aims to implement Boolean functions with nano-crossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence of high fault densities and extreme parametric variations in nano-crossbar architectures.

The start-up value of SRAM cells can be used as the random number vector or a seed for the generation of a pseudo random number. However, the randomness of the generated number is pretty low since many of the cells are largely skewed due to process variation and their start-up value leans toward zero or one. In this paper, we propose an approach to increase the randomness of SRAM-based True Random Number Generators (TRNGs) by leveraging transistor aging impact. The idea is to iteratively power-up the SRAM cells and put them under accelerated aging to make the cells less skewed and hence obtaining a more random vector. The simulation results show that the min-entropy of SRAM-based TRNG increases by 10X using this approach.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate to replace CMOS based on-chip memories due to its advantages such as non-volatility, high density and scalability. However, its stochastic switching and higher sensitivity to process variation compared to CMOS memories can significantly affect its performance, energy and reliability. Although a few works exist which analyze the impact of process variation at the bit-cell level, such analysis at the system level is missing. We have bridged this gap in our work. Specifically, we quantify the effect of stochasticity and process variations from the cell-level to the overall memory system and perform a variation-aware memory configuration optimization for energy or performance while meeting reliability constraints. Our system-level variation-aware framework has been built on top of the well-known NVSim engine. The results show that our framework can provide more realistic margins and the optimized variation-aware memory configuration could be significantly different from the conventional framework.

Due to the stochastic switching behavior of the bit-cell in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), an excessive write margin is required to guarantee an acceptable level of reliability and yield. This prevents the usage of STT-MRAM in fast memories such as L1 or L2 caches. The excessive write margin of STT-MRAM can be reduced to a large extent by an opportunistic write (i.e., terminating the write process before all bit switchings are completed) and by reducing thermal stability factor. The bits with unfinished writes have to be processed by robust Error Correction Codes (ECCs). However, such coding schemes have relatively large decoding latencies, which increases the overall read latency significantly. Moreover, thermally induced retention failures can limit the applicability of such schemes. In this paper, we exploit the fact that error detection is much faster than correction. Therefore, the errors can be detected quickly and all erroneous data can be reverted before they arrive critical parts of the system (e.g., commit stage or memory ports). We also provide an adaptive approach to manage temperature-dependent retention failures at runtime. Hence, our proposed approach enables the use of STT-MRAM technology for fast cache applications.

Electromigration (EM) becomes a major reliability concern in three-dimensional integrated-circuits (3D ICs). To mitigate this problem, a typical solution is to use TSV redundancy in a reactive manner, maintaining the operability of a 3D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this work, we explore an alternative, more preferred approach to enhance the EM-related lifetime reliability of TSV grid, in which redundancy is used proactively to allow non-faulty TSVs to be temporarily deactivated. In this way, EM wear-out can be reversed by exploiting its recovery property. Applied to 3D benchmark designs, the recovery-aware proactive repair approach increases EM-related lifetime reliability (measured in mean-time-to-failure) of the entire TSV grid by up to 12X relative to the conventional reactive method, with less area overhead.

The reliability of digital integrated circuits is becoming the primary design concern in advanced technology nodes. The accelerated transistor aging mechanisms, such as Bias Temperature Instability, reduce the noise margin of memory cells leading to increased failure rate. Traditionally, error correction codes, such as Hamming code, are widely used to detect and correct transient errors in memory arrays, due to radiation-induced soft errors. In this work, we propose a new coding scheme which is able to reduce the overall aging rate of the memory arrays, by balancing the signal probabilities of the stored values. The optimal coding scheme is found with the help of an optimization technique which evolves a systematic Hamming code into an aging-aware non-systematic code. This technique is applicable to different memory arrays such as caches. The simulation results on different workloads show 45.2% reduction in aging induced Static Noise Margin (SNM) degradation compared to the conventional methods.

Spin Transfer Torque Magnetic RAM (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM in processor caches. However, STT-MRAM suffers from a high write latency and high write energy consumption which have to be addressed for energy-efficient on-chip caches. The non-volatility property of STT-MRAM can be relaxed by reducing the thermal stability factor to improve both the write latency and write energy of STT-MRAM. However, this leads to increase in retention failure and read disturb rates resulting in erroneous data stored in the cache. This problem can naturally be mitigated in the scope of approximate computing in which such errors can be tolerated at the application level. In this paper, we show how STT-MRAM technology can effectively be used for approximate computing by tuning technology and application parameters to achieve an acceptable level of correctness with significant gains. Results show that using our proposed approximate computing framework, the per-access write latency and energy can be improved up to 25% and 70%, respectively.

Due to the widespread use of FPGAs in many critical application domains, their security is of high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs), users can gain access, even remotely, to the reconfigurable fabric to implement custom accelerators. This access can expose new security vulnerabilities in the entire system through malicious use of the FPGA fabric. In the past, attacks on the power supply level required local access to the hardware. In this paper, we reveal a security vulnerability in FPGAs that allows a valid configuration to generate severe voltage fluctuations, which crashes the FPGA within a few microseconds. Moreover, the extent of this crash is so severe, that manual power-cycling is required to be able to access and use the system again. This vulnerability has been systematically exploited in two different generations of FPGAs, and a SoC containing an FPGA. Because this vulnerability can lead to severe security attacks in systems using FPGA-based accelerators, we also analyze its underlying mechanism, and discuss possibilities for mitigation.

With increasing temperature and current density, electromigration (EM) becomes a major interconnect reliability challenge in power distribution networks (PDNs) of three-dimensional integrated-circuits (3D ICs). In order to improve the EM reliability of power/ground (P/G) through-silicon-vias (TSVs), the conventional solution is to use larger TSVs in order to decrease the current densities. In this work we exploit the recovery effects for EM reliability improvement by periodically deactivating P/G TSVs. In order to predict EM-related lifetime for TSV accurately, a novel three-phase EM model is proposed with a focus on single damascene via-last process. Different from existing TSV EM models, the new TSV EM model considers the nucleation phase and the impacts of initial thermo-mechanical stress, which is significant for the TSVs in addition to this recovery effect modeling. Furthermore, a recovery-aware repair architecture is developed for EM reliability improvement. Applied to 3D benchmark designs, the proposed repair approach increases EM-related lifetime of the P/G TSV grid by 4.4X in average relative to the conventional TSV sizing method, with negligible area overhead.

Aggressive energy reduction is a mandatory requirement for many computing systems used in energy-constrained Internet of Things (IoT) platforms. Operating circuits at supply voltages close to the threshold voltage of the transistors, commonly known as near-threshold computing, is a promising approach to achieve such low energy goals. However, maintaining the resiliency at such low supply voltages is very challenging as the impacts of variability sources could be orders of magnitude larger compared the the nominal voltage. This mandates new design automation paradigms to ensure resiliency for aggressively voltage scaled circuits. In this work, we introduce design flows and strategies to improve the resiliency and energy efficiency of circuits at near-thresohold voltage region.

There has been a growing trend in recent years to outsource various aspects of the semiconductor design and manufacturing flow to different parties spread across the globe. Such outsourcing increases the risk of adversaries adding malicious logic, referred to as hardware Trojans, to the original design. In this paper, we introduce a run-time hardware Trojan detection method for microprocessor cores. This approach uses Half-space trees to detect the activation of Trojans that introduce abnormal patterns in the data streams obtained from performance counters. It does not require any additional hardware or the monitoring of a large number of internal signals. We evaluate our method by detecting the activation of Trojans that cause denial-of-service, the degradation of system performance, and change in functionality of a microprocessor core. Results obtained using the OpenSPARC T1 core and an FPGA prototyping framework show that Trojan activation is detected with true positive ratio of above 0.9 and a false positive ratio of below 0.1 for most of the implemented Trojans.

Spin Transfer Torque Magnatic Random Access Memory (STT-MRAM) has the potential to become a universal memory technology due to its various attractive features such as non-volatility, high density, CMOS compatibility and zero leakage. However, STT-MRAM suffers from high write latency and poor reliability compared to SRAM. This is primarily due to its stochastic nature of switching, which makes it not suitable for fast caches such as L1. The use of robust Error Correction Coding (ECC) with multiple bit correction capability to optimize the write margin and reliability results in large decoding latencies and large number of check bits. In this paper, we propose a new solution to exclude the high costs of using ECC in terms of decoding latency and storage overhead to be able to use STT-MRAM for fast caches. We exploit the fact that STT-MRAM poses asymmetric errors due to the nature of Magnetic Tunnel Junction (MTJ) cell, which makes ECC a pessimistic solution to address such errors. Therefore, efficient Systematic Unidirectional Error-Detecting Code (SEDC) is proposed to be adopted instead of conventional ECC combined with proper cache access mechanism to fetch correct data in case of error detection. Our proposed approach provides orders of magnitude better reliability and considerable performance improvement that makes STT-MRAM viable for fast-caches compared to the existing solutions.

With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. Therefore, without effective defect and fault tolerance for NV flip-flops, the manufacturing yield will be affected severely. In this paper, we propose a fault-tolerant NV latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. The simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with a considerably lower overhead than traditional approaches.

Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior in the near-threshold voltage region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power, and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than 1.95×.

Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales. The main impact of BTI on SRAM memory cells is the degradation of the static noise margin (SNM), which leads to a higher susceptibility to failures. A variety of techniques for mitigating the impact of BTI on caches have been proposed at architecture level. However, their considerable overheads limit the application of such techniques. Recent studies showed that the utilization of the cache capacity widely varies from one workload to another and even within a workload. When cache utilization is low, for the majority of the cells, the same value is stored for a very long period, which significantly degrades SNM due to BTI. In this paper, we propose a technique to dynamically adjust the cache size according to the running workload cache requirement by monitoring the cache miss rate. The unused cache capacity is power gated to increase the energy efficiency and mitigate aging of the entire cache. The experimental results show that the proposed technique reduces hold and read SNM degradation by up to 48.1% and 33.3%, respectively, at the cost of 2.0% performance penalty.

With increasing temperature and current density, electromigration (EM) becomes a major interconnect reliability concern for 3-D integrated-circuits (3-D ICs). In 3-D power delivery networks, local vias are used inside power/ground (P/G) through-silicon-vias (TSVs) for vertical power delivery, which are susceptible to EM effects. In order to improve the EM reliability of P/G TSVs, it is desirable to insert multiple local vias in each P/G TSV whereby the current density of each local via can be reduced. However, excessive local vias may consume too much routing area, which leads to exacerbated routing congestion and increased delay overhead. In this paper, we propose a design technique to handle this tradeoff between EM reliability of P/G TSVs and timing performance of 3-D ICs. By utilizing an integer-linear-programming formulation, the optimal local-via number in each P/G TSV can be determined to minimize the local via-induced routing congestion while satisfying the given requirement of EM reliability.

With technology scaling, conventional CMOS-based flip-flops can no longer efficiently cope with the increasing leakage power challenge. Therefore, various non-volatile flip-flop designs were recently introduced to reduce the static power consumption. However, these flipflop architectures employ non-volatile Magnetic Tunnel Junction (MTJ) storing devices only for backup, i.e. to save and restore the content before and after power gating. This limits their efficiency for aggressive power gating for effective power reduction. To overcome this limitation, we propose a novel Non-Volatile Non-Shadow flip-flop (NVNS-FF) using Spin Orbit Torque (SOT) based MTJ cells. In this design, we exploit the high speed, low energy and high-reliability features of SOT devices to employ them as active components of the flip-flop. This enables efficient normally-off computing by allowing very aggressive power gating for both short and long standby periods. Experimental results show that the NVNS-FF has similar energy and timing characteristics as conventional CMOS-based flip-flops in active mode, and at the same time it allows to reduce the static power by 5X compared to backup flip-flops.

Increasing wire delay and higher interconnect power consumption are major concerns for nanoscale CMOS ICs. Three-dimensional integrated circuits (3D ICs) based on through-silicon-vias (TSVs) appear to be a promising solution to overcome bottleneck in CMOS scaling. However, volume production and commercial exploitation of 3D ICs are not feasible before pressing concerns about heat dissipation and test cost, as well as manufacturing yield and resiliency challenges are adequately addressed. At present, interposer-based 2.5D ICs are being advocated as a precursor to 3D ICs. All the dies in a 2.5D or 3D IC must be adequately tested for product qualification. Moreover, the introduction of TSVs for both signal routing across multiple dies as well as power delivery network (PDN), imposes new challenges in terms of manufacturing yield and resiliency issues which should be addressed in both design and test flows. The purpose of this special session, consisting of a set of talks given by experts from the US, Asia and Europe, is to present the test and resiliency challenges faced for the 2.5D and 3D integrated circuits, and discuss the path to overcome such challenges.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a a major challenge to test 2.5 ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this work, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. Compared to previous work, the proposed technique can reduce testapplication time by 53:4% for benchmark designs while achieving higher fault coverage.

Fault injection is the de facto standard for evaluating the sensitivity of digital systems to transient errors. Due to various masking effects only a very small portion of the injected faults lead to system-level failures, and hence, too many faults have to be injected for achieving statistically meaningful results. At the same time, since the majority of injected faults will be masked, lots of simulation cycles will be wasted for tracking each and every injected fault separately. In this paper, we propose an opportunistic acceleration technique which evaluates the impact of multiple non-interacting faults in one workload execution. In case no failure is observed, this technique skips the evaluation of those individual faults which leads to a significant speedup. The experimental results on the Leon3 processor show that our proposed technique shortens the fault injection runtime by two orders of magnitude.

Radiation-induced soft errors are major reliability threat for VLSI systems fabricated using nanoscale technologies. While soft errors are generated due to device-level interactions, they could propagate at multiple levels and impair user-visible outputs. Hence, it is crucial to evaluate the impact of these errors using a combined knowledge of various layers in a cross-layer manner. Development of a fast and accurate soft error analysis requires a detailed information about underlying technology, functionality of the hardware implementation, the system micro-architecture and architecture, and also the running application characteristics. This paper justifies the importance of cross-layer soft error modeling and mitigation by showing how existing soft error modeling techniques at various abstraction levels could be coupled to form a fast and accurate cross-layer soft error modeling platform, and accordingly, how this platform can be exploited towards low-cost design for soft error reliability.

Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact the product time-to-market. In this paper, we propose a novel fault injection technique to evaluate the reliability of a computing system running a software at early design stage where the hardware architecture is not completely defined yet. The proposed approach efficiently operates on the original source code of the software in order to inject transient faults in the data or the instructions. To be accurate and to achieve a better characterization of the system, we simulate faults occurring in the system memory units such as the data cache and the RAM by developing a system emulator. To validate our approach, we compare the simulation results to those obtained with an FPGA-based fault injector. The similarity of the results proves the accuracy of our approach to evaluate system reliability with a gain in the execution time and without requiring a fully defined hardware system.

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of arithmetic and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of "Emerging Computing Models" or "Computational Nanoelectronics", more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.

Due to recent technology scaling trends and increased circuit complexity, process and runtime variabilities are becoming major threats for correct circuit operation. Among these, transient voltage fluctuations appear to be the most critical issue, accounting for the biggest component of timing margin, at increased cost. As various design and workload parameters have an impact on voltage fluctuations, they need to be fully understood in order to design efficient countermeasures and margining. FPGAs are predestined for this analysis by allowing more control over such experiments at lower cost than ASICs. Even more, they highly suffer from the same issues, which are typically only handled by excessive and over-pessimistic timing margining built into the mapping tools. In this work, we implemented and calibrated sensors in configurable logic appropriate to observe delay changes caused by transient voltage fluctuations. We place them at multiple locations on the chip to evaluate temporal and spatial changes in timing margin due to different workload-characteristics. This analysis provides useful insights to designers for application mapping and workload scheduling.

Multi-port memories are widely used as shared memory, such as register files, in a microprocessor system, and its number of ports and capacities are significantly increasing with every product generation. However, with technology advancements, multi-port memories are facing severe challenges due to their bit-cell leakage and scalability, as well as reliability issues due to increase in design complexity. In this paper, we design a novel multi-port memory architecture in which we employ emerging Spin Orbit Torque (SOT) magnetic devices as a storing component because of its several beneficial attributes such as non-volatility, scalability, zero-leakage, almost infinite endurance, low access latency, low area and immunity to soft-errors. Moreover, due to separate read and write current paths in these devices, simultaneous read and write operations can be performed on the same cell while maintaining data integrity. In our proposed architecture, we have demonstrated that with this characteristic of SOT, the read-write contention can be resolved inherently at the device-level, which can simplify the overall multi-port design. Experimental results show that our proposed multi-port design has low access latency, and high energy efficiency with negligible area overhead.

Power/energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultra-low power and energy-harvested systems. Aggressive voltage scaling and in particular Near-Threshold Computing (NTC) is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior at near threshold region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than 3X.

Energy constrained systems become the cornerstone of emerging energy harvested or battery-limited applications in Internet of Thing (IoT) platforms. A promising approach is to operate at near threshold voltage ranges, which can significantly reduce energy per operation. However, due to increased sensitivity to variations and reduced noise margin at low voltages, resiliency becomes a major challenge. In this paper we provide a cross layer approach, from compiler all the way to circuit design, to maximize the energy efficiency as well as the resiliency of functional units. The key idea is to identify the instructions which become timing critical at low voltages and address them by a combination of circuit redesign, multi-cycle execution and code replacement. This allows us to significantly reduce timing failures and at the same time limit leakage energy, which becomes considerable at low voltages. This approach enables resilient and energy efficient operation in a wide voltage range to trade off energy and performance.

Radiation-induced soft errors are growing reliability concerns, especially in mission- and safety-critical systems. A variety of software-based fault tolerant techniques have widely been proposed and used to mitigate soft errors at the application-level. Such techniques are typically evaluated using statistical fault injection at software-visible variables of the system as fault injection at higher levels of abstraction is much faster than logic-level or Register Transfer Level (RTL). Recent studies revealed that software-based fault injection techniques are not accurate for analyzing soft errors originating in flip-flops. However, the effectiveness of such techniques for evaluation of the entire processor including register-files and cache arrays are not studied yet. In this paper, we comprehensively study the soft error rate of several workloads and their protected version using software-based fault tolerance by performing detailed error generation and propagation analysis at hardware-level. Our detailed experimental analysis shows that there is no significant correlation between the results of hardware- and software-based fault injection for the effectiveness of software-based fault tolerance. Furthermore, software-based fault injection cannot accurately model the relative improvement provided by fault tolerant software implementation, and hence, its results could be misleading.

Near threshold computing (NTC) has the potential to reduce the energy consumption by orders of magnitude. However, NTC designs suffer from a higher sensitivity to process variation and substantial performance degradation. In NTC, process variation affects the delays of different pipeline stages significantly, resulting in energy-inefficient designs. In this paper, we propose an energy-efficient variation-aware processor pipeline optimization, in which the pipeline stages are balanced by considering the impact of process variation during earlier design phases. This can lead to a well-balanced design and significant improvement in energy-efficiency. For this purpose, we employ an iterative variation-aware synthesis flow in which the synthesis tool is provided with variation information. Since the impact of process variation is considered during synthesis, our technique can improve the energy-efficiency by avoiding pessimistic guard band. Simulation results show that our technique can improve the energy-efficiency of OpenSPARC and FabScalar cores by 55% and 85%, respectively.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM due to its low leakage and scalability advantages. In fact, although being more energy-efficient than SRAM, STT-MRAM caches at higher levels (e.g. L3) still incur a high energy consumption due to 1) high leakage in their read and write circuits and 2) high dynamic write energy in their bit-cells. To address this problem, we propose a novel normally-off STT-MRAM cache that exploits the fact that most applications access zero-byte patterns very frequently. In this architecture, writing of zero-bytes is avoided to reduce write energy. In addition, all read and write circuits are by default power gated (i.e. normally-off) to reduce leakage power. Then, dynamically at runtime, only those circuits required for the ongoing operation are activated. Our evaluations for an L3-cache of a multi-core microprocessor show that this approach reduces the energy consumption by 60% compared to state-of-the-art, while its impact on performance is negligible.

The approximate computing paradigm can be leveraged to exploit the intrinsic error resilience of many applications to enable highly efficient memory implementations. Most emerging memory technologies have a wide range of performance/power/reliability trade-offs which can be exploited in fault tolerant approximate computing. In this work, we use approximate computing to tolerate the increased retention failure rate caused by relaxing the thermal stability factor of Spin-Transfer Torque Magnetic RAM (STT-MRAM) to enable fast and energy efficient STT-MRAM cache memories for image applications.

As technology scales deep into nanometer era, power and energy have become major design constraints, especially for energy-harvested and similar ultra-low power systems, such as embedded processors, remote sensors and implantable devices for the Internet of Things (IoT). Aggressive supply voltage scaling is one of the most efficient ways of reducing power and energy for digital circuits. Near-threshold computing (NTC), in which the supply voltage is close to the threshold voltage of the transistor, can provide a very high energy efficiency (10X or higher) compared to the traditional super-threshold region at the cost of significant (>10X) increase in time to complete a task. However, NTC can come with some major challenges such as decreased functional margins in various circuit elements and greatly increased sensitivity to process variations. To ensure correct functionality in the field, testing of NTC circuits faces some serious challenges, and possibly requires a paradigm shift from conventional testing methods.

Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power overhead to predict the soft-error vulnerability of on-chip memory arrays. The vulnerability prediction is based on signal probabilities (SPs) of a small set of flip-flops, chosen at design time, by studying the correlation between the soft-error vulnerability and the flip-flop SPs for representative workloads. We exploit machine learning to develop a predictive model that can be deployed in the system in software form. Simulation results on two processor designs show that the proposed technique can accurately estimate the soft-error vulnerability of on-chip memory arrays that constitute the instruction cache, the data cache, and the register file.

Field programmable gate arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them. External devices like thermal chambers are usually used to heat up the chip to a desired temperature in order to apply the test. However, there are many limitations for these external devices, which make the thermal-aware testing of the FPGA a challenging process. In this paper, thermal-aware testing of FPGAs using built-in self-heating is presented, in which the internal resources of FPGA are used to build controlled self-heating elements (SHEs). These controlled SHEs are distributed across the FPGA and integrated with the test scheme to generate the required temperature profile for testing, and thus no external devices for heating up the FPGA are needed. We present two different categories of SHEs integration techniques for different testing purposes. The first one is for built-in self-test, and the second one is for application-dependent testing. The techniques are applied on representative test cases. The experimental results show that a wide range of maximum chip temperatures can be achieved (from 50 °C up to 125 °C on Virtex-5 FPGA) with a high accuracy (±1 °C).

Radiation-induced multiple event transients (METs) are expected to become more frequent than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a fast and accurate layout-based soft error rate (SER) assessment technique with consideration of both SET and MET fault models is presented. Despite existing techniques in which the adjacent MET sites are extracted from a logic-level netlist, we conduct a comprehensive layout analysis to obtain MET adjacent cells. Experimental results reveal that the layout-based technique is the only viable solution for identification of the adjacent cells as netlist-based techniques considerably underestimate the overall SER. Furthermore, by identifying the most vulnerable adjacent cells and increasing their physical distance in the layout using local adjustment rules, we are able to considerably reduce the overall SER without imposing any area and performance penalty.

Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt-induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A consequence of voltage droop is usually an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, also known as guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For dynamic voltage-frequency to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop due to pattern-dependent IR drop based on inputs to the chip at runtime. Moreover, we reduce the amount of data needed for accurate prediction by using correlation-based feature selection. Several benchmarks from ITC'99 and International Work on Logic and Synthesis'05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present the hardware design and synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits.

Soft error is nowadays a major reliability issue for nanoscale VLSI, and addressing it during high-level synthesis is essential to improve the efficiency of error mitigation. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables and operations have non-uniform soft error vulnerabilities, we propose a novel reliability-aware allocation and binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive vulnerability analysis at the behavioral level by considering error propagation and masking in both control and data flows. Then the optimizations based on integer linear programming, as well as heuristic algorithm, are employed to incorporate the behavioral vulnerabilities into the register and functional unit binding phases to achieve cost-efficient error mitigation. The experimental results reveal that compared with the previous techniques which ignored behavioral vulnerabilities, the proposed approach can achieve up to 85% reliability improvement with the same amount of area budget in the RTL design.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising memory technology because of its advantageous features, such as nonvolatility, scalability, high density, zero-leakage, and CMOS compatibility. However, one of its major drawbacks is the high overall energy consumption. To make matters even worse, the write process in STT-MRAM is of stochastic nature, i.e., the completion of a write operation is nondeterministic. However, if the read/write completion could be detected on the fly (i.e., dynamically) and the respective components could be turned-OFF immediately, the energy consumption can be reduced by a large extent. Therefore, we propose a technique where the read and write completion signals are generated asynchronously on the fly using a self-timed bitwise technique. With this approach, the memory consumes power only when it is in the actual operational mode. Experimental results show that this technique significantly reduces the energy consumption of read and write operations with negligible area overhead.

Radiation-induced multiple bit upsets (MBUs) are a major reliability concern in nanoscale technology nodes. Occurrence of such errors in the configuration frames of a field-programmable gate array (FPGA) device permanently affects the functionality of the mapped design. Periodic configuration scrubbing combined with a low-cost error correction scheme is an efficient approach to avoid such a permanent effect. Existing techniques employ error correction codes with considerably high overhead to mitigate MBUs in configuration frames. In this paper, we present a low-cost error-detection code to detect MBUs in configuration frames as well as a generic scrubbing scheme to reconstruct the erroneous configuration frame based on the concept of erasure codes. The proposed scheme does not require any modification to the FPGA architecture. Implementation of the proposed scheme on a Xilinx Virtex-6 FPGA device shows that the proposed scheme can detect 100% of MBUs in the configuration frames with only 3.3% resource occupation, while the recovery time is comparable with the previous schemes.

Fast and accurate soft error vulnerability assessment is an integral part of cost-effective robust system design. The de facto approach is expensive fault simulation or emulation in which the error is injected in random bits and cycles, and then the effect is simulated for millions of cycles. In this paper, we propose a novel alternative approach to obtain the soft error vulnerability by integrating transient error propagation in an event-driven gate-level logic simulator which captures the combined effect of various masking factors. By carefully combining various generated errors at different cycles, in one pass all the error generation and propagation effects across all bits and all cycles are analyzed. This enables us to drastically reduce the runtime while maintaining the accuracy compared to statistical fault injection.

With CMOS technology downscaling into the nanometer regime, the reliability of SRAM memories is threatened by accelerated transistor aging mechanisms such as Bias Temperature Instability (BTI). BTI leads to a considerable degradation of SRAM cell Static Noise Margin (SNM), which increases the memory failure rate. Since BTI is workload dependent, the aging rates of different cells in a memory array are quite non-uniform. To address this issue, a variety of bit-flipping techniques has been proposed to decrease the SNM degradation by balancing the signal probabilities of the cells. However, existing bit-flipping techniques impose too much area and power overhead as at least an additional column is required to store the inversion flags. In this paper, we propose a low cost self-controlled bit-flipping technique which inverts all bit positions with respect to an existing bit. This technique is applied to a register-file and cache units of an embedded microprocessor. Our simulation results show that the reliability of the proposed technique is similar to that of existing bit-flipping techniques, while imposing 64% less area overhead.

Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated-Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of P/G TSVs will change the voltage of each node in the power grid, which also impacts the delays of the connected gates. Thus, it is necessary to consider the combined effect on delay variation during the P/G TSV planning. In this work, we propose a methodology using Mixed-Integer-Bilinear-Programming (MIBLP) to optimize this delay variation by a refined P/G TSV allocation. Taking into account the impact of thermal stress as well as voltage drop on the circuit delay, we optimally plan the P/G TSVs to minimize the circuit delay for different keep-out zones (KOZs) and PDN pitches.

Technology scaling advancement coupled with operational and environmental effects make embedded memories more vulnerable to both manufacturing and transient errors including multi-bit upsets. Conventional error correcting codes incur high latency, area, and power overheads to correct multi-bit errors. In this paper, we propose Embedded Erasure Coding (EEC), a low-cost technique that can correct multi-bit errors with low overheads. This technique employs interleaved parity bits to provide a fast and low-cost multi-bit error detection. Using the erasure coding concept, the error correction is done by reconstructing the contents of the erroneous cache blocks within each cache set. Our proposed technique trades the performance for higher reliability by reserving a part of the cache (e.g. one way) to store the erasure codes. Our simulation results show that EEC provides high reliability (100% error detection and correction) with lower area overhead as compared to other state-of-the-art techniques while imposing negligible performance overhead (3%).

System reliability becomes one of the major design concerns in nanoscale VLSI technologies. To cope with the increasing design complexity and the challenge of cost-efficient reliability improvement, modular and hierarchical optimizations are essential in the design space exploration. In this paper a novel scheduling and binding approach is proposed to investigate the potentials of reliability enhancement in high level synthesis. Inspired by the observation that the timing resource within individual clock cycle can be redistributed to maximize reliability, we propose a reliability-aware operation chaining technique, considering both the behavioral operation vulnerabilities and RTL reliability-cost tradeoffs in functional units. Using a characterized RTL component library regarding soft error, the experimental results show that compared to the traditional chaining, with the same timing constraint the proposed technique can generate the RTL with 3X reduction of the system failure rate, while introducing only 15% area and 16% power overhead.

Bias Temperature Instability (BTI)-induced transistor aging degrades path delay over time and may eventually induce circuit failure due to timing violations. Chip health monitoring is therefore necessary to track delay changes on a per-chip basis. We propose a method to accurately predict the fine-grained circuit-delay degradation with minimal area and performance overhead. It re-uses on-chip design-for-test (DfT) infrastructure to track the severity of run-time stress by periodiclly capturing system state and compacting it using a multiple input signature register (MISR). The captured stress information is fed to a software-based prediction model in realtime. The prediction model is trained offline using support vector regression. Aging prediction based on run-time stress monitoring can be used to proactively activate aging mitigation techniques. Experimental results for benchmark circuits highlight the accuracy of the proposed approach.

Bias Temperature Instability (BTI) affects both timing and functionality of Flip-Flops (FFs). In a typical processor, a considerable portion of FFs always operate under severe BTI stress independent of the running workload. This leads to a serious timing degradation in these FFs, and to avoid timing violations in field, they mandate a large aging guardband (timing margin). In this paper, we propose a method to mitigate the BTI-induced aging of such FFs via transistor sizing optimization. The optimized FFs are more resilient against BTI stress compared to the original ones. The imposed overall leakage is negligible, and the area of the optimized FFs is similar to the original ones in order to facilitate the replacement of the original FFs with optimized alternatives in the circuit layout. Simulation results show that incorporating the optimized FFs in a processor can reduce the timing guardband of the processor by 22.8% compared to the original design, which translates into prolonged lifetime and more reliability.

Emerging non-volatile Magnetic Random Access Memory (MRAM) is a promising alternative for replacement of SRAM-based configuration bits of conventional FPGAs. However, the costs of reconfiguration in MRAM-FPGAs are typically higher than SRAM-FPGAs due to the high write latency and energy of MRAM. In this paper, a novel energy-efficient partitioning technique is proposed to minimize the number of reconfigurations and content updates for dynamic reconfigurable MRAM-FPGAs. The simulation results show that the proposed technique significantly reduces the reconfiguration energy (up to 68.1% on average) as compared to the existing partitioning techniques.

Run-time solutions based on real-time monitoring and adaptation are required for resilience in nanoscale integrated circuits as design-time solutions and guard bands are no longer sufficient. Bias Temperature Instability (BTI)-induced transistor aging, one of the major reliability threats in nanoscale VLSI, degrades path delay over time and may eventually induce circuit failure due to timing violations. Chip health monitoring is, therefore, necessary to track delay changes on a per-chip basis. Chip-monitoring techniques based on actual measurement of path delays can only track a coarse-grained aging trend in a reactive manner. In this paper, we show how the on-chip design for test (DfT) infrastructure can be reused in order to perform fine-grain workload-induced stress monitoring for accurate aging prediction. The captured stress information is fed to a prediction model in real-time. The prediction model is trained offline using support-vector regression and implemented in software. This approach can leverage proactive adaptation techniques to mitigate further aging of the circuit by monitoring aging trends. Simulation results for realistic open-source benchmark circuits highlight the accuracy of the proposed approach.

The manufacturing yield challenge of three-dimensional integrated circuit (3D ICs) is one of the key obstacles in the industry adoption of 3D integration based on through-silicon-vias (TSVs). The addition of spare TSVs to repair faulty functional TSVs is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a “dual-uniform” scenario in which both the placement and the defect probabilities of functional TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with non-uniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect-distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer-linear-programming formulation, respectively. By considering the trade-off between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work.

High write latency and high write energy are the major challenges in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) design. The write operation in STT-MRAM is of stochastic nature. Therefore, it requires a very long timing margin to maintain an acceptable level of reliability and yield. Traditionally, Error Correction Codes (ECCs) are used to reduce the timing margin in STT-MRAM. However, they impose high storage and latency overheads. In this paper, we propose a low-cost architecture-level technique to significantly reduce the amount of required timing margin. This technique employs a handshaking protocol between the memory and its controller to dynamically determine the write latency at run-time. Our simulation infrastructure comprehensively models the combined effect of process variation and stochastic write behavior at circuit-level and abstracts it to architecture-level. The simulation results show that the proposed technique not only considerably reduces the write error rate but also improves the overall system performance on average by 15.4% compared to existing solutions.

While the notion of self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing, we are seeing the emerging need for self-awareness in the context of complex Systems-on-Chip that must address the often conflicting requirements of performance, resiliency, energy, cost, etc. in the face of highly dynamic operational behaviors coupled with process, environment, and workload variabilities. Unlike traditional Systems-on-Chip (SoCs), self-aware SoCs must deploy an intelligent co-design of the control, communication, and computing infrastructure that interacts with the physical environment in real-time in order to modify the systems behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). Self-aware SoCs require a combination of ubiquitous sensing and actuation, health-monitoring, and self-learning to enable the SoCs adaptation over time and space. This special session targets self-learning and self-awareness in two domains. The first one is a self-learning runtime reliability prediction approach by reusing Design-for-Test (DfT) infrastructure. The other one discusses real-time systems and applications to wireless communication, signal processing and control.

Accelerated transistor aging is one of the major unreliability sources at nano-scale technology nodes. Aging causes the circuit delay to increase and eventually leads to timing failures. Since aging is dependent on various factors such as temperature and workload, the aging rates of different components of the circuit are non-uniform. However, timing failures start to occur once the most-aged part fails to meet the timing constraint. In this paper, we present a cross-layer aging mitigation methodology from device level up to architecture level by balancing the delays of different parts of the design at the desired lifetime rather than at design time. Our results show that the proposed approach can efficiently prolong the system lifetime with a negligible impact on area and power.

Radiation-induced Multiple Bit Upsets (MBUs) are major reliability concerns for embedded memory arrays fabricated in advanced technology nodes. Although various error correction techniques with different attributes have been developed, there has been limited efforts towards pure MBU detection. In this paper, we present stepped parity, a cost-efficient technique to detect MBUs in memory arrays. In this technique, each data bit is associated with several parity bits in a way that the most common MBU patterns could be detected by at least one of the parity bits. The experimental results reveal that the stepped parity reduces the area and power overheads of the stat-of-the-art solutions by about 30% for a given reliability constraint.

As CMOS technologies enter nanometer scales, maintaining the microprocessor reliability becomes a major design challenge. In particular, accelerated transistor aging is a serious reliability concern, as it considerably reduces the operational microprocessor lifetime. To address this issue, in this work cross-layer solutions for aging modeling and simulation as well as mitigation are investigated and proposed, to be able to co-optimize reliability together with the traditional design constraints such as power, performance, and cost. Therefore, the knowledge from several abstraction layers, ranging from circuit to architecture-level, are exploited for cost-effective aging-aware micro-architecture design. The detailed simulations and experimental analysis performed in this work show the benefits of this approach over state-of-the-art single-layer solutions.

Improvements in chip manufacturing technology, driven by high degree of integration due to small device sizes and additional complex functionalities enabled by heterogeneous integration, have propelled an astonishing growth of computing systems. While the pervasiveness of these systems enables emerging application domains, however, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and resiliency of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process, while other factors appear because of high frequencies and nanoscale features. This paper overviews the vision by some of the key industrial players regarding the emerging resiliency challenges faced at the extreme nanoscale technologies.

Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints.

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as nonvolatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this paper, we provide a very detailed analysis of SOT-MRAM at both the circuit-and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybrid-combination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60% while the performance increases by 1% compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is 27× smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65 nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.

Process together with runtime variations in temperature and voltage, as well as transistor aging, degrade path delay and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential, and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these sensors and the large number of critical paths in today's IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging- and variationaware representative path selection technique based on machine learning that allows to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to delay variations. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical-path delay based on the selected representative paths.

Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to bias temperature instability and hot carrier injection. As a result, device delays increase over time, reducing the mean time to failure (MTTF) and hence lifetime of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically most critical. However, also the decoding stages can become aging critical and limit the microprocessor lifetime, as we will show in this work. Therefore, we propose a novel aging-aware instruction set-encoding methodology (ArISE) that improves the instruction encoding iteratively using a heuristic algorithm. In addition, the switching activities of the affected memory elements are considered in order to co-optimize lifetime and energy efficiency. Our experimental results show that MTTF of the decoding stages can be improved by 2.3× with negligible implementation costs.

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as non-volatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this work, we provide a very detailed analysis of SOT-MRAM at both circuit- and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that with a hybrid-combination of SRAM for the L1-cache and SOT-MRAM for the L2-cache the energy consumption can be reduced by 63 % in average while the performance can be increased by 1 %. In addition, the memory area is 43% lower compared to an SRAM-only configuration.

Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to Bias Temperature Instability and Hot Carrier Injection. As a result, device delays increase over time reducing the Mean Time To Failure (MTTF) of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically most critical. However, also the decoding stages can become aging-critical and limit the microprocessor lifetime, as we will show in this work. In this paper, we propose a novel aging-aware instruction set encoding methodology (ArISE), that improves the instruction encoding iteratively using a heuristic algorithm. Our experimental results show that MTTF of the decoding stages can be improved by 1.93x with negligible implementation costs.

In the deep nanoscale regime, process and runtime variations have emerged as the major sources of uncertainty and unpredictability in circuit operation. Static mitigation approaches do not consider the dependence of variations on workload and chip usage, while adaptive techniques do not incorporate detailed circuit-level information. We propose a fine-grained adaptive technique in which machine learning is exploited to perform circuit clustering and obtain a representative for each cluster. By monitoring the representative in each cluster at runtime, performance variations in the entire cluster can be tracked such that appropriate fine-grained adaptation can be applied to each cluster. Experimental results for ISCAS'89, IWLS'05, and ITC'99 benchmarks as well as the LEON processor show that the proposed approach introduces negligible overhead significantly extends circuit lifetime, facilitates higher operating frequencies, and reduces the leakage power.

As soft error is a major reliability issue for nanoscale VLSI, addressing it during high level synthesis can have a significant impact on the overall design quality. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables have nonuniform soft error vulnerabilities, we propose a novel reliability-aware register binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive variable vulnerability analysis at the behavioral level, by considering error propagation and masking in both control and data flow. Then an optimization based on integer linear programming is used to incorporate vulnerabilities into the register binding phase with a selective register protection scheme. The experimental results reveal that the proposed technique can achieve significant soft error mitigation (60% coverage of the total vulnerabilities) with a small portion (20%) of register protection.

This paper presents a comprehensive analysis of radiation-induced soft errors of SRAMs designed in SOI FinFET technology. For this purpose, we propose a cross layer approach starting from a 3D simulation of particle interactions in FinFET structures up to circuit level analysis by considering the layout of the memory array. This approach enables us to consider the effect of different factors such as supply voltage and process variation on Soft Error Rate (SER) of FinFET SRAM memory arrays. Our analysis shows that proton-induced soft errors are becoming important and comparable to the SER induced by alpha-particles especially for low supply voltages (low power applications). Moreover, we observe that the ratio of Multiple Bit Upset (MBU) to Single Event Upset (SEU) for alpha-particle radiation is much higher than that of proton.

Multiple bit upsets due to radiation-induced soft errors are a major concern in nanoscale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. The combination of error correction schemes and configuration scrubbing is an efficient approach to avoid such permanent errors. Existing solutions exploit coding techniques with considerably high overhead to protect configuration frames against multiple bit upsets. In this paper, we propose a generic scrubbing scheme which reconstructs the erroneous configuration frame based on the concept of erasure codes. Our proposed scheme does not require any changes to the FPGA architecture. Experimental results on a Xilinx Virtex-6 FPGA device show that the proposed scheme achieves error recovery coverage of 99.30% with only 3% resource occupation while the mean time to repair is comparable with previous schemes.

Promising advantages offered by resistive NonVolatile Memories (NVMs) have brought great attention to replace existing volatile memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in Field-Programmable Gate Arrays (FPGAs). One major limitation of employing NVMs in FPGAs is significant power and area overheads imposed by the Peripheral Circuitry (PC) of NVM configuration bits. In this paper, we investigate the applicability of different NVM technologies for configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). The proposed PCM-based architecture has been evaluated using different technology nodes and it is compared to the SRAM-based FPGA architecture. Power and Power Delay Product (PDP) estimations of the proposed architecture show up to 37.7% and 35.7% improvements over SRAM-based FPGAs, respectively, with less than 3.2% performance overhead.

Spin Transfer Torque (STT) memory is an emerging and promising non-volatile storage technology. However, the high write current is still a major challenge which leads to a huge power consumption of the memory. Due to an inherent torque asymmetry of the Magnetic Tunnel Junction (MTJ) device employed in STT memories, the switching time between parallel to anti-parallel and anti-parallel to parallel magnetization is significantly different. Hence, the write latencies for writing `0' and `1' are also considerably different. In this paper, we propose a technique called Asynchronous Asymmetrical Write Termination (AAWT) which utilizes this asymmetrical behavior to terminate the write operations asynchronously and as a result significantly reduces the write power consumption. Furthermore, we present two different AAWT implementations to determine the actual write termination times. The first one makes use of a clock signal and the second one employs a self-timing approach based on an internal delay element. As shown by our experimental results, AAWT can reduce the total write energy by 30% in average with a negligible area overhead.

Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.

Transistor aging, mostly due to Bias Temperature Instability (BTI), is one of the major unreliability sources at nano-scale technology nodes. BTI causes the circuit delay to increase and eventually leads to a decrease in the circuit lifetime. Typically, standard cells in the library are optimized according to the design time delay, however, due to the asymmetric effect of BTI, the rise and fall delays might become significantly imbalanced over the lifetime. In this paper, the BTI effect is mitigated by balancing the rise and fall delays of the standard cells at the excepted lifetime. We find an optimal tradeoff between the increase in the size of the library and the lifetime improvement (timing margin reduction) by non-uniform extension of the library cells for various ranges of the input signal probabilities. The simulation results reveal that our technique can prolong the circuit lifetime by around 150% with a negligible area overhead.

In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated-Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D-ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with the Power Distribution Network (PDN) design due to the increasing power density and larger supply current compared to 2D-ICs. As an important part of 3D-IC PDNs, Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be well-managed. Excessive or ill-placed P/G TSVs impact the power integrity (e.g. IR-drop), and also consume a considerable amount of chip real estate. In this work, we propose a Mixed-Integer-Linear-Programming (MILP)-based technique to plan the P/G TSVs. The goal of our approach is to minimize the average IR-drop while satisfying the total area constraint of TSVs by optimizing the P/G TSV placement. Therefore, the locations, sizes and the total number of the P/G TSVs are co-optimized simultaneously. The experimental results show that the average IR-drop can be reduced by 11.8 % in average using the proposed method compared to a random placement technique with a much smaller runtime.

Radiation-induced soft error is a significant reliability issue in nanoscale technology nodes. In this paper, a novel approach based on probabilistic model checking is proposed to quantify the soft error vulnerabilities of the registers in the control paths at the Register-Transfer Level (RTL). Efficient abstraction and model simplification techniques are proposed to significantly improve the scalability of our method. The experimental results show the effectiveness of proposed techniques to successfully quantify the register vulnerabilities in the RTL design, to be used for cost-effective selective register protection.

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional Look-Up Table (LUT). Both GRHL cells and LUTs can be power gated and turned off by controlling configuration bits. In the proposed MC, only one cell is active and the others are turned off. Experimental results on MCNC benchmark suite reveal that the proposed architecture reduces the critical path delay, power, and Power Delay Product (PDP) of LBs up to 5.3%, 30.4%, and 28.8% as compared to the equivalent LUT-based architecture.

Modern Field Programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. This makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. Thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. The experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has potential to become a universal memory technology because of its various advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. However, read disturb is a major reliability issue in which a read operation can lead to a bitflip, because read and write current share the same path. This major reliability challenge is growing with technology scaling as read to write current ratio decreases. In this paper, we propose a circuit-level technique to detect read disturb by sensing the current during the read operation. Experimental results show that the proposed technique can effectively detect read disturb at the cost of negligible power and area overhead.

Field Programmable Gate Arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them. External devices like thermal chambers are usually used to heat up the chip to a desired temperature in order to apply the test. However, there are many limitations for these external devices, which make the thermal-aware testing of the FPGA a challenging process. In this paper, a self-heating approach for thermal-aware testing of FPGAs is presented, in which the internal resources of FPGA are used to build controlled self-heating elements (SHEs). These controlled SHEs are distributed across the FPGA and integrated with the built-in self-test (BIST) scheme to generate the required temperature profile for testing. Thus, no external devices for heating up the FPGA are needed. The experimental results show that a wide range of maximum chip temperatures can be achieved (from 50°C up to 125°C on Virtex-5 FPGA) with a high accuracy (±1°C).

Voltage droop is a major reliability concern in nano-scale VLSI designs. Undesirable voltage droop occurs when logic gates in the circuit draw high switching current from the on-chip power supply network, and this problem is exacerbated at high clock frequencies and smaller technology nodes. A consequence of voltage droop is an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, a.k.a. guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling (DVF) is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For DVF to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop at runtime. Several benchmarks from ITC99 and IWLS'05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits.

Carbon Nanotube Field Effect Transistor (CNTFET)--based technologies become more and more a concurrent alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFET) technologies. In contrast to a MOSFET technology, the active layer of a CNTFET technology is not a regular silicon film with homogeneous doping and rectangular dimensions, but an array of mostly aligned carbon nanotubes (CNTs). The quality of this active layer, which depends on various technology process parameters, is expressed by parameters such as CNT alignment and array density. These parameters affect the electrical properties of the logic cells placed on top of the active layer and hence the overall CNTFET circuit yield. Although not all parameters in CNT fabrication process can be fully controlled, designers still need to assure a very high yield of their cell layouts, that is, a high reproducibility of the electrical characteristics to achieve a reasonable manufacturing yield for the entire chip. In this work we close the gap between CNTFET process fabrication and circuit design by presenting a novel accurate model for active layers in CNTFET--based technologies. Our model enables the designers to obtain technology--dependent driver strength of the custom cell layouts under realistic conditions. The new model can also be used to extract and evaluate CNTFET Design for Manufacturing (DfM) and Design for Robustness (DfR) design rules, and provide feedback to adjust process technology parameters to achieve desirable functional yield.

No abstract available.

As complementary metal-oxide-semiconductor technologies enter nanometer scales, microprocessors become more vulnerable to transistor aging, mainly due to bias temperature instability and hot carrier injection. These phenomena lead to increasing device delays during the operational lifetime, which result in growing delays of the instruction pipeline stages. However, the aging rates of different stages are different. Hence, a previously delay-balanced pipeline becomes increasingly imbalanced resulting in a non-optimized design in terms of lifetime [i.e., mean time to failure (MTTF)], frequency, area, and power consumption. In this paper, we propose an aging-aware, MTTF-balanced pipeline design, in which the pipeline stage delays are balanced at the desired lifetime rather than at design time. This can lead to significant MTTF (lifetime) improvements as well as additional performance, area, and power benefits. Our experimental results show that for two different microprocessors, MTTF can be extended by at least 2.3 times while achieving an additional 10% energy improvement with no penalty on delay and area. If the demand for performance is higher than that for a longer MTTF, it is also possible to improve the clock frequency by 2%.

No abstract available.

With continuous technology downscaling, the rate of radiation induced soft errors is rapidly increasing. Fast and accurate soft error vulnerability analysis in early design stages plays an important role in cost-effective reliability improvement. However, existing solutions are suitable for either regular (a.k.a address-based such as memory hierarchy) or irregular (random logic such as functional units and control logic) structures, failing to provide an accurate system-level analysis. In this paper, we propose a hybrid approach integrating architecture-level and logic-level techniques to accurately estimate the vulnerability of all regular and irregular structures within a microprocessor. All error propagation and masking scenarios are carefully handled among these structures. We have evaluated the vulnerability of the OR1200 processor using the proposed approach. Comparison with statistical fault injection shows an average inaccuracy of less than 7% with five orders of magnitude improvement in runtime.

In nano-scale regime, there are various sources of uncertainty and unpredictability of VLSI designs such as transistor aging mainly due to Bias Temperature Instability (BTI) as well as Process-Voltage-Temperature (PVT) variations. BTI exponentially varies by temperature and the actual supply voltage seen by the transistors within the chip which are functions of leakage power. Leakage power is strongly impacted by PVT and BTI which in turn results in thermal-voltage variations. Hence, neglecting one or some of these aspects can lead to a considerable inaccuracy in the estimated BTI-induced delay degradation. However, a holistic approach to tackle all these issues and their interdependence is missing. In this paper, we develop an analytical model to predict the probability density function and covariance of temperatures and voltage droops of a die in the presence of the BTI and process variation. Based on this model, we propose a statistical method that characterizes the life-time of the circuit affected by BTI in the presence of process-induced temperature-voltage variations. We observe that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions results in 16% over-design, translating to unnecessary yield and performance loss.

With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout-based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is proposed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER.

Reliability concerns due to technology scaling have been a major focus of researchers and designers for several technology nodes. Therefore, many new techniques for enhancing and optimizing reliability have emerged particularly within the last five to ten years. This perspective paper introduces the most prominent reliability concerns from today's points of view and roughly recapitulates the progress in the community so far. The focus of this paper is on perspective trends from the industrial as well as academic points of view that suggest a way for coping with reliability challenges in upcoming technology nodes.

In the nanometer era, runtime variations due to workload dependent voltage and temperature variations as well as transistor aging introduce remarkable uncertainty and unpredictability to nanoscale VLSI designs. Consideration of short-term and long-term workload-dependent runtime variations at design time and the interdependence of various parameters remain as major challenges. Here, we propose a static timing analysis framework to accurately capture the combined effects of various workload-dependent runtime variations happening at different time scales, making the link between system-level runtime effects and circuit-level design. The proposed framework is fully integrated with existing commercial EDA toolset, making it scalable for very large designs. We observe that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions is optimistic and results in considerable underestimation of timing margin.

We propose a novel custom instruction (CI) selection technique for process variation and transistor aging aware instruction-set architecture synthesis. For aggressive clocking, we select CIs based on statistical static timing analysis (SSTA), which achieves efficient speedup during target lifetime while mitigating degradation of timing yield (i.e., probability of satisfying the timing). Furthermore, we consider process variation and aging on not only CIs but also basic instructions (BIs). Even if basic functional units (BFUs), e.g., ALU, get slower due to aging, only a few BIs with critical propagation delay may violate the timing, whereas the other BIs running on the same BFU can still satisfy the timing. We then introduce “customized BFUs”, which execute only such aging-critical BIs. The customized BFUs, used as spare BFUs of the aging-critical BIs, can extend lifetime of the system. Combining the two approaches enables speedup as well as lifetime extension with no or negligibly small area/power overhead. Experiments demonstrate that our work outperforms conventional worst-case work (by an average speedup of about 49%) and existing SSTA-based work (16x or more lifetime extension with comparable speedup).

As CMOS technologies enter nanometer scales, microprocessors become more vulnerable to transistor aging mainly due to Bias Temperature Instability and Hot Carrier Injection. These phenomena lead to increasing device delays during the operational lifetime, which results in increasing pipeline stage delays. However, the aging rates of different stages are different. Hence, a previously delay-balanced pipeline becomes increasingly imbalanced resulting in a non-optimized design in terms of Mean Time to Failure (MTTF), frequency, area and power consumption. In this paper, we propose an MTTF-balanced pipeline design, in which the pipeline stage delays are balanced after the desired lifetime rather than at design time. This can lead to significant MTTF (lifetime) improvements as well as additional performance, area, and power benefits. Our experimental results show that MTTF of the FabScalar microprocessor can be improved by 2x (or frequency by 3 %) while achieving an additional 4% power, and 1% area optimization.

Summary form only given. Improvements in chip manufacturing technology have propelled an astonishing growth of computing systems which are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. At the device level, as the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and availability of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process (e.g., process variability, sub-wavelength lithographic inaccuracies), while other factors appear because of high frequencies and nanoscale features (e.g. RLC noise, on-chip temperature variation, increased sensitivity to radiation and transistor aging). At the other end of the spectrum, these systems are seeing a tremendous increase in software content. Whereas traditional software design paradigms have assumed that the underlying hardware is fully predictable and error-free, there is now a critical need to build a software stack that is responsive to variations, and resilient against emerging vulnerabilities in the underlying hardware. To cost-efficiently tackle resiliency challenges, a new “cross-layer” trend has emerged in which different levels of design stacks, in hardware and software, work together to find a globally optimal solution. The interdisciplinary topic of cross layer resiliency cross various disciplines and requires collaboration and cooperation of various communities such as design automation, testing and design for testability, computer architecture, embedded systems and software, validation and verification, fabrication, device, circuits, and systems. Such cross-layer approach will lead to possible paradigm shifts to consider reliability throughout the design flow, from devices to systems and applications.

Power Supply Noise (PSN) has emerged as an important resilience issue in nano-scale CMOS technology. Due to simultaneous switching of various gates, the actual supply voltage seen by individual gates inside the circuit might be lower than the nominal supply voltage, leading to extra delays. Since in at-speed scan testing simultaneous switchings are higher than the functional mode, test invalidation due to excessive PSN can happen, which may impact yield loss. In this paper, we propose a Linear Programming-based X-filling approach to minimize PSN in at-speed scan test by assigning appropriate values to X-bits in partially specified test patterns. In this paper, spatial and transition time correlations due to circuit layout, power mesh, and netlist are taken into account to increase the accuracy of dynamic PSN estimation and for the first time the delay of the circuit is directly targeted to minimize the effect of PSN during the at-speed scan test.

Accurate thermal profile estimation for FPGA, at design time, is necessary to avoid unexpected thermal hot-spots in the circuit before deploying the FPGA to the in-field operation. Both accurate dynamic and leakage power values are needed for the thermal profile estimation and they can be estimated using the FPGA vendor's tools. However these report leakage power as a single value for the whole chip, and no details are given in literature or the FPGA toolset about its distribution across the FPGA chip for the thermal simulation. To cope with this problem, we present a method for properly distributing the leakage power across the FPGA chip. The method uses a temperature-leakage loop estimation model for distributing and adapting the leakage power for more accurate thermal simulation. Furthermore, to accurately calibrate the presented method and its model and also to validate the resulting thermal profiles, we utilize an infrared thermal camera, which measures the emissions from the backside of a Virtex-5 FPGA chip. The results of testing several designs, with different sizes and frequencies, show that our approach can achieve accurate thermal-profile estimation when compared to the camera measurements, with average absolute estimation error of around 1°C across the chip.

The continuous shrinking of CMOS transistors in the nano-scale era poses many manufacturing and reliability challenges such as process variation, sub-threshold leakage, power dissipation, increased circuit noise sensitivity, and reliability concerns due to transient (e.g. radiation-induced soft errors) and permanent (e.g. transistor aging) failures [1, 2]. State-of-the-art FPGAs, pushed by the ever-increasing demands on higher performance and lower power, use the latest advancements in CMOS technology [3, 4], and thus they share most of these challenges. Therefore, to guarantee the required lifetime of FPGA-mapped systems in the field, proper techniques at various levels should be devised. Transistor aging, as an important factor, causes an increase in the magnitude of threshold voltage, which in turn slows down the switching speed of the transistor and leads to timing failures and faster wear-out rates [5]. To properly deal with this issue in FPGAs, it requires modeling, monitoring and mitigation at device and architecture levels as well as the tool-chain at user level.

Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. Field Programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration of Look-Up Tables (LUTs) and the input signal probabilities against BTI-induced aging of LUTs. In this paper, we propose two methods to mitigate BTI-induced aging in LUTs. The mitigation is performed by manipulating the configuration of the used LUTs and their input signal probabilities, while maintaining the functionality of the mapped design. We implemented the proposed methods using the academic tool Verilog to Routing (VTR). The experimental results show that our methods can mitigate BTI-induced aging of LUT substantially and improve the lifetime of the FPGA-mapped designs, on average, by more than 200%.

As CMOS technology scales down into the nanometer regime, designers have to add pessimistic timing margins to the circuit as guardbands to avoid timing violations due to various reliability effects, in particular accelerated transistor aging. Since aging is workload-dependent, the aging rates of different paths are non-uniform, and hence, design time delay-balanced circuits become significantly unbalanced after some operational time. In this paper, an aging-aware logic synthesis approach is proposed to increase circuit lifetime with respect to a specific guardband. Our main objective is to optimize the design timing with respect to post-aging delay in a way that all paths reach the assigned guardband at the same time. In this regard, in an iterative process, after computing the post-aging delays, the lifetime is improved by putting tighter timing constraints on paths with higher aging rate and looser constraints on paths which have less post-aging delay than the desired guarband. The experimental results shows that the proposed approach improves circuit lifetime in average by more than 3X with negligible impact on area. Our approach is implemented on top of a commercial synthesis toolchain, and hence scales very well.

The Advanced Encryption Standard (AES) is one of the most widespread encryption techniques used by millions of users worldwide. Although AES was designed to withstand linear or differential attacks, the security of encrypted messages is not guaranteed. Bit flips occurring during the encryption due to runtime failures or purposely invoked by an attacker are a major security concern and can significantly jeopardize integrity, privacy, and confidentiality and hence the security of the system. Therefore, techniques to increase the reliability (fault-tolerance) and with it the security of cryptographic systems are necessary. This work proposes a self-adaptive software-implemented fault-tolerance methodology for AES (A-SOFT-AES) to enhance its fault-tolerance. This technique is based on a pool of software-implemented fault-tolerance techniques out of which it dynamically chooses the best one in terms of performance, cost, and fault-tolerance for a wide range of fault rates. Therefore, it provides superior flexibility over classic hardware-based implementations.

Transistor aging degrades path delay over time and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these designs and the large number of critical paths in today's IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging-aware representative path-selection method that allows us to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to transistor aging. Moreover, since aging is affected by process variations and runtime variations in temperature and voltage, we use machine learning and linear algebra to incorporate these variations during representative path selection. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical path delay based on the selected representative paths.

With continuous downscaling of VLSI technologies, logic cells are becoming more susceptible to radiation-induced soft error. To accurately model this at chip-level, the impact of electrical masking should be accurately considered. Moreover, increasing complexity of VLSI chips at nanoscale results in voltage fluctuation across the chip which impacts the electrical masking. In this paper, we present a chip-level electrical masking analysis which accurately considers the impact of voltage fluctuation across the chip. Our analysis shows that neglecting voltage fluctuation in electrical masking can lead up to 152% inaccuracy in the overall soft error rate. We also present a technique based on backward pulse propagation to reduce the runtime of this analysis.

Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Hence, asynchronous logic, which is intrinsically more robust to variability, seems an ideal and perhaps unavoidable choice for digital circuits in CNFET technology. This article presents the results on the design and analysis of a CNFET-based implementation of an asynchronous circuit primitive: the Muller C-element. Using a CNFET SPICE model, we evaluate the robustness of CNFET-based C-element in the presence of CNT fabrication-related nonidealities. We investigate a quantitative evaluation of how timing variability impacts the functionality of a C-element and then, extract the necessary delay constraints of the C-element circuit from the signal transition graph specification. Considering the large degrees of spatial correlation observed between the CNFETs fabricated on directionally grown CNTs, a layout technique is exploited to overcome the robustness challenges of a CNFET-based C-element. Extensive Monte Carlo simulations on the proposed technique have demonstrated the effectiveness of the proposed CNFET-based C-element by improving approximately 50X in its robustness in expense of 65% area, 47% delay, and 56% power consumption overheads. Experimental results indicate that implementation of some CNFET-based Quasi Delay Insensitive (QDI) benchmark circuits using the proposed C-element results in significant robustness improvement with negligible power and throughput overheads. As a promising step toward CNFET-based giga-scale integrated circuits, this article shows that the asynchronous logic is an effective approach to design robust integrated circuits in CNFET technology with inherent extreme physical variations.

Several emerging nano-technologies, including crossbar nano-architectures, have recently been studied as possible replacement or supplement to CMOS technology in the future. However, extreme process variation and high failure rates, mainly due to atomic device sizes, are major challenges for crossbar nano-architectures. This article presents variation- and defect-tolerant logic mapping on crossbar nano-architectures. Since variation/defect-aware mapping is an NP-hard problem, we introduce a set of Integer Linear Programming (ILP) formulations to effectively solve the problem in a reasonable time. The proposed ILP formulations can be used for both diode-based and FET-based crossbars. Experimental results on benchmark circuits show that our approach can reduce the critical-path delay 39% compared to the Simulated Annealing (SA) method. It can also successfully achieve 97% defect-free mapping with 40% defect density. It can tolerate process variations to meet timing constraints in 95% of the cases, compared to only 77% achieved by SA.

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.

Carbon Nanotube Field Effect Transistors (CNT-FETs) are being considered as a promising successor to current CMOS technology. Since the alignment of CNTs cannot be fully controlled yet, the layout of CNTFET-based standard cells has to be designed robust against misalignment. As CNTFET-based designs become more prevalent, a systematic methodology for misalignment robustness evaluation becomes crucial. In this work we present a novel EDA tool “Layout-Driven Robustness Analysis” (LDRA) which enables designers to, for the first time, measure the robustness against misalignment. LDRA is validated and applied to various CNTFET-based standard cell layouts. The comparison of these cells reveals that robustness against misalignment is complex and depends on many factors. A CNT curve model is introduced and its influence on the robustness result is discussed. In conclusion, key factors for designing layouts robust against misalignment are proposed.

Negative Bias Temperature Instability (NBTI) is a major source of transistor aging in scaled CMOS, resulting in slower devices and shorter lifetime. NBTI is strongly dependent on the input vector. Moreover, a considerable fraction of execution time of an application is spent to execute NOP (No Operation) instructions. Based on these observations, we present a novel NOP assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. Our analysis shows that NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as NOP. We also proposed two methods, software-based and hardware-based, to replace the original NOP with this maximum aging reduction NOP. Experimental results based on SPEC2000 applications running on a MIPS processor show that this method can extend the lifetime by 37% in average while the overhead is negligible.

With shrinking feature sizes, transistor aging due to NBTI and HCI becomes a major reliability challenge for microprocessors. These processes lead to increased gate delays, more failures during runtime and eventually reduced operational lifetime. Currently, to ensure correct functionality for a certain operational lifetime, additional timing margins are added to the design. However, this approach implies a significant performance loss and may fail to meet reliability requirements. Therefore, aging-aware microarchitecture design is inevitable. In this paper we present ExtraTime, a novel microarchitectural aging analysis framework, which can be used in early design phases when detailed transistor-level information is not yet available to model, analyze, and predict performance, power and aging. Furthermore, we show a comprehensive investigation using ExtraTime of various clock and power gating strategies as well as aging-aware instruction scheduling policies as a case study to show the impact of the architecture on aging.

With shrinking feature sizes, transistor aging becomes a reliability challenge for embedded processors. Processes such as NBTI and HCI lead to increasing gate delays and eventually reduced lifetime. Currently, to ensure functionality for a certain lifetime, safety margins are added to the design, which means overdesign and increased costs. To extend lifetime, reduce power and heat, while maintaining the required performance we propose a dynamic runtime adaptation approach, which is based on runtime monitoring of temperature, performance, power and wearout in combination with fine-grained proactive dynamic voltage and frequency scaling. The experimental results presented in this work show lifetime improvements between 63% up to 5×, while the required performance as well as power and temperature constraints are maintained.

Summary form only given. In this paper, we propose schemes for protecting the front-end logic of present-day superscalar processors. This logic is comprised of several structures like Rename Table, Issue Queue (IQ) and Re-order buffers (ROB) which contain critical information about instructions moving through the pipeline. As the instructions reside in these structures for multiple cycles, the Architecture Vulnerability Factor (AVF) of these structures is significantly high. The proposed schemes look at the lifetime of instructions in various pipeline structures, utilize the inherent redundancy present in the front-end logic of the pipeline and increase it to a minimal level, in order to detect and recover from transient errors.

As the state-of-the-art FPGA devices use the latest advancements in CMOS technology, they also face the reliability challenges of nano-scale CMOS. Transistor aging, mainly due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), is a major reliability issue. In this paper, we present a tool to predict the amount of aging-induced degradation for designs mapped to FPGA devices, to help the designers, in an early phase of the design flow, to choose the appropriate mapping and/or optimization efforts, in order to prolong the lifetime of their FPGA-mapped designs. The tool is based on system level abstractions for both BTI and HCI device level models, in addition to implicit device-level information existed in the power and timing reports provided from the FPGA's vendor tools. A case study of using the tool to explore different designs and mapping options shows that aging of the FPGA device is dependent on the design loaded onto it. Furthermore, different mappings and optimizations of the same circuit can result in different aging rates.

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. As much as FPGAs benefit from the most scaled and advanced technologies, they become more susceptible to transistor aging. In this paper, we investigate the effect of transistor aging on programmable routing resources of FPGAs, by considering different implementations through detailed SPICE simulations. The effects of different parameters, such as wire length, cascaded routing, routing fan-out, signal probability and supply voltage on the aging of routing resources are studied.

As CMOS feature size scales to the nanometer regime, transistor aging mostly due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), has emerged as a major reliability concern. Threshold voltage shift causes the circuit to fail, once the post-aging delay exceeds the timing constraint. In this paper, we investigate the stacking effect of transistors on aging and propose a novel input/transistor reordering approach to alleviate the effect of NBTI and HCI during the active mode operation of the circuit. According to the results, the circuit failing due to aging effect is postponed by increasing the operational lifetime for ISCAS benchmarks by 23.6%, in average, while it has a negligible effect on delay, area, and power compared to the original cell input ordering.

Programmable nano-architectures fabricated using bottom up self assembly are promising alternatives to CMOS circuits. However, extreme process variation and high defect rate are major challenges in this nanotechnology. In this paper, we present variation and defect aware logic mapping algorithms for these nano-architectures. Simulation results show that the proposed logic transformations and the mapping algorithms based on them can improve manufacturing yield by 65% with only 12.5% area overhead.

Soft error is becoming one of the major reliability concerns with continuously shrinking transistor size. Low level transient events may result in multiple correlated bit flips at high level. Considering this correlation effect is essential for accurate error rate estimation and efficient error mitigation. This paper proposes a novel framework to address this correlation issue at logic level. Based on the concept of error propagation function, graph transformation techniques are utilized to convert the error probability and correlation problem into the computation of signal probability and correlation. The experimental results show that compared with Monte-Carlo simulation, our approach is 72× faster, while the average inaccuracy of error probability estimation is below 0.006.

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application. In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

Reversibility as an inherent requirement of quantum computation motivates further research on reversible logic. Due to anticipated high failure rates for such technologies, thorough testing is a must for these circuits. In this paper, we present a compact test generation and application method for reversible circuits which achieves high (100%) fault coverage and can be adopted for BIST implementations. In this method, the next test pattern is the response of the reversible circuit to the previous test pattern. A test generation algorithm to minimize test time and achieve 100% fault coverage is also presented. Simulation results on a set of reversible benchmark circuits confirm that this approach can detect all single missing/repeated gate faults as well as the majority of multiple faults.

Programmable nano-architectures fabricated based on bottom-up self-assembly process are alternative for CMOS technology to overcome physical barriers as well as increased lithography-based fabrication costs in downscaling. Extreme process variation and high failure rate due to nondeter-ministic self assembly fabrication process pose serious challenges for logic implementation in this technology. In this paper, we analyze the effect of variations on mapped designs and propose an efficient mapping method to reduce variation effects on crossbar nano-architectures. This method takes advantage of reconfigurability and abundance of resources for tolerating variation and improving reliability. The main idea is based on duplicating crossbar input lines as well as swapping rows (columns) of a crossbar to reduce the output dependency and be able to reduce delay variation. Experimental results on a set of benchmarks show that the proposed method can reduce critical path delay up to 74% (57% in average).

In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and speed-up (10,000X faster) of MEPP.

Reversible logic is a promising design methodology, particularly in the scope of quantum computing, for extremely low power consumption by elimination of power dissipation due to information loss. Anticipated high fault rates for future technologies raise demand for fault tolerance in reversible logic. In this paper we propose fault masking techniques (to prevent error propagation) for reversible logic. We present different implementations of reversible majority voters. Using voter insertion techniques and taking advantage of available non-functional outputs, we are able to provide diagnosis information with adjustable resolution for reversible circuits. Such diagnosability has important applications in manufacturing testing as well as online repair. In contrast to previous work this voter is robust against single point of failure. We target missing and repeated gate fault models which are specific to reversible logic.

Transistor aging due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is a major reliability issue for aggressive device downscaling at nanoscale. State-of-the-art FPGA chips, which use most recent CMOS technologies and smallest feature sizes to meet high performance demands, are at the front line to face this problem. In this paper, we present the design and mapping of a low-cost logic level aging sensor for FPGA-based designs. The mapping of this sensor is designed to provide controlled sensitivity, ranging from a warning sensor to late transition detector. The functionality of the sensor has been verified on a Virtex5-based board. Area, delay, and power overhead of a set of sensors mapped for most aging-critical paths of representative designs are very modest. (≈ 1.3% area, ≈ 1.6% performance, and ≈ 1.5% power overhead).

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI chips. As much as FPGAs benefit from the most scaled and advanced technologies, they become susceptible to transistor aging. In this paper, we investigate the effect of transistor aging, due to NBTI and PBTI, in look-up tables (LUTs), by considering different implementations through detailed SPICE simulations. We found out that the delay degradation due to transistor aging depends on the mapped configuration, usage (input signal probability) as well as the specific LUT implementation. Moreover, the specific configuration mapped previously into an LUT has a considerable effect on the delay degradation of the currently used configuration of that LUT. We also found that the all-zero configuration which is normally used as the standby configuration is not the best choice and it may even result in high delay degradation.

Transistor aging is a serious reliability challenge for nanoscale CMOS technology which can significantly reduce the operation lifetime of VLSI chips. Negative Bias Temperature Instability (NBTI) is the major contributor to transistor aging which affect PMOS transistors. The input vectors applied to the logic core has a significant impact on the overall aging of the logic block. In this paper, we present an efficient input vector selection technique based on Linear Programming (LP) to be used for maximum relaxation during the standby phase. We consider an accurate delay model for post-aging critical paths. Our mixed-LP (binary-relaxed) formulation scales well for very large circuits and provides near-optimal solutions. Experimental results and comparison with Monte-Carlo simulations show the speedup (4-5 orders of magnitude) and further optimization (11%) of our approach. Using these input vectors for the standby phase, the aging effect can be postponed by 71% in average.

Nano crossbar architectures are based on emerging nan- otechnology fabricated using self-assembly processes to reduce manufacturing costs and achieve higher levels of integration. An extreme parameter variation due to nondeterministic nanofabrication is one of the major challenges in this nanotechnology. Asynchronous circuits seem a promising option for logic implementation on nano-crossbar architectures. However, the circuit must be designed in such a way to guarantee the required timing constraints, under extreme delay variations, to ensure correct functionality. In this paper, we propose an efficient implementation of Quasi Delay Insensitive (QDI) asynchronous circuits on nano crossbar arrays. The proposed method guarantees timing requirements in isochronic forks with respect to worst case delay variations. Extensive Monte Carlo simulations for delay variations on a set of representative designs confirm that our approach can tolerate 200% delay variations with success rate of 99.55%, compared to only 0.13% achieved by the previous work, with almost 100% area overhead.

Power supply noise in nano-scale VLSI is one of the design concerns. Due to switching current of various logic gates, the actual supply voltage seen by different devices fluctuates, causing extra delays and ultimately intermittent faults during operation. Therefore, accurate estimation of worst case scenario, maximum noise and the vectors causing it, is extremely important for design, verification, and manufacturing test steps. In this paper we present a mixed-integer linear programming modeling of power supply noise in digital circuits to obtain fast and accurate solutions. Compared with accurate SPICE simulations of random vectors for a set of benchmark circuits, the proposed approach can achieve 13115× speedup while obtains 2.7% more optimization in average.

As hardware devices like processor cores and memory sub-systems based on nano-scale technology nodes become more unreliable, the need for fault tolerant numerical computing engines, as used in many critical applications with long computation/mission times, is becoming pronounced. In this paper, we present an Algorithm-based Fault Tolerance (ABFT) scheme for an iterative linear solver engine based on the Conjugated Gradient method (CG) by taking the advantage of numerical defect correction. This method is "pay as you go", meaning that there is practically only a runtime overhead if errors occur and a correction is performed. Our experimental comparison with software-based Triple Modular Redundancy (TMR) clearly shows the runtime benefit of the proposed approach, good fault tolerance and no occurrence of silent data corruption.

High resolution diagnosis plays a critical role in silicon debug and yield improvement. Application-dependent diagnosis is also a key component in online testing and adaptive computing. In this paper, a new technique for high resolution localization of faults in the interconnects and logic blocks of an arbitrary design implemented on a field-programmable gate array (FPGA) is presented. This work is complementary to application-independent detection methods for FPGAs. This technique can uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The number of test configurations for interconnect diagnosis is logarithmic to the size of the mapped design, whereas logic diagnosis is performed in only one test configuration with less than 5% overhead of built-in self diagnosis. These techniques have been further extended for multiple fault diagnosis.

Bottom-up self-assembly nanofabrication process yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled nanodevices. Therefore, it is one of the major design challenges to tolerate variation, in addition to defect tolerance, in emerging nano architectures. In this paper, we present a solution for variation tolerant logic mapping for FET based crossbar array nano architectures using Simulated Annealing. Furthermore, we extended the framework for defect tolerance. Experimental results including comparison with exact method confirm the effectiveness of the proposed approach.

In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault injection approach with 92% accuracy. This makes the proposed approach applicable to industrial-scale circuits.

Bottom up self-assembly of nano-crossbars from carbon nano-tubes and semiconductor nano-wires has shown the potential to overcome the limitations of lithographic fabrication of CMOS for further down-scaling. However, very high permanent and transient fault rates necessitates the incorporation of efficient fault tolerance techniques, capable of handling multiple faults. Self repair provides fault tolerance through fault detection, diagnosis and reconfiguration to recover from permanent faults. In this paper, we present a multiple faults diagnosis scheme based on dual rail error checking frameworks for nano-crossbar architectures. The proposed scheme is capable of identifying multiple faulty crosspoints with very low performance and area overheads. The experimental results show that all of the multiple faults are correctly diagnosed.

High runtime failure rate as a result of reliability detractors is one of the major challenges for scaled-CMOS as well as emerging nanotechnologies. This results in multiple faults during life time operation. In this paper we propose a self-timed asynchronous architecture which can tolerate multiple transient bit-flips. This architecture has self-timed property, making it robust against delay variations caused by increased process variations at nanoscale. The proposed architecture can achieve 100% tolerance of single transient faults as well as more than 93% tolerance of multiple faults for failure rate less than 10-2.

Research in reversible logic is motivated by its application in quantum computing as well as its promise in extremely low power consumption by elimination of power dissipation due to information loss. In this paper we propose a set of novel dual rail reversible logic gates for online testable reversible logic design. Experimental results show that our technique detects 100% of single faults while reducing the area and the number of garbage outputs up to 6.4X and 4.6X, compared to previously proposed techniques, respectively.

Radiation effects on SRAM-based FPGA configuration memory induce unique failure modes that cannot be found in similar ASIC devices and can translate into permanent errors in the circuit mapped into the FPGA. The physical layout of the mapped circuit has a considerable impact on the overall reliability of the implemented circuit. In this work we present a set of soft error reliability aware placement and routing algorithms, by modifying the original VPR toolset, to improve the reliability of the mapped designs against SEUs occurring in the FPGA SRAM configuration memory. Our proposed approach tries to minimize the number of possible errors in the circuit while optimizing for traditional design constraints, namely, area and delay. Using our approach we were able to reduce the number of total sensitive bits by 58% on average.

In hybrid nano-architectures, self-assembled nanoscale crossbars are fabricated on top of a reliable CMOS subsystem. Bottom-up self-assembly nanofabrication process, used in nano-architectures, yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled nanodevices. Therefore, it is one of the major design challenges to tolerate variation and defects in emerging nano architectures. In this paper, we present an alternative approach for variation and defect tolerant mapping in which no application-independent test and characterization (defect and variation map) is required. The variation tolerant mapping is done on-the-fly which can ultimately be transformed into built-in self-mapping. Different mapping algorithms are presented and their efficiencies in terms of variation and defect tolerance as well as mapping time are compared. The experimental results show that the proposed heuristic mapping algorithm can achieve the same success rate with the exhaustive method in terms of meeting required timing constraints with orders of magnitude fewer reconfiguration retries.

Soft errors, due to cosmic radiations, are the major reliability barriers for VLSI designs. To meet reliability constraints in a costeffective way, it is critical to assess soft error reliability parameters in early design stages. In this paper, we present a framework to accurately obtain soft error rate (SER) for high-level (behavioral) descriptions (Verilog or VHDL). We transform the SER problem into an equivalent Boolean satisfiability (SAT) problem and use state-of-the-art SAT-solvers to obtain SER. We have developed an automated flow to convert high-level hardware descriptions into SAT formulations for exact SER computation. We compare our technique to traditional fault simulation techniques. The experimental results show that fault simulations with orders of magnitude run time overhead still result in significantly inaccurate underestimation of SER values. We applied the technique on the largest ISCAS benchmark circuits and found out that it scales well.

In hybrid nano architectures, self-assembled nanoscale crossbars are fabricated on top a reliable CMOS subsystem. Bottom-up selfassembly process used in the fabrication of nanoscale devices yields significantly more defects compared to the conventional top-down lithography used in CMOS fabrication. Therefore, applying defect tolerant design schemes is inevitable in order to map the design to these programmable fabrics by bypassing defects. In this paper, we present an alternative approach for defect tolerant mapping in which the mapping phase is built into the programmable fabric and reliable on-chip resources are used for on-the-fly defectfree mapping. This built-in self map (BISM) scheme significantly reduces the complexity of defect tolerance during design time as well as post-fabrication configuration time. Various BISMschemes are presented and their efficiencies in terms of defect tolerance and mapping time are compared.

Crossbar nano-architectures based on self-assembled nano-structures are promising alternatives for current CMOS technology, which is facing serious challenges for further down-scaling. One of the major challenges in this nanotechnology is elevated failure rate due to atomic device sizes and inherent lack of control in self-assembly fabrication. Therefore, high permanent and transient failure rates lead to multiple faults during lifetime operation of crossbar nano architectures. In this paper, we present a concurrent multiple error detection scheme for multistage crossbar nano-architectures based on dual-rail implementations of logic functions. We prove the detectability of all single faults as well as most classes of multiple faults in this scheme. Based on statistical multiple fault injection, we compare the proposed technique with other online error detection and masking techniques such as Triple Module Redundancy (TMR), duplication, and parity checking, in terms of fault coverage as well as area and delay overhead.

It is anticipated that the number of defects in nanoscale devices fabricated using bottom-up self-assembly process is significantly higher than that for CMOS devices fabricated by conventional top-down lithography patterning. This is mainly because of inherent lack of control in self-assembly fabrication as well as atomic scale of devices. The goal of defect tolerance, as an integral part of nano computing, is to obtain error-free computation from such fabrics containing defective elements. In this article, an application-independent defect tolerant scheme for reconfigurable crossbar array nanoarchitectures is presented. The main feature of this approach is that the existence and location of defective resources within the nano-fabric are hidden from the entire design flow, resulting in minimum post-fabrication customization per chip and minimum changes to the entire design and synthesis flow. It is also shown how to drastically minimize the area overhead associated with this flow. The proposed technique requires extraction of regular yet incomplete defect-free subsets, in contrast to previously proposed complete defect-free subsets. This can greatly reduce the area overhead required for defect tolerance while not sacrificing logic mapping or signal routing capabilities. Extensive simulation results confirm considerable reduction in the area overhead without any negative impact on the usability of modified defect-free subsets.

Soft errors due to alpha and cosmic particles are a growing reliability threat to information systems. In this work, a methodology is developed to analyze the effects of single event upsets (SEU) and obtain FIT rates for commercial microprocessors in live information systems. Our methodology is based on data collected from error logs and error traces of the information systems present globally in the field. We also compare the system effects of errors that are suspected to be due to SEUs as compared with non-SEU errors. Soft errors are further localized within specific microprocessor resources with the assistance of the machine check architecture. The analyzed field data represents a world-wide population of microprocessors installed in the field. In total, several thousands systems and thirty-six months of field data were analyzed. The methodology used in carrying out this field analysis is discussed in detail and results are presented.

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Since the reliability requirements of these high performance storage subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in the overall system reliability. We validate the projections produced by our analytical model by using field error rates obtained from actual field failure data of a large FPGA-based design used in the logical unit module board of a commercial storage system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied)

Testing of field-programmable gate array (FPGA) resources used for mapping a particular design (application-dependent testing) is a key factor in FPGA defect tolerance for yield enhancement and cost reduction as well as online testing in adaptive reliable computing. The majority of the FPGA real estate is dedicated to the interconnect network, and defects in the interconnects manifest themselves as delay faults. In this paper, a very thorough application-dependent interconnect delay testing technique is presented. Achieving a high coverage on path delay fault has been traditionally intractable for application-specific integrated circuits. However, by leveraging the reconfigurability of FPGAs, the presented technique is able to achieve 100% robust path delay coverage on all the paths in the design. This automatically results in 100% transition fault coverage. The required number of test configurations is two or four, depending on the structure of the design. Algorithms with linear time complexity are presented for automatic test configuration and test vector generation

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.

Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the probability of particle strikes in these elements is high and can significantly impact overall processor reliability. Previous work [ 2] has developed effective metrics to accurately measure the vulnerability of cache memory elements. Based on these metrics, we have devel oped a reliability-performance evaluation framework, which has been built upon the Simplescalar simulator. In this work, we focus on the reliability aspects of L1 and L2 caches. Specifically, we present algorithms for tag vulnerability computation and investigate and report in detail on the vulnerability of data, tag, and status bits in the L2 array. Experiments on SPECint2K and SPECfp2K benchmarks show that one class of error, replacement error, makes up almost 85% of the total tag vulnerability of a 1MB write-back L2 cache. In addition, the vulnera bility of L2 tag-addresses significantly increases as the size of the memory address space increases. Results show that the L2 tag array can be as susceptible as first-level instruction and data caches (IL1/DL1) to soft errors.

Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), the probability of system failure due to soft errors, is a key factor in design of cost-effective soft error resilient systems. We present a very fast and accurate approach based on enhanced static timing analysis and signal probabilities to estimate the probability of latching an incorrect value in the system bistables (timing derating). Experimental results and comparison with fault injections using timing accurate Monte-Carlo simulations show that the accuracy of our approach is within 1 % while orders of magnitude faster.