The chase for high yield designs can effectively reduce chip manufacturing costs, making yield optimization a crucial problem in the IC community. However, the timeconsuming Monte Carlo simulations required by yield analysis hinder the traditional yield optimization methods from applying to the efficient analog circuit design flow, especially in high-dimensional design spaces. In this paper, we propose a high-dimensional yield optimization method via Monte Carlo tree search and self-regressive auto-encoder promoted subspace decomposed Gaussian process. To mitigate the common issue of over-exploration in high-dimensional optimization, a Monte Carlo tree is adopted to quickly identify promising local regions within the design space. The optimization in the selected region is realized by Bayesian optimization. To further accelerate the convergence speed of local optimization, a self-regressive autoencoder is proposed to adaptively learn for each performance metric an embedded linear subspace with dimensionality much smaller than the original design space. A specific subspace decomposed Gaussian process is constructed to model the yield variation based on the low-dimensional features of observed design parameters. A message passing algorithm is used to efficiently maximize the acquisition function, which obtains the next candidate design in intersected subspaces. Compared with the state-of-the-art methods, the proposed method achieves 2:20× – 3:99× speedup in simulation cost and 5:22×–14:33× speedup in time cost when tested in three real circuit designs.

This paper introduces Atelier, a large language model (LLM)-based framework for analog circuit design to address the issues of data scarcity and the substantial domain-specific knowledge required in this field. Atelier integrates general-purpose LLMs with a high-quality, compact knowledge base to fulfill the considerable knowledge requirements of analog circuit design, obviating the need for extensive domain-specific training or fine-tuning. The knowledge base is meticulously curated to be task-oriented and encapsulates critical information from pertinent literature within user-defined templates, leveraging the LLMs’ capabilities in text comprehension and summarization. The framework comprises several LLM agents, structured in a graph-of-thoughts architecture, with each agent specialized in a distinct task in analog circuit design, including circuit analysis, topology selection, topology modification, parameter tuning, and design decision. This collaborative multi-agent system, enriched with access to the compact knowledge base and advanced mechanisms such as self-reflection, backtracking, and tool integration, automates the analog circuit design process. It significantly enhances design quality and efficiency while ensuring interpretability. Experimental results highlight Atelier’s superiority over state-of-the-art black-box methods, general-purpose LLMs, and LLM-based methods, demonstrating notable improvements in success rates, design quality, and runtime.

Digital computing-in-memory (DCIM) systems integrate complex digital logic with parasitic-sensitive bitcell arrays, presenting unique physical design challenges. Conventional design strategies often fall short in these systems due to irregular dataflow patterns and excessive interconnect lengths, which degrade performance and increase parasitic effects. As a result, current DCIM implementations frequently rely on manual layout, which is both time-consuming and a major bottleneck in the design cycle. While existing DCIM layout synthesis frameworks attempt to automate this process using template-based placement methods inspired by manual design, their rigid constraints can lead to inefficient area utilization and increased core sizes. To address these limitations, we propose DAMIL-DCIM+, a novel placement framework that combines the structural clarity of template-based methods with the flexibility of optimization-based techniques. Specifically, DAMIL-DCIM+ employs a global dataflow-aware floorplan to guide placement and leverages MILP-based detailed placement to optimize wirelength and preserve dataflow regularity. Inspired by self-assembling design principles, this approach enables scalable and structured integration of parasitic-sensitive components. The hybrid methodology of DAMIL-DCIM+ reduces total wirelength, lowers parasitic effects, and enhances performance while maintaining design regularity. Experimental results on a 28nm DCIM circuit demonstrate that DAMIL-DCIM+ improves operating frequency by 25.2% and reduces power consumption by 19.6% compared to Cadence Innovus, without increasing core area.

Robust analog circuit design is becoming increasingly challenging due to process, voltage, and temperature (PVT) variations at advanced technology nodes. In this article, we formulate analog circuit synthesis as a robust optimization problem, and propose a Contextual Robust OptimiZAtion (CROZA) method for variation-aware analog circuit design. The proposed method uses Contextual Gaussian process to model both the design parameters and perturbation parameters, and a hybrid strategy of adversarially robust optimization and stochastically perturbed robust optimization to find robust solutions. Compared to state-of-the-art methods, our proposed approach achieves significant simulation and runtime speedups while delivering superior optimization results.

As semiconductor technology node advances, the number of parameters in the modern device compact model increases drastically. Manual extraction of these model parameters becomes not only tedious but also impossible, and the automatic method is strongly desired. Traditional black-box optimization suffers from poor scalability due to the curse of dimensionality, while deep learning–based methods typically require large amounts of training data. To address these challenges, we propose CDRPE: a combined deep learning and self-attention enhanced reinforcement learning framework for automatically extracting a large set of DCM parameters across multiple electrical characteristics. The framework leverages a pre-trained multilayer perceptron to initialize core parameters, incorporates device physics knowledge to guide the search, and employs a self-attention–enhanced RL agent for efficient exploration in high-dimensional parameter spaces. Experimental results on BSIM4, BSIMSOI, and BSIMCMG demonstrate that CDRPE can automatically extract 100 parameters with root-mean-square error below 5% relative to TCAD and silicon data. Compared with existing methods, the proposed framework achieves a 7.7x speed up. Moreover, the generated models show good convergence in both digital and analog circuit simulations, exhibiting the potential of this framework for future practical applications.

Numeric optimization methods are widely utilized to tackle complex analog circuit sizing problems, where the challenges include expensive simulations, non-linearity, and high parameter dimensionality. However, the diverse characteristics exhibited by different circuits result in varied optimization landscapes, making it difficult to identify a single algorithm that consistently outperforms others across all problems. In this paper, we introduce a multi-algorithm interworking optimization framework, which achieves optimization superadditivity based on a pool of member algorithms and a powerful algorithm-interworking protocol. We propose a computing resource reallocation method, which employs multitask Gaussian process regression and portfolio optimization techniques, leading to flexible and prudent online adaption of member algorithms. To efficiently utilize the computing resources for local exploitation, an evaluation data broadcast strategy enables cooperativeness across member algorithms. Besides, algorithms with different modeling overheads are integrated time-adaptively via an asynchronous parallelization mechanism. Comparative experiments against state-of-the-art algorithmcombining tools and optimization algorithms demonstrate the superiority of the proposed optimization framework.

Harmonic balance (HB) method is a powerful frequency-domain method used in RF circuit simulations. The key point of HB method is efficiently solving the Jacobian system in Newton’s method. In this paper, we first introduce a new time-domain preconditioner for HB Jacobian. Unlike existing time-domain preconditioners, which cannot balance the efficiency of solving the linear system corresponding to the preconditioner with the reduction in iteration step for strongly nonlinear circuit, the proposed preconditioner successfully addresses both aspects. We also present a new preconditioning method that extends time-domain preconditioners to circuit with distributed devices, which was previously unattainable. Finally, a matrix norm-based metric is proposed to measure the strength of circuit nonlinearity, which can help us a priori choose the appropriate preconditioner.

The parameterizable and synthesizable RISC-V processors enable the automatic generation of customized CPU cores through EDA tools. However, current methods often explore the extensive design space with significant model errors while neglecting design constraints, which are critical for practical implementations. To address these limitations, we propose a Self-Review Bayesian Optimization method (SRBO). This method integrates a teacher-student paradigm within a local Bayesian optimization framework to reduce model errors and enhance exploration efficiency. Additionally, it employs deep ensembles for effective constraint handling. Experimental results demonstrate that our approach outperforms state-of-the-art methods within a limited time budget, significantly enhancing exploration efficiency.

Mapping to$k$-input lookup tables ($k$-LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact$k$-LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.

This paper presents INTO-OA, an interpretable topology optimization method for operational amplifiers (op-amps). We propose a Bayesian optimization-based approach to effectively explore the high-dimensional, discrete topology design space of op-amps. Our method integrates a Gaussian process surrogate model with the Weisfeiler-Lehman graph kernel to extract structural features from a dedicated circuit graph representation. It also employs a candidate generation strategy that combines random sampling with mutation to balance global exploration and local exploitation. Additionally, INTO-OA enhances interpretability by assessing the impact of circuit structures on performance, providing designers with valuable insights into generated topologies and enabling the interpretable refinement of existing designs. Experimental results demonstrate that INTO-OA achieves higher success rates, a 1.84× to 19.10x improvement in op-amp performance, and a 3.20x to 14.33× increase in topology optimization efficiency compared to state-of-the-art methods.

Digital computing-in-memory (DCIM) systems integrate complex digital logic with parasitic-sensitive bitcell arrays. Conventional physical design strategies degrade DCIM performance due to a lack of dataflow regularity and excessive wirelength. As a result, current DCIM design often relies on manual layout, which is time-consuming and a bottleneck in the design cycle. Existing layout synthesis frameworks for DCIM often mimic the manual approach and employ a template-based method for DCIM placement. However, overly constrained templates lead to an excessive core area, resulting in high costs in practice. In this work, we introduce DAMIL-DCIM, a novel placement framework that bridges template-based techniques with optimization-based placement methods. DAMIL-DCIM utilizes a global dataflow-aware floorplan inspired by template methods and further optimizes the layout using MILP(Mixed Integer Linear Programming)-based detailed placement. The combination of global floorplanning and placement optimization reduces total wire length while maintaining dataflow regularity, resulting in lower parasitic and enhanced performance. Experimental results show, on a practical 28nm DCIM circuit, our approach improves frequency by 25.2% and reduces power consumption by 19.6% compared to Cadence Innovus, while maintaining the same core area.

Thermal issues are critical in 2.5D/3D IC design, and liquid cooling provides an effective solution for heat dissipation. Widely used compact thermal models (CTMs) convert chips into circuit networks for fast thermal simulations. However, current matrix-solving acceleration methods for CTM-derived circuits are inadequate for high-speed iterative transient thermal analysis of large-scale liquid-cooled 2.5D/3D ICs during design optimization. In contrast, the random walk method can provide fast solutions for local nodes in large-scale circuit networks, but it is not applicable to the circuit networks of the CTMs with liquid cooling. In this paper, we propose LCTMwalk, a novel GPU-accelerated random walk method for transient thermal analysis of liquid-cooled 2.5D/3D ICs. To enable random walks on the liquid-cooled CTM-derived circuit network, we replace the voltage-controlled current source model with the diode model. Additionally, we improve the transient analysis by using a time-backward random walk with time-domain path reuse, accelerating the solution of temperature at local circuit nodes. Experimental results show LCTMwalk can solve million-scale cases in only 500 ms, and achieves a 14-22× speedup compared to the state-of-the-art alternating direction implicit (ADI) method with GPU. Besides, LCTMwalk exhibits good generalizability and can be applied to various 2.5D/3D IC structures with high accuracy (error<1 K compared to 3D-ICE).

For highly integrated, thermally constrained chiplets, the design process requires iterative shape optimization, making rapid thermal simulation across varying geometries critically important. Existing deterministic approaches, such as COMSOL and HotSpot require solving large-scale linear systems, incurring expensive computational costs. Stochastic methods suffer from slow convergence, demanding excessive resources for high-precision results. Current neural network (NN)-based methods necessitate retraining upon geometry modifications, limiting adaptability. Meanwhile, neural networks suffer from the absence of provable error bounds, introducing three fundamental risks in practical deployment. We enable the fast solution of heat equations for varying geometries and propose a novel solver that integrates operator learning with stochastic methods. By employing diffeomorphic mapping, our approach addresses the challenge of operator networks in handling shape variations. Furthermore, the network’s predictions guide the stochastic method for variance reduction, which extremely accelerates the traditional stochastic method, while the stochastic results provide error guarantees and corrections for the neural network’s outputs. Extensive experiments show that we achieve a speedup of 10.69-23.04× over commercial field solver COMSOL and a speedup of 5.20-11.87× over the traditional stochastic methods.

Yield analysis has grown in significance with the increasing integration of SRAM arrays. The post-layout simulation introduces strong inter-column correlations in SRAM caused by parasitic parameters, thereby complicating yield analysis. However, most existing methods only consider the pre-layout simulation of SRAM circuits. In this paper, we present BAGNet: a boundary-aware Graph Neural Network (GNN) for SRAM yield analysis in post-layout simulation. We introduce a GNN module that learns the graph representations of SRAM arrays while generating feature vectors. We then construct an accurate surrogate model by the Multilayer Perceptron (MLP) to provide predictions for circuit performances. Given that delineating failure boundaries is vital for yield estimation, we propose an innovative nonlinear mapping strategy and an adaptive iterative strategy integrated with BAGNet, thus endowing our model with boundary-aware capability. After the model is built, we employ the importance sampling (IS) method on our surrogate model to deliver efficient and accurate yield estimation without time-consuming circuit simulations. Experimental results demonstrate that BAGNet outperforms the state-of-the-art method with 1.823.52x speedup, without losing accuracy.

Modern processor microarchitectures face increasing complexity, leading to larger search spaces and lengthy design-to-silicon validation flows. While reusing design knowledge across architectures offers potential efficiency gains, the common practice remains specific-architecture search due to inherent discrepancies in power, performance, and area (PPA) metrics between designs. We propose an attention-based microarchitecture search framework for effective cross-architecture knowledge transfer. Our approach propose a cross-attention network to capture interdependencies between microarchitectural topology and design tool configurations, enabling knowledge adaptation across architectures with minimal fine-tuning. Additionally, we complement it with an uncertainty-guided optimization strategy that efficiently navigates search based on specific user preferences. Experimental results demonstrate our approach outperforms previous methods with 68.16% higher hypervolume indicators and 3.85× speed-up of time in reaching the same hypervolume. Furthermore, our approach successfully discovers design points that meet user-specified PPA targets that state-of-the-art (SOTA) methods failed to identify. Our code is publicly available at https://github.com/MarsH3107/ICAN, enabling broader adoption and encouraging further research in transferable processor design optimization.

With the rapid increase of the transistor number in VLSI, rapidly rising power density and temperatures make heat dissipation a major challenge in IC design and manufacturing. However, conventional deterministic thermal analysis methods have difficulties in obtaining local temperature solutions efficiently, and the existing stochastic method is inaccurate when dealing with thermal analysis problems involving Robin boundary conditions (BCs). In this article, a highly parallelized path integral random walk (PIRW) solver is innovatively proposed for steady-state thermal analysis with mixed BCs, especially Robin BCs. The rigorous calculation of the local time and the Feynman-Kac functional$\hat {e}_{c}(t)$are adopted to accurately handle Neumann and Robin BCs for the first time. Furthermore, based on the PIRW, we propose an accurate and microsecond-level precalculation PIRW (pPIRW) predictor, which precalculates time-consuming random walks, obtains temperatures by simple vector multiplication, and therefore is suitable for proactive thermal management. The pPIRW essentially calculates a partial inverse of large-scale matrices constructed from the finite difference-based compact thermal models (CTMs). Experimental results show that compared with 3D-ICE, the PIRW solver maintains high accuracy with a negligible error within$0.5~^{\circ }$C, achieves$136\times $–$209\times $speedup and$8.53\times $–$11.1\times $storage space reduction with all three kinds of BCs, and decreases to$1\times $–$1.53\times $speedup for lacking the absorbing Dirichlet boundary. The pPIRW further has speed improvement of 2.5e$4\times $–6.7e$6\times $and memory reduction of$36.6\times $–$42.5\times $over PIRW without loss of accuracy. Integrated within a thermal management strategy, the pPIRW predictor can eliminate all thermal conflicts while maintaining the highest working frequency. Meanwhile, pPIRW achieves$29.2\times $speedup and$634\times $memory reduction over the CTM during the offline precalculation stage.

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This article proposes GiFt, a parameter-free initialization technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multiresolution smooth signals of circuit graphs to generate optimized initial placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Moreover, we present GiFtPlus, an enhanced version of GiFt, which is more efficient in handling large-scale circuit placement and can accommodate location constraints. Experimental results on public benchmarks show that GiFt and GiFtPlus significantly improve placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, the recently proposed GPU-accelerated analytical placer DREAMPlace uses up to 50% more total runtime than GiFtPlus-DREAMPlace.

Bayesian optimization (BO) is more efficient in automatically synthesizing operational amplifier (opamp) topologies compared to conventional methods. However, the design space for behavior-level opamp topologies involves numerous connections that are difficult to comprehend, and evaluating each topology incurs substantial computational costs. To tackle these challenges, this brief introduces ATOM, an automatic opamp topology synthesis framework. We construct a concise design space for behavior-level opamp topologies, consisting of topologies that designers can easily understand. We propose an opamp topology optimization method that incorporates freeze-thaw BO. This method efficiently explores the design space and expedites the evaluation process. Experimental studies demonstrate that ATOM outperforms state-of-the-art topology synthesis methods in terms of success rate and optimization results while reducing the number of required simulations by up to 8.15 times. The source code for ATOM is available athttps://github.com/Jinyi-Shen/ATOM.

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform.

The synthesizable and parameterizable RISC-V microarchitecture, combined with multiobjective optimization-based design space exploration (DSE), facilitates agile adaptation to various microprocessor designs for customized applications. However, to enhance design quality, DSE must consider both architecture parameters and EDA tool parameters, resulting in exponentially increased optimization complexity with the dimensionality of parameters. Exhaustively exploring the whole design space is impossible. Additionally, due to the time-consuming nature of microprocessor simulation, minimizing the number of simulations is imperative. Addressing these challenges, we propose asynchronous parallel Pareto set learning for microarchitecture DSE (APPLE-DSE). APPLE-DSE utilizes the Pareto set learning (PSL) technique to obtain an approximate Pareto front with a “light-weight” evaluation. PSL captures the structural characteristics of the Pareto set (PS) guided by the surrogate models, enabling it to explore any tradeoff area in the approximate PS. Employing the probabilistic reparameterization (PR) technique, APPLE-DSE adapts PSL to handle discrete variables. Furthermore, APPLE-DSE incorporates a simulation time-aware asynchronous parallel scheduling strategy to further enhance optimization efficiency. Experimental results show that APPLE-DSE achieves a maximum improvement of 16.81% in hypervolume within the same time budget and a$127.73\times $speedup in algorithm run time per iteration compared to state-of-the-art methods.

Optimizing multiple competitive black-box objectives with tight constraints poses a common challenge in analog circuit design. Multiobjective Bayesian optimization (MOBO) is a sample-efficient approach to identify the optimal tradeoffs, namely, the Pareto front (PF). However, existing MOBO methods exhibit limitations in handling high-dimensional design space, large sample budgets, many objectives and tight constraints. This article introduces VTSMOC, a sample-efficient and computationally lightweight approach for addressing high-dimensional constrained multiobjective optimization problems. VTSMOC decomposes the design space into Voronoi cells, dynamically constructing a hierarchical Voronoi tree through clustering observations with dominance relationships. Promising leaf nodes in the Voronoi tree are pinpointed by traversing the tree with gradient bandit. The diversity of PF is ensured by parallel sampling within different promising cells, selected using a diffusive strategy. We also propose the expected PF improvement (EPFI) and probability of PF improvement (PPFI) acquisition functions to facilitate the PF efficiently along the radial direction of PF surface. Compared to state-of-the-art methods, VTSMOC achieves significant improvements in both sample and computational efficiency.

Design automation of complex analog circuits (CAC) with multiple sub-blocks is challenging mainly due to large design search space, uncertain intermediate subgoal creation, and lengthy CAC simulation runtime. In this work, we propose a hierarchical and heterogeneous integration framework as a fully automated and time-efficient CAC design optimization solution. In Particularly, we (i) decompose CAC into two levels hierarchically and for the first time introduce hierarchical RL agents with hindsight and subgoal testing to automate the subgoal creation between these two levels. The subgoal converges to the optimal value through algorithm interactions. (ii) We enable high-level design space dimensionality reduction, minimize CAC simulation runs through a buffer hold, and employ low-level sub-block execution parallelization to reduce overall runtime. (iii) We construct a heterogeneous integration of different RL algorithms and black-box optimization algorithms in hierarchy to further boost the speed by benefiting both from the hierarchical structure and the advantages of each different algorithm. Experiments on four CAC topologies demonstrate that this framework achieves a maximum of 11.4× speed up compared to existing methods at the desired figure-of-merit. This work opens up a time efficient design automation route for complex analog circuits and systems.

Logic synthesis is crucial in digital design automation, significantly enhancing performance, reducing area, and lowering power consumption through technology-independent optimization followed by technology mapping. Logic rewriting, a key strategy for optimization, iteratively replaces portions of logic circuits with more compact implementations. Despite historical advancements, challenges remain in subgraph selection, technology-dependent metrics, and performance-runtime trade-offs. This article presents a novel Te chnology- a ware logic R e W riting ( TeaRW ) framework to address these challenges. TeaRW incorporates a technology-aware rewriting algorithm that evaluates post-mapping netlist metrics during the technology-independent optimization phase. It employs four distinct subgraph rewriting techniques to maximize the effectiveness of local optimization. For efficiency, TeaRW utilizes an optimized logic representation database derived from exact synthesis, enabling cost-effective replacements. Experimental results on real-world benchmarks show improvements over the ABC tool, including an average Area-Delay-Product (ADP) improvement of 8.18% in delay-oriented optimization and 0.28% in area-oriented optimization when compared to state-of-the-art optimization scripts.

The optimization of operational amplifiers, including topology design and parameter tuning, is significantly challenging, given the high-dimensional and heterogeneous characteristics of the design space. This paper presents MACRO, a novel approach to operational amplifier design that employs multi-agent reinforcement learning for cross-layer optimization. We model the sequentially executed topology design and parameter tuning tasks as a Markov decision process, where the high-dimensional design space is effectively transformed into a series of manageable action spaces at each step. Two agents are meticulously tailored to specialize in these two distinct tasks respectively. The co-evolution of the agents is ensured by sharing design information and customizing the policy-gradient training method. Experimental results show that, compared with state-of-the-art methods, MACRO can produce superior-performing circuits while maintaining competitive design efficiency.

The escalated intricacy of analog circuits, compounded by the high-dimensional nature of the design space, introduces complexities in optimizing circuit performance. Since the evaluation cost, often through circuit simulation, is resource-intensive and time-consuming, it is crucial to obtain a feasible design with a decent Figure of Merit (FOM) value within a limited simulation budget. In this study, we conduct an in-depth review and analysis of cutting-edge exploration and exploitation techniques developed to address the intricacies encountered in analog circuit design automation. Moreover, to enable algorithmic comparisons and advance the state of the field, we provide benchmarks encompassing analog circuit netlists with high-dimensional design variables, which empower researchers to rigorously assess and refine their optimization algorithms, leading to enhanced efficacy and novel developments.

For analog circuit sizing, constrained multi-objective optimization is an important and practical problem. With the popularity of multi-core machines and cloud computing, parallel/batch computing can significantly improve the efficiency of optimization algorithms. In this paper, we propose an Asynchronous Batch Constrained Multi-Objective Bayesian Optimization algorithm (ABCMOBO). Since the performances below the specifications are worthless, we adopt a dynamic reference point selection on the expected hypervolume improvement acquisition function for constraint handling. To save the time of waiting for all the simulations in the same batch to complete, ABCMOBO asynchronously evaluates the next candidate point if there is an idle worker. The experimental results quantitatively demonstrate that our proposed algorithms can reach 3.49 ~ $8.18 \times$ speed-up with comparable optimization results compared to the state-of-the-art asynchronous/synchronous batch multi-objective optimization methods.

This paper presents Artisan, an automated operational amplifier design framework using large language models (LLMs). We develop a bidirectional representation to align abstract circuit topologies with their structural and functional semantics. We further employ Tree-of-Thoughts and Chain-of-Thoughts approaches to model the design process as a hierarchical question-answer sequence, implemented by a mechanism of multi-agent interaction. A high-quality opamp dataset is developed to enhance the design proficiency of the Artisan-LLM. Experimental results demonstrate that Artisan outperforms state-of-the-art optimization-based methods and benchmark LLMs, in success rate, circuit performance metrics, and interpretability, while accelerating the design process by up to 50.1X. Artisan will be released for public access.

This study presents a novel high-dimensional multi-objective optimization method via adaptive gradient-based subspace sampling for analog circuit sizing. To handle constrained multi-objective optimization, we exploit promising regions from a non-crowded Pareto front, with lightweight Bayesian optimization (BO) based on a novel approximate constrained expected hypervolume improvement. This lightweight BO is computational efficient with constant complexity concerning simulation numbers. To tackle high-dimensional challenges, we reduce the effective dimensionality around promising regions by sampling candidates in an adaptive subspace. The subspace is constructed with gradients and previous success steps with their significance decaying over iterations. The gradients are approximated by sparse regression without additional simulations. The experiments on synthetic benchmarks and analog circuits illustrate advantages of the proposed method over Bayesian and evolutionary baselines.

Automated analog circuit design migration significantly alleviates the burden on designers in circuit sizing under various operating conditions. Conventional methods model the migration problem as black-box optimization, requiring excessive iterations of costly simulations to converge. Reinforcement learning exhibits significant promise in transfer learning, as it enables the generation of circuits that fulfill specifications efficiently. The paper proposes a novel value decomposition-based multi-agent reinforcement learning framework, aiming to model complex analog circuits and eliminate the need for manually defined specifications of sub-circuits for new operating conditions. Additionally, it incorporates domain randomization techniques to efficiently generate circuits that meet unforeseen scenarios with minimal simulations. Experiment demonstrates that our algorithm can efficiently generate circuits meeting specifications under new operating conditions in few number of steps, outperforming state-of-the-art methods.

Inverse Lithography Technology (ILT) is an important Resolution Enhancement Technology (RET) in chip manufacturing. Due to the high computational demands of ILT, large-scale layouts are typically partitioned into smaller tiles for independent processing. In this paper, we propose a multigrid-Schwarz method to overcome challenges in tile assembly. Experimental results show that our approach achieves comparable performance to the full-chip ILT, offering increased parallelizability and speedup in parallel mode. Unlike the traditional divide-and-conquer algorithm, it effectively alleviates discontinuities of tile stitching, preventing manufacturing failures.

We propose a novel scalable Bayesian optimization method with truncated subspace sampling (tSS-BO) to tackle high-dimensional optimization challenges for large-scale analog circuit sizing. To address the high-dimensional challenges, we propose subspace sampling subject to a truncated Gaussian distribution. This approach limits the effective sampling dimensionality down to a constant upper bound, independent of the original dimensionality, leading to a significant reduction in complexity associated with the curse of dimensionality. The distribution covariance is iteratively updated using a truncated flow, where approximate gradients and center steps are integrated with decaying prior subspace features. We introduce gradient sketching and local Gaussian process (GP) models to approximate gradients without additional simulations to mitigate systematic errors. To enhance efficiency and ensure compatibility with constraints, we utilize local GP models for the selection of promising candidates, avoiding the cost of acquisition function optimization. The proposed tSS-BO method exhibits clear advantages over state-of-the-art methods in experimental comparisons. In synthetic benchmark functions, the tSS-BO method achieves up to$4.93\times$evaluation speedups and a remarkable over$30\times$algorithm complexity reduction compared to the Bayesian baseline. In real-world analog circuits, our method achieves up to$2\times$speedups in simulation number and runtime.

We propose a pyramid scene parsing network (PSPN) with skip-connection architecture to effectively utilize physical information that characterizes IR drop distribution, including current source locations, via locations, and asymmetric topological connections, achieving highly accurate IR drop prediction for power delivery networks (PDN) of varying scales, even with a limited dataset. Skip-connection architecture preserves the positional information of current sources, which often correlates with large IR drop, facilitating the identification of hotspots. We incorporate via locations into the model to effectively describe the topological connection distance between voltage sources and different nodes in the multi-layer PDN, while the traditional method only considers the horizontal distance between nodes and voltage sources, which is invalid for prediction. To capture asymmetric connection features within the PDN efficiently, we introduce a shape-adaptive convolutional kernel to solve the problem of inadequate extraction of feature information in a traditional method. Finally, we propose a loss function with Kirchhoff's law constraints to ensure the model's prediction aligns with the electrical characteristics of the circuit, which can't be guaranteed by traditional machine learning-based methods only taking the prediction accuracy into consideration. Our results, based on training with only 100 synthetic circuits, demonstrate the superiority of our method over the state-of-the-art prediction technique. Across evaluations on 10 real circuits, our approach consistently delivers a 50 % improvement in precision.

This paper introduces a novel circuit simulator of k-input lookup table (k-LUT) networks, based on semi-tensor product (STP). STP-based simulators use computation of logic matrices, the primitives of logic networks, as opposed to relying on bitwise logic operations for simulation of k- LUT networks. Experimental results show that our STP-based simulator reduces the runtime by an average of 7.2 ×. Furthermore, we integrate this proposed simulator into a SAT sweeper. Through a combination of structural hashing, simulation, and SAT queries, SAT sweeper simplifies logic networks by systematically merging graph vertices from input to output. To enhance the efficiency, we used STP-based exhaustive simulation, which significantly reduces the number of false equivalence class candidates, thereby improving the computational efficiency by reducing the number of SAT calls required. When compared to the state-of-the-art SAT sweeper, our method demonstrates an average 35% runtime reduction.

Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduced AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. AnalogGym's user-friendly design allows researchers to easily adapt it for robust, transparent comparisons of state-of-the-art methods, while also exposing them to real-world industrial design challenges, enhancing the practical relevance of their work. Additionally, we have conducted a comprehensive comparison study of various analog sizing methods on AnalogGym, highlighting the capabilities and advantages of different approaches. AnalogGym is available in the GitHub repository1. The documentations are also available at2.

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics.

Current state-of-the-art (SOTA) analog circuit sizing methods predominantly rely on derivative-free algorithms. However, these methods struggle with sample efficiency due to the lack of derivative information, acting as a bottleneck for further advancements. In contrast, classic sensitivity analysis computes partial derivatives of circuit performance with respect to design parameters, enabling efficient first-order optimization. Yet, sensitivity-driven analog sizing has seen limited use due to: 1) accumulated numerical errors from nonlinear devices, and 2) the complex, non-convex nature of circuit optimization problems, which makes local search methods like gradient descent ineffective for global optimization. To address these challenges, this paper equips SOTA analog sizing algorithms with derivative awareness and proposes DarBO, a Derivative-aware Bayesian Optimization method. DarBO uses derivatives from error-suppressed adjoint sensitivity analysis to improve Gaussian process posteriors in local optimization, enhancing convergence with fewer circuit simulations. For global exploration, DarBO adapts a derivative-aware Gaussian mixture model (d-GMM) for region partitioning and a gradient-driven Monte Carlo tree search (d-MCTS) for subregion selection. By bridging classic sensitivity-driven analog sizing with SOTA Bayesian optimization algorithms, DarBO offers an efficient and robust solution for analog circuit sizing. Experimental results show that DarBO achieves up to 5.0 × acceleration in terms of the number of circuit simulations compared to existing first-order and derivative-free optimization methods.

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption.

Bayesian optimization (BO) is a well-established methodology for optimizing costly black-box functions. However, the sparse observations in the high-dimensional search space pose challenges in constructing reliable Gaussian Process (GP) models, which leads to blind exploration of the search space. We propose a novel Voronoi Graph Traversing (VGT) algorithm to extend BO to ultra high-dimensional problems. VGT employs a Voronoi diagram to mesh the design space and transform it into an undirected Voronoi graph. VGT explores the search space by iteratively performing path selection, promising cell sampling, and graph expansion operations. We introduce a UCB-based global traversal strategy to select the path towards promising Voronoi cells. Then we perform local BO within the promising cell and train local GP with a neighboring subset. The intrinsic geometric boundaries and adjacency of the Voronoi graph assist in fine-tuning the trajectory of local BO sampling. We also present a subspace enhancement approach for the intrinsic low-dimensional problems. Experimental results, including both synthetic benchmarks and real-world applications, demonstrate the proposed approach’s state-of-the-art performance for tackling ultra high-dimensional problems ranging from hundreds to one thousand dimensions.

Abstract Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an “AI4EDA” approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This study argues for a paradigm shift from AI4EDA towards AI-rooted EDA from the ground up, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, register-transfer level (RTL) designs, circuit netlists, and physical layouts. We champion the creation of large circuit models (LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-rooted philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound “shift-left” in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design-tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area (PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems’ capabilities.

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce and compare three different multiagent RL algorithms and corresponding frameworks to demonstrate the effectiveness of the MA-RL method. (iv) employing twin-delayed techniques and proximal policy to further boost training stability and accomplish higher performances. (v) The impacts of different reward function definitions as well as different state settings of MA-RL agents are investigated to further improve the robustness of this framework. (vi) Experiments on three different complex analog circuit topologies (GBA, DLL and SAR ADC) and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits’ design. This work shines the light for future large scale analog circuit system design automation.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. In the dummy filling flow, dummy synthesis works as the key step to adjust the post- CMP profile height. However, existing dummy synthesis optimization approaches usually fail to balance the filling quality and efficiency. This article proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving$8134\times $speedup on gradient calculation by backward propagation. Entrenched in the CMP neural network models, we further implement an improved version of NeurFill (pNeurFill) to alleviate the post- CMP height variation caused by dummy perimeter. After each iteration of dummy density optimization, an additional perimeter adjustment based on a given candidate dummy pattern set is applied to search for the optimal perimeter fill amount. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods. The extra perimeter adjustment strategy in pNeurFill can achieve an average 66.97Å decreasing in height variation and 8.92% quality improvement compared to NeurFill. This will provide guidance for DFM so as to increase IC chip yield.

In this article, we propose a novel batch Bayesian and Gaussian process enhanced subspace derivative free optimization (DFO) method to solve high-dimensional and simulation-expensive analog circuit optimization problems. The existing optimization methods, such as Bayesian optimization and trust region-based DFO, suffer from under-fitting surrogate models in high-dimensional problems, which leads to inefficient optimization and suboptimal solutions. To address this issue, we propose a novel approach that integrates a batch Bayesian querying strategy for exploring the global design space and a Gaussian process (GP) enhanced subspace DFO method for exploiting promising regions in effective low-dimensional subspace. The GP is used to approximate the gradient pattern for subspace establishment, significantly enhancing the simulation efficiency. The selection of promising regions is based on an innovative region acquisition function that estimates the weighted local expected improvement. The effectiveness of the proposed method is demonstrated on real-life analog circuits, achieving${2.05\times - 17.65\times }$simulation number speedup and${1.37\times - 16.11\times }$runtime speedup compared with the state-of-the-art optimization methods.

Interconnect capacitive parasitics are becoming increasingly dominant at finer technology nodes. Chip-scale interconnect capacitance extraction is a critical but challenging task. The structure patterns of nanometer-scale on-chip interconnects are complex. The accuracy of widely used pattern-matching-based capacitance extraction methods is limited by labor-intensive pattern library construction. This work presents graph neural network (GNN)-Cap, a GNN-based method for chip-scale interconnect capacitance extraction. GNN-Cap uses graph presentation learning to model the complex interconnect structural patterns, which enables accurate and efficient prediction of wiring capacitances. Compared with StarRC, the de facto commercial capacitance extraction tool, GNN-Cap achieves a speed up of$11\times $to$13\times $, and reduces the average relative errors of total and coupling capacitances by 81% and 59%, respectively.

Exploring the design space of RISC-V processors faces significant challenges due to the vastness of the high-dimensional design space and the associated expensive simulation costs. This work proposes a region of interest (ROI)-driven method, which focuses on the promising ROIs to reduce the over-exploration on the huge design space and improve the optimization efficiency. A tree structure based on self-organizing map (SOM) networks is proposed to partition the design space into ROIs. To reduce the high dimensionality of design space, a variable selection technique based on a sensitivity matrix is developed to prune unimportant design parameters and efficiently hit the optimum inside the ROIs. Moreover, an asynchronous parallel strategy is employed to further save the time taken by simulations. Experimental results demonstrate the superiority of our proposed method, achieving improvements of up to 43.82% in performance, 33.20% in power consumption, and 11.41% in area compared to state-of-the-art methods.

The reliability of circuits is significantly affected by process variations in manufacturing and environmental variation during operation. Current yield optimization algorithms take process variations into consideration to improve circuit reliability. However, the influence of environmental variations (e.g., voltage and temperature variations) is often ignored in current methods because of the high computational cost. In this article, a novel and efficient approach named BNN-BYO is proposed to optimize the yield of analog circuits in multiple environmental corners. First, we use a Bayesian Neural Network (BNN) to simultaneously model the yields and performances of interest in multiple corners efficiently. Next, the multi-corner yield optimization can be performed by embedding BNN into a Bayesian optimization framework. Since the correlation among yields and performances of interest in different corners is implicitly encoded in the BNN model, it provides great modeling capabilities for yields and their uncertainties to improve the efficiency of yield optimization. Our experimental results demonstrate that the proposed method can save up to 45.3% of simulation cost compared to other baseline methods to achieve the same target yield. In addition, for the same simulation cost, our proposed method can find better design points with 3.2% yield improvement.

Bayesian optimization (BO) is an efficient global optimization method for expensive black-box functions, but the expansion for high-dimensional problems and large sample budgets still remains a severe challenge. In order to extend BO for large-scale analog circuit synthesis, a novel computationally efficient parallel BO method, D 3 PBO, is proposed for high-dimensional problems in this work. We introduce the dynamic domain decomposition method based on maximum variance between clusters. The search space is decomposed into subdomains progressively to limit the maximal number of observations in each domain. The promising domain is explored by multi-trust region-based batch BO with the local Gaussian process (GP) model. As the domain decomposition progresses, the basin-shaped domain is identified using a GP-assisted quadratic regression method and exploited by the local search method BOBYQA to achieve a faster convergence rate. The time complexity of D 3 PBO is constant for each iteration. Experiments demonstrate that D 3 PBO obtains better results with significantly less runtime consumption compared to state-of-the-art methods. For the circuit optimization experiments, D 3 PBO achieves up to 10× runtime speedup compared to TuRBO with better solutions.

Floorplanning is a complex physical design problem that produces initial locations of movable objects, the quality of which has a great impact on downstream tasks such as placement and routing. To improve the efficacy of floorplanning, machine learning techniques have recently been recruited for help. However, the application-specific location constraints (IOs and cells with fixed locations) pose a huge challenge for machine learning. This article presents a novel uniformization approach by Dirichlet boundary conditions, which decomposes floorplanning into two easier-to-solve subproblems, namely a convex quadratic wirelength optimization problem with location constraints and an NP-hard combinatorial problem with homogeneous Dirichlet boundary conditions. The former problem is efficiently solved using quadratic optimization, and the latter is addressed by efficient graph inference using the proposed hierarchical GNN-based model. The proposed floorplanner called DPlanner has been integrated with state-of-the-art mixed-size placers to generate high-quality placement solutions with up to 56% and 41% improvement in placement iterations and runtime. In addition, compared to the state-of-the-art integrated floorplanning-placement flow, DPlanner achieves over a 20% improvement in placement iteration and more than a 21% reduction in total runtime, along with a 2% average reduction in wirelength.

As the resolution continues to increase, the scale of the power grid of the flat panel display (FPD) becomes huge. This imposes a severe computational challenge for analysis and storage. In this paper, based on the highly periodic FPD structure, we present an efficient simulator which contains a novel stamping scheme and a fast structural solver. Experiments on real industrial cases show that compared to the conventional stamping scheme, our proposed stamping scheme achieves up to 118× speedup in 74× less memory; compared to the state-of-art direct solver, Cholmod, our proposed structural solver achieves up to 17× speedup in 5× less memory.

Inverse Lithography Technology (ILT) is a widely investigated method to improve the yield of chip manufacturing. However, high computational complexity and difficulty in fabricating curvilinear shapes have hindered the widespread adoption of ILT. This paper presents an efficient ILT framework, including a multi-level resolution method for simulation acceleration, a downsampling strategy for mask optimization, and an improved mask binary function to improve mask printability. Experimental results show that the proposed method outperforms state-of-the-art methods with at least a 33.8% reduction in L2 loss and a 15.5% reduction in PVBand.

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

A constrained Voronoi tree-based domain decomposition method for high-dimensional Bayesian optimization is proposed to solve large scale analog circuit synthesis problems, which can be formulated as high-dimensional heterogeneous black-box optimization. Hierarchical Voronoi tree progressively breaks down the design space into partitions with implicit performance boundaries such that promising regions are efficiently explored. Fast exploitation is ensured in Voronoi nest via local Bayesian optimization with a few observations. A slice-enhanced Gibbs sampling method is proposed to sample acquisition function cMES in irregular polyhedrons with design constraints. Compared with state-of-the-art methods, cVTS achieves significant speed up without loss of accuracy.

This paper presents a neural architecture search scheme for chip layout hotspot detection. In this work, hotspot detectors, in the form of neural networks, are modeled as weighted directed acyclic graphs. A variational autoencoder maps the discrete graph topological space into a continuous embedding space. Bayesian Optimization performs neural architecture search in this embedding space, where an architecture performance predictor is employed to accelerate the search process. Experimental studies on ICCAD 2012 and ICCAD 2019 Contest benchmarks demonstrate that, the proposed scheme significantly improves the agility of previous neural architecture search schemes, and generates hotspot detectors with competitive detection accuracy, false alarm rate, and inference time.

Existing hardware emulators use either FPGA or Boolean processors, which suffer from long compile time and poor debuggability (FPGA-based), or low emulation performance (Boolean processor-based). This work presents Sphinx, a hybrid Boolean processor-FPGA hardware emulation platform aiming to overcome these shortcomings. Sphinx hardware is a new hybrid architecture that integrates software programmable Boolean processors and FPGAs. Sphinx software is a compilation framework that conducts incremental design partitioning and implements the design-under-test components on Boolean processors and the rest on FPGAs. Together, Sphinx enables an incremental emulation flow and demonstrates high emulation performance, fast compile turnarounds, and good debuggability.

Efficient high-dimensional performance modeling of analog/RF circuits over multiple corners is an important-yet-challenging task. In this article, we propose a novel performance modeling approach for analog/RF circuits, referred to as correlated Bayesian model fusion (C-BMF). The key idea is to encode the correlation information for both model template and coefficient magnitude among different corners by using a unified prior distribution. Next, the prior distribution is combined with a few simulation samples via Bayesian inference to efficiently determine the unknown model coefficients. Two circuit examples designed in a commercial 40-nm CMOS process demonstrate that C-BMF achieves about$2\times $cost reduction over the traditional state-of-the-art modeling technique without surrendering any accuracy.

Device sizing is a challenging problem for analog circuit design. Traditional methods depend on domain knowledge and intensive simulations to search for feasible parameters. Recent studies apply the Bayesian optimization (BO) and a Gaussian process (GP) model in analog circuit synthesis to improve efficiency. The BO framework automatically selects the parameter candidates by inferring the surrogate GP model. However, naive BO employs a sequential updating strategy which is inefficient in a multicore environment. Besides, the widely used GP model requires costly high fidelity data, which are obtained from fine simulations. In this article, we propose a constrained batch BO approach with a multifidelity (MF) model to solve the above difficulties. The batch BO exploits parallel computing and selects promising parameters by multiple acquisition function ensemble. In addition, the MF GP model adapts the low fidelity data obtained from coarse simulations. Specifically, the proposed method incorporates information gain in a weighted clustering algorithm to refine the parameter candidates. As a result, the proposed method maintains the candidates’ quality and diversity, which speeds up the optimization convergence. In the experiments, we demonstrate the efficiency of the proposed approach on three real-world circuits. The results show that our approach reduces the simulation costs by at least 54.6% compared to the state-of-the-art baselines.

Graph spectral sparsification-based preconditioning technique has shown promising results for power grid analysis. However, the conventional methods converge slowly for high-accuracy requirement. In this work, we propose an efficient approach to address this issue. Instead of using the Cholesky factorization, we employ the incomplete Cholesky factorization to factorize the spectral sparsifier. We also propose a concept of graph spectral pattern, which can further reduce the preconditioned conjugate gradient (PCG) iterations using less number of nonzeros. Experiments show that under 10−6 relative tolerance, our proposed preconditioning technique achieves$1.17\times $speedup compared to AMGPCG in average; compared to the conventional spectral sparsification-based preconditioning techniques, our proposed approach achieves up to$8.53\times $speedup of the factorization,$8.74\times $speedup of the PCG iteration, and$5.6\times $speedup of the total time. Moreover, the speedup of the total time continues to enlarge for higher-accuracy requirement, e.g., 10−12. Finally, but not least, our method is compatible with existing graph spectral sparsification algorithms for power grid analysis.

The operational amplifier is a key building block in analog systems. However, the design process of the operational amplifier is time consuming and heavily depends on engineers’ experiences. This article presents OPAMP-Generator, an analog operational amplifier generator, which automates the full design flow from user-defined specifications to GDSII layout without human intervention. OPAMP-Generator includes behavioral-level topology optimization, efficient sizing algorithm based on the classical$ {g_{m}/I_{d}}$design methodology, and automated layout generation. The behavioral-level description of the opamp is represented by the directed acyclic graph (DAG) and a customized variational graph autoencoder is proposed to embed the discrete graph representation into a low-dimensional continuous space. The topology of the opamp can thus be optimized in the latent space, which greatly improves the optimization efficiency. The sizing algorithm based on${g_{m}/I_{d}}$methodology can guarantee the quality of transistor-level circuit implementation. The constraints of the layouts can be naturally derived from the topology level, which facilities the automatic generation of layouts. Experimental results demonstrate that our proposed method can efficiently synthesize operational amplifiers with competitive performances compared to manual designs.

In this paper, we propose an analog circuit building block generator, which is composed of a layout-aware analog circuit sizing scheme and an automated analog circuit layout generator. We reformulate the analog circuit sizing problem as a novel constrained multi-objective optimization problem and propose a multi-objective Bayesian optimization scheme that can find multiple different qualified designs. We further leverage a nested multi-fidelity Bayesian optimization method in layout-aware sizing to counterbalance the schematic-level simulation and the expensive post-layout simulation without losing efficiency. The automated layout generator enables the in-loop layout generation, and thus it is possible to find a set of valid post-layout results directly. The experimental results on three real-world analog circuits have demonstrated the efficiency of our proposed approach.

Fast verification for the extremely large-scale power grid is demanding as CMOS technology advances consistently. In this work, we propose ESPSim, an efficient scalable power grid simulator based on a parallel smoothed aggregation-based algebraic multigrid technique. ESPSim has the ability to do fast DC and transient analysis through MPI and adaptive timestep control mechanism. Thanks to the smoother applied on the prolongation operator, ESPSim copes well with the convergence rate on extremely large-scale power grid transient analysis. Extensive experiments are conducted with a variety of serial/parallel solvers. The runtime of ESPSim is linear with case size. With 16 processors, 1,000 timesteps transient analysis of 63.4M nodes can be completed in 22.1 min. Over 22× speedup compared to the well-known direct solver Cholmod is observed.

Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the density constraint, which in essence is a process of constructing an optimized mapping from circuit connectivity to physical locations. Proven to be an NP-hard problem, chip floorplanning is difficult to be solved efficiently using algorithmic approaches. This article presents GraphPlanner, a variational graph-convolutional-network-based deep learning technique for chip floorplanning. GraphPlanner is able to learn an optimized and generalized mapping between circuit connectivity and physical wirelength and produce a chip floorplan using efficient model inference. GraphPlanner is further equipped with an efficient clustering method, a unification of hyperedge coarsening with graph spectral clustering, to partition a large-scale netlist into high-quality clusters with minimized inter-cluster weighted connectivity. GraphPlanner has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, GraphPlanner improves placement runtime by 25% with 4% wirelength reduction on average.

Analog circuits are characterized by various circuit performances obtained from multiple testbenches which need to be simulated independently. In this paper, we propose an efficient Bayesian optimization approach for multi-testbench analog circuit design. Predictive Entropy Search with Constraints (PESC) is applied for selecting the suitable testbench to simulate, and time-weighted PESC (wPESC) is also proposed considering different analysis time. Furthermore, the Feasibility Expected Improvement (FEI) acquisition function for constraints and solving a multi-modal optimal problem of FEI are proposed to improve the efficiency of exploring feasible regions. The proposed approach can gain$2.{7}\sim 3.8\times$speedup compared with the state-of-the-art method, and achieve better optimization results.

Floorplanning has long been a critical physical design task with high computation complexity. Its key objective is to determine the initial locations of macros and standard cells with optimized wirelength for a given area constraint. This paper presents Flora, a graph attention-based floorplanner to learn an optimized mapping between circuit connectivity and physical wirelength, and produce a chip floorplan using efficient model inference. Flora has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, Flora improves placement runtime by 18%, with 2% wirelength reduction on average.

This paper presents an efficient yield optimization method for analog circuits via Gaussian process classification and varying-sigma sampling. To quickly determine the better design, yield estimations are executed at varying sigma of process variations. Instead of regression methods requiring accurate yield values, a Gaussian process classification method is applied to model these preference information of designs with binary comparison results, and the preferential Bayesian optimization framework is implemented to guide the search. Additionally, a multi-fidelity surrogate model is adopted to learn the yield correlation at different sigmas. Compared with the state-of-the-art methods, the proposed method achieves up to 12× speed-up without loss of accuracy.

Operational amplifier is a key building block in analog circuits. However, the design process of the operational amplifier is complex and time-consuming, as there are no practical automation tools available in the industry. This paper presents a new topology optimization method for operational amplifiers. The behavioral description of the operational amplifier is described using a directed acyclic graph (DAG), which is then transformed into a low-dimensional embedding in continuous space using a variational graph autoencoder. Topology search is performed in the continuous embedding space using stochastic optimization methods, such as Bayesian Optimization. The yield search results are then transformed back to operational amplifier topologies using a graph decoder. The proposed method is also equipped with a surrogate model for performance prediction. Experimental results show that the proposed approach can achieve significant speedup over the genetic searching algorithms. The produced three-stage operational amplifiers offer competitive performance compared to manual designs.

Lithography hotspot detection is of great importance in chip manufacturing. It aims to find patterns that may incur defects in the early design stage. Inspired by the success of deep learning in computer vision, many works convert layouts into images, turn the hotspot detection problem into an image classification task. Traditional graph-based methods consume fewer computer resources and less detection time compared to image-based methods, but they have too many false alarms. In this paper, a hotspot detection approach via the graph neural network (GNN) is proposed. We also propose a novel representation model to map a layout to one graph, in which we introduce multi-dimensional features to encode components of the layout. Then we use a modified GNN to further process the extracted layout features and get an embedding of the local geometric relationship. Experimental results on the ICCAD2012 Contest benchmarks show our proposed approach can achieve over 10x speedup and fewer false alarms without loss of accuracy. On the ICCAD2020 benchmark, our model can achieve 2.10% higher accuracy compared with the previous approach.

In this work, we propose a path integral random walk (PIRW) solver, the first accurate stochastic method for steady-state thermal analysis with mixed boundary conditions, especially involving Fourier heat transfer Robin boundary conditions. We innovatively adopt the strictly correct calculation of the local time and the Feynman-Kac functional êc (t) to handle Neumann and Robin boundary conditions with high precision. Compared with ANSYS, experimental results show that PIRW achieves over 121× speedup and over 83× storage space reduction with a negligible error within 0.8° C at a single point. An application combining PIRW with low-accuracy ANSYS for the temperature calculation at hot-spots is provided as a more accurate and faster solution than only ANSYS used.

In this paper, we propose an efficient batch Bayesian optimization algorithm for analog circuit synthesis based on the multi-points selection criterion. Simplex evolution operator and Niching Migratory Multi-Swarm Optimizer (NMMSO) are used to generate candidates. The multi-point selection criterion is adopted to select multiple points from the candidates for parallel evaluation which can make full use of the computing resources. The experimental results demonstrate that this method can reduce the simulation time effectively while achieving better optimization results. Compared with the Multi-objective Acquisition function Ensemble (MACE) and the weighted expected improvement based Bayesian optimization (WEIBO), our proposed approach can accelerate the optimization process by up to $3 \times$ and $27 \times$.

The resource-sharing constraints can be imposed by limiting the maximum allowable number of components for individual functional units in the scheduling process. However, the sharing of the functional units is not explicitly considered in the scheduling procedure. In this paper, we propose a SAT-based scheduling algorithm for high-level synthesis considering the resource-sharing problem. Several pruning strategies have been proposed to reduce the search space. Meanwhile, a minimum-cost network-flow algorithm is proposed to accelerate the repeatedly called scheduling procedure.

Lithography hotspot detection is of great significance in chip manufacturing. Hotspots are those patterns that may cause fatal defects in the final tape-out, such as short or open circuits. Therefore, identifying and eliminating hotspots in the early design stage can improve chip yield and reduce manufacturing costs. Traditionally, lithography simulation is used to detect hotspot patterns. But as the feature size shrinks and the design complexity increases, the lithography simulation of the entire chip requires a longer time overhead, which seriously delays the design cycle. Consequently, many deep learning-based methods have been proposed to accelerate hotspot detection. These approaches all show a good performance in the ICCAD 2012 contest benchmarks. However, deep neural networks are vulnerable to adversarial attacks. In this paper, we propose to generate samples by adjusting the critical distance between polygons in the layout based on existing patterns. Layouts are very sensitive to the distance between polygons, the type of a layout may flip by slight modifications in the distances. These adversarial samples are closer to the decision boundary of neural networks than the original ones. Experimental results show that the accuracy of neural network-based hotspot detectors drops significantly in the dataset formed by generated samples. Adding the generated samples to the training dataset improves the robustness and generalization ability of neural networks.

As the circuit feature size continuously shrinks down, hotspot detection has become a more challenging problem in modern design for manufacturability flows. Developed deep learning techniques have recently shown their superiorities on hotspot detection tasks. However, existing hotspot detectors can only handle defect detection from one small layout clip each time, thus, may be very time-consuming when dealing with a large full-chip layout. In this article, we develop a new end-to-end framework that can detect multiple hotspots in a large region at a time and promise a better hotspot detection performance. We design a joint auto-encoder and inception module for efficient feature extraction. A two-stage classification and regression framework is designed to detect hotspot with progressive accurate localization, which provides a promising performance improvement. Experimental results show that our framework enables a significant speed improvement over existing methods with higher accuracy and fewer false alarms.

In this article, to accurately estimate the rare failure rates for large-scale circuits (e.g., SRAM) where process variations are modeled as truncated normal distributions in high-dimensional space, we propose a novel truncated scaled-sigma sampling (T-SSS) method. Similar to scaled-sigma sampling (SSS), T-SSS distorts the truncated normal distributions by a scaling factor, resulting in an analytical model for failure rate estimation. By drawing random samples from the distorted distribution and estimating a sequence of scaled failure rates, we can solve all unknown model coefficients and predict the original failure rate by extrapolation. The accuracy of T-SSS is further assessed by estimating its confidence interval (CI) based on resampling. Our numerical results demonstrate that the proposed T-SSS method can achieve superior accuracy over the state-of-the-art method without increasing the computational cost.

With the aggressive and amazing scaling of the feature size of semiconductors, hotspot detection has become a crucial and challenging problem in the generation of optimized mask design for better printability. Machine learning techniques, especially deep learning, have attained notable success on hotspot detection tasks. However, most existing hotspot detectors suffer from suboptimal performance due to two-stage flow and less efficient representations of layout features. What is more, most works can only solve simple benchmarks with apparent hotspot patterns like ICCAD 2012 Contest benchmarks. In this article, we first develop a new end-to-end hotspot detection flow where layout feature embedding and hotspot detection are jointly performed. An attention mechanism-based deep convolutional neural network (CNN) is exploited as the backbone to learn embeddings for layout features and classify the hotspots simultaneously. The experimental results demonstrate that our framework achieves accuracy improvement over prior arts with fewer false alarms and faster inference speed on much more challenging benchmarks.

In this article, a novel asymptotic probability evaluation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing a large number of replicated cells. The key idea is to approximate the failure rate of the entire system by solving a set of nonlinear equations derived from a general analytical model. An error refinement method based on look-up table is further developed to improve numerical stability and, hence, reduce estimation error. Furthermore, a statistical algorithm based on resampling is developed to accurately estimate the confidence interval of APE. Our numerical experiments demonstrate that compared to the state-of-the-art method, APE can reduce the estimation error by up to$30\times $without increasing the computational cost.

While the VLSI community cares about designs with high yields under process variations, expensive computational costs make conventional yield optimization methods for analog circuits inefficient for industrial applications. In this article, an efficient yield optimization method via the freeze–thaw Bayesian optimization technique is proposed for analog circuits. The yield analysis is integrated into the exploration process of the Bayesian optimization. With a specified Gaussian process regression method, the flexible freeze–thaw Bayesian optimization technique is utilized to automatically guide the search in the design space and control the accuracy of yield analysis in the process space. A performance optimization problem is formulated and solved to mine prior knowledge, and a further speed up is achieved. Experimental results show that the proposed method can gain a$2.47\times $–$5.73\times $speedup compared with the state-of-the-art methods, without loss of accuracy.

Bayesian optimization is a promising methodology for analog circuit synthesis. However, the sequential nature of the Bayesian optimization framework significantly limits its ability to fully utilize real-world computational resources. In this article, we propose an efficient parallelizable Bayesian optimization algorithm via multiobjective acquisition function ensemble (MACE) to further accelerate the optimization procedure. By sampling query points from the Pareto front of the probability of improvement (PI), expected improvement (EI), and lower confidence bound (LCB), we combine the benefits of state-of-the-art acquisition functions to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem. Based on this batch design, we further adjust the algorithm for the constrained optimization problem. By dividing the optimization procedure into two stages and first focusing on finding an initial feasible point, we manage to gain more information about the valid region and can better avoid sampling around the infeasible area. After achieving the first feasible point, we favor the feasible region by adopting a specially designed penalization term to the acquisition function ensemble. The experimental results quantitatively demonstrate that our proposed algorithm can reduce the overall simulation time by up to$74\times $compared to differential evolution (DE) for the unconstrained optimization problem when the batch size is 15. For the constrained optimization problem, our proposed algorithm can speed up the optimization process by up to$15\times $compared to the weighted EI-based Bayesian optimization (WEIBO) approach, when the batch size is 15.

Knee osteoarthritis (OA) is a chronic disease that considerably reduces patients' quality of life. Preventive therapies require early detection and lifetime monitoring of OA progression. In the clinical environment, the severity of OA is classified by the Kellgren and Lawrence (KL) grading system, ranging from KL-0 to KL-4. Recently, deep learning methods were applied to OA severity assessment to improve accuracy and efficiency. However, this task is still challenging due to the ambiguity between adjacent grades, especially in early-stage OA. Low confident samples, which are less representative than the typical ones, undermine the training process. Targeting the uncertainty in the OA dataset, we propose a novel learning scheme that dynamically separates the data into two sets according to their reliability. Besides, we design a hybrid loss function to help CNN learn from the two sets accordingly. With the proposed approach, we emphasize the typical samples and control the impacts of low confident cases. Experiments are conducted in a five-fold manner on five-class task and early-stage OA task. Our method achieves a mean accuracy of 70.13% on the five-class OA assessment task, which outperforms all other state-of-art methods. Despite early-stage OA detection still benefiting from the human intervention of lesion region selection, our approach achieves superior performance on the KL-0 vs. KL-2 task. Moreover, we design an experiment to validate large-scale automatic data refining during training. The result verifies the ability to characterize low confidence samples. The dataset used in this paper was obtained from the Osteoarthritis Initiative.

Layout hotspot detection is of great importance in the physical verification flow. Deep neural network models have been applied to hotspot detection and achieved great success. Despite their success, high-performance neural networks are still quite difficult to design. In this article, we propose a bayesian optimization-based neural architecture search scheme to automatically do this time-consuming and fiddly job. Experimental results on ICCAD 2012 and ICCAD 2019 Contest benchmarks show that the architectures designed by our proposed scheme achieve higher performance on hotspot detection task compared with state-of-the-art manually designed neural networks.

In this paper, we propose an efficient parametric yield estimation method based on Bayesian Inference. By observing that nowadays analog and mixed-signal circuit is designed via a multi-stage flow, and that the circuit performance correlation of early stage and late stage is naturally symmetrical, we introduce a general region to capture the common features of the early and late stage. Meanwhile, two private regions are also incorporated to represent the unique features of these two stages respectively. Afterwards, we introduce classifiers one for each region to explicitly encode the correlation information. Next, we set up a graphical model, and consequently adopt Bayesian Inference to calculate the model parameters. Finally, based on the obtained optimal model parameters, we can accurately and efficiently estimate the parametric yield with a simple sampling method. Our numerical experiments demonstrate that compared to the state-of-the-art algorithms, our proposed method can better estimate the yield while significantly reducing the number of circuit simulations.

Bayesian optimization has been successfully introduced to analog circuit synthesis recently. Since the evaluations of performances are computational expensive, batch Bayesian optimization has been proposed to run simulations in parallel. However, circuit simulations may fail during the optimization, due to the improper design variables. In such cases, Bayesian optimization methods may have poor performance. In this paper, we propose a Robust Batch Bayesian Optimization approach (RBBO) for analog circuit synthesis. Local penalization (LP) is used to capture the local repulsion between query points in one batch. The diversity of the query points can thus be guaranteed. The failed points and their neighborhoods can also be excluded by LP. Moreover, we propose an Adaptive Local Penalization (ALP) strategy to adaptively scale the penalized areas to improve the convergence of our proposed RBBO method. The proposed approach is compared with the state-of-the-art algorithms with several practical analog circuits. The experimental results have demonstrated the efficiency and robustness of the proposed method.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. This paper proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving $8134 \times$ speedup on gradient calculation by backward propagation. Multi-modal starting points search is further applied in the framework to obtain satisfying filling quality optimums. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods.

Operational amplifier is a basic component for analog circuit design. The compensation network of an operational amplifier is crucial to improve the stability of the operational amplifier. In this paper, we present an automated compensation scheme design approach for operational amplifiers. We map the behavioral-level description of the operational amplifier to an acyclic graph and transfer the compensation design problem into a topology optimization problem. A feature mapping method is proposed to encode the graph and a bi-level Bayesian optimization approach is proposed to efficiently solve the topology optimization problem. Experimental results show that our proposed method can obtain competitive three-stage operational amplifiers compared to manual designs.

This paper firstly focuses on yield estimation problem on post-layout-simulation of high dimensional SRAM arrays. Post-layout-simulation is much more credible than pre-simulation. However, it introduces strong relationship among SRAM columns. The Multi-Fidelity Gaussian Process model between the small and the large SRAM arrays near Optimal Shift Vector (OSV) is built. An iterative strategy is proposed and Multi-Modal method is applied to obtain more prior knowledge of the small SRAM arrays and further accelerate convergence. Experimental results show that the proposed method can gain 5-7x speedup with less relative errors than the state-of-the-art method for 384D cases.

Due to advances in semiconductor processing technologies, wafer failure pattern detection plays a key role in preventing yield loss excursion events for semiconductor manufacturing. In the recent semiconductor industry, visible surface defects are still mainly being inspected manually, which may result in inevitably erroneous classification. Many machine learning techniques-based pioneered arts in academia have been proposed to aid wafer failure pattern classification. However, few of these attach importance to unlabeled information and alleviate the data imbalanced issue. Based on these concerns, this paper designs an end-to-end wafer defect classifier that unites the few-shot learning and self-supervised learning algorithms. The aim of applying the few-shot learning paradigm is to learn representations that generalize well to the minority defect pattern classes where only a few wafer images are available, while the self-supervision information containing the intrinsic correlations of unlabeled wafer maps and their augmentations is expected to enhance the few-shot learner. The experimental results demonstrate the proposed framework has superior performance compared to cutting-edge wafer defect classification methods.

In this paper, we propose a logic re-simulation method on GPU via gate/event parallelism and state compression. We achieve 2-dimensional parallelism on GPU through grouping gates and splitting events. Furthermore, we compress the states to reduce the communication overhead. Asynchronous communication between GPU and CPU is used to hide the latency of dumping results. Compared with the first place of problem C of ICCAD contest 2020, the proposed method can be 47.1 % better on the speedup of single design and 10.5% better on the geometric mean of speedup for all the benchmarks.

With the rapid development of semiconductors and the continuous scaling-down of circuit feature size, hotspot detection has become much more challenging and crucial as a critical step in the physical verification flow. In recent years, advanced deep learning techniques have spawned many frameworks for hotspot detection. However, most existing hotspot detectors can only detect defects arising in the central region of small clips, making the whole detection process time-consuming on large layouts. Some advanced hotspot detectors can detect multiple hotspots in a large area but need to propose potential defect regions, and a refinement step is required to locate the hotspot precisely. To simplify the procedure of multi-stage detectors, an end - to-end single-stage hotspot detector is proposed to identify hotspots on large scales without refining potential regions. Besides, multiple tasks are developed to learn various pattern topological features. Also, a feature aggregation module based on Transformer Encoder is designed to globally capture the relationship between different features, further enhancing the feature representation ability. Experimental results show that our proposed framework achieves higher accuracy over prior methods with faster inference speed.

In this paper, we propose an efficient Bayesian optimization approach for analog circuit synthesis based on the multi-task Gaussian process model. Instead of building the Gaussian process models separately for each circuit specification as the traditional Bayesian optimization methods do, we extend the Gaussian process to a vector-valued function with a shared covariance function to learn the dependencies between different specifications of circuits. The weighted expected improvement function is selected as the acquisition function to cope with the constraints. The experimental results show that the proposed method can reduce the number of simulations while achieving better optimization results.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing process in VLSI manufactures. The main challenge of dummy filling is balancing multiple objectives, such as fill amounts, planarity, parasitic capacitance, etc. An obvious drawback of traditional rule-based dummy filling methods is pattern densities, instead of post-chemical mechanical polishing (CMP) topographies, being included in optimization objectives. Although the quality of post-CMP topography strongly depends on pattern features of layouts, especially the density uniformity, however, experimental results show that chip surface variations are not exactly the same as density variations. In this article, a unified dummy fill insertion optimization framework is proposed, integrated with the multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver, where all objectives are considered without approximation. Inside this framework, a full-chip CMP simulator is first integrated to evaluate the planarity of the chip surface. By selecting the initial points smartly with heuristic prior knowledge, the proposed method can be effectively accelerated. The effectiveness of the proposed algorithm is verified with the average 25.8% improvement of quality compared with rule-based methods.

Layout hotspot detection is of great importance in the physical verification flow. Deep neural network models have been applied to hotspot detection and achieved great successes. The layouts can be viewed as binary images. The binarized neural network (BNN) can thus be suitable for the hotspot detection problem. In this article, we propose a new deep learning architecture based on BNNs to speed up the neural networks in hotspot detection. A new binarized residual neural network is carefully designed for hotspot detection. Experimental results on ICCAD 2012 and 2019 benchmarks show that our architecture outperforms previous hotspot detectors in detecting accuracy and has an 8× speedup over the best deep learning-based solution. Since the BNN-based model is quite computationally efficient, a good tradeoff can be achieved between the efficiency and performance of the hotspot detector by applying ensemble learning approaches. Experimental results show that the ensemble models achieve better hotspot detection performance than the original with acceptable speed loss.

As the technology node shrinks to the nanometer scale, process variation become one of the most important issues in IC designs. The industry calls for designs with high yield under process variations. Yield optimization is computationally intensive because traditionally it relies on the Monte-Carlo yield estimation. In this paper, we will first review the Bayesian methods that reduce the computational cost of yield estimation and optimization. By applying Bayes' theorem, maximizing the circuit yield is transformed to identify the design parameters with maximal probability density, conditioning on the event that the corresponding circuit is “pass”. It can thus avoid repetitive yield estimations during optimization. The computational cost can also be reduced by using the Bayesian optimization strategy. By using the Gaussian process surrogate model and adaptive yield estimation, Bayesian optimization can significantly reduce the number of simulations while achieving even comparable yields for analog and SRAM circuits. We further propose a Bayesian optimization approach for yield optimization via maxvalue entropy search in this paper. The proposed max-value entropy search can better explore the state space, and thus reduce the number of circuit simulations while achieving competitive results.

Due to time-consuming SPICE simulations and extremely low failure rates, yield optimization for large static random access memory (SRAM) circuits is still a challenging problem. In this paper, a novel robust yield optimization problem is firstly proposed for SRAM circuits, where robust means considering design and process parameter variations simultaneously. Both a multi-fidelity Gaussian process regression model, which utilizes the strong nonlinear relationship between small and large SRAM columns, and a Bayesian optimization framework are applied to guide the sampling of the expensive large SRAM circuits. A multimodal problem is formulated to find all peaks and valleys on the small SRAM circuits. Such precomputational knowledge can accelerate the convergence of the proposed multi-fidelity and Bayesian optimization framework. Experimental results show that robust yield is essential to yield optimization, for traditional optimal design will degenerate with 4-5 orders of magnitude of yields, if design variations considered, and it doesn't coincide with the new optimum under the robust yield. The proposed method can gain a 3~4× speedup compared to the state-of-the-art method without loss of accuracy.

In this paper, we propose EasyBO, an Efficient ASYn-chronous Batch Bayesian Optimization approach for analog circuit synthesis. In this proposed approach, instead of waiting for the slowest simulations in the batch to finish, we accelerate the optimization procedure by asynchronously issuing the next query points whenever there is an idle worker. We introduce a new acquisition function which can better explore the design space for asynchronous batch Bayesian optimization. A new strategy is proposed to better balance the exploration and exploitation and guarantee the diversity of the query points. And a penalization scheme is proposed to further avoid redundant queries during the asynchronous batch optimization. The efficiency of optimization can thus be further improved. Compared with the state-of-the-art batch Bayesian optimization algorithm, EasyBO achieves up to 7.35× speed-up without sacrificing the optimization results.

Bayesian optimization with Gaussian Process (GP) models has been proposed for analog synthesis since it is efficient for the optimizations of expensive black-box functions. However, the computational cost for training and prediction of Gaussian process models are O(N3) and O(N2), respectively, where N is the number of data points. The overhead of the Gaussian process modeling would not be negligible as N is relatively large. Recently, a Bayesian optimization approach using neural network has been proposed to address this problem. It reduces the computational cost of training and prediction of Gaussian process models to O(N) and O(1), respectively. However, reducing the infinite-dimensional kernel to finite-dimensional kernel using neural network mapping would weaken the characterization ability of Gaussian process. In this paper, we propose a novel Bayesian optimization approach using Sparse Pseudo-input Gaussian Process (SPGP). The idea is to use M <; N so-called inducing points to build a sparse Gaussian process model to approximate the conventional exact Gaussian process model. Without the need to sacrifice the modeling ability of the surrogate model, it also reduces the computational cost of both training and prediction to O(N) and O(1), respectively. Several experiments were provided to demonstrate the efficiency of the proposed approach.

With the aggressive and amazing scaling of the feature size of semiconductors, hotspot detection has become a crucial and challenging problem in the generation of optimized mask design for better printability. Machine learning techniques, especially deep learning, have attained notable success on hotspot detection tasks. However, most existing hotspot detectors suffer from suboptimal performance due to two-stage flow and less efficient representations of layout features. What is more, most works can only solve simple benchmarks with apparent hotspot patterns like ICCAD 2012 Contest benchmarks. In this paper, we firstly develop a new end-to-end hotspot detection flow where layout feature embedding and hotspot detection are jointly performed. An attention mechanism-based deep convolutional neural network is exploited as the backbone to learn embeddings for layout features and classify the hotspots simultaneously. Experimental results demonstrate that our framework achieves accuracy improvement over prior arts with fewer false alarms and faster inference speed on much more challenging benchmarks.

This paper presents an efficient memory partitioning algorithm for multi-pattern data access in Spintransfer torque random access memory (STT-RAM). The algorithm generates check patterns to solve read disturbance problem while ensuring multi-pattern data access in parallel. The implementation results imply that our proposed approach highly outperforms state-of-the-art algorithm in terms of bank number, searching time, performance and storage overhead.

Bayesian Optimization (BO) is an efficient method for black-box optimization problems. It has been successfully applied to the analog circuit sizing problem. However, all the design variables are viewed as continuous variables in these methods. Actually, many design variables are discrete due to the design rules. In this paper, we proposed an improved BO method for analog circuit sizing with both discrete and continuous variables. We also utilize the Gaussian Process (GP) regression model as the surrogate model for BO. However, we modified the kernel of GP and make it applicable to mixed variables. Experimental results demonstrated that the proposed mixed-variable BO method can significantly reduce the number of simulations with comparable optimization results, compared with the existing BO methods.

To efficiently estimate parametric yields over multiple process, voltage, temperature corners for binary output circuits, we propose a novel Bayesian Inference method based on Bernoulli distribution with conjugate prior in this paper. The key idea is to adopt a product of Beta distributions as the conjugate prior for the yields and encode circuit performance correlations among different corners into this prior. Next, the hyper-parameters are optimized by using multi-start Quasi-Newton method, and the yields over different corners are estimated via maximum-a-posteriori. Two circuit examples demonstrate that the proposed method achieves up to 3.0× cost reduction over the state-of-the-art methods without surrendering any accuracy.

Acceleration and wide deployability in deeper recurrent neural network is hindered by high demand for computation and memory storage on devices with memory and latency constraints. In this work, we propose a novel regularization method to learn hardware-friendly sparse structures for deep recurrent neural networks. Considering the consistency of dimension in continuous time units in recurrent neural networks, low-rank structured sparse approximations of the weight matrices are learned through the regularization without dimension distortion. Our method is architecture agnostic and can learn compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The structured sparsity rather than random sparsity also facilitates the hardware implementation. Experiments on language modeling of Penn TreeBank dataset show that our approach can reduce the parameters of stacked recurrent neural network model by over 90% with less than 1% perplexity loss. It is also successfully evaluated on larger highway neural network model with word2vec dataset like enwik8 and text8 using only 20M weights.

In this article, we propose an efficient correlated Bayesian inference (CBI) method to estimate the system-level failure rates for large-scale circuit systems over multiple process corners. The key idea is to encode the correlations of circuit performances among the different corners into the prior distributions of several carefully defined failure events. The hyper-parameters of these distributions can be learned from a few simulation samples via Bayesian inference and, next, the system-level failure rates over different corners can be simultaneously estimated by taking into account these prior distributions. An iteratively constrained inference method is further developed to guarantee the numerical stability of the proposed method and legalize all estimated failure rates. The numerical experiments demonstrate that compared to the state-of-the-art algorithm, the proposed method can achieve around 10× runtime reduction without surrendering any accuracy.

Parametric yield estimation over multiple process corners plays an important role in robust circuit design. In this article, we propose a novel Bayesian inference method based on Bernoulli distribution (BI-BD) to efficiently estimate the multicorner yields for binary output circuit. The key idea is to encode the circuit performance correlation among different corners as our prior knowledge. Consequently, after combining a few simulation samples, the yield estimation over all corners can be calibrated via Bayesian inference based on iterative reweighted least squares (IRLS) and expectation maximization (EM). A circuit example demonstrates that the proposed BI-BD method can achieve up to 2.0 × cost reduction over the conventional Monte Carlo method without surrendering any accuracy.

In this article, a novel asymptotic probability approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient hierarchical subset simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimate the overall failure rate of correlated rare failure events involving more than 20 000 independent random variables.

Discrete Cosine Transform (DCT) is a commonly used building block for image and video compression. In this article, we present a Markov Random Field (MRF)-based design for DCT implementation because MRF logic gates outperform standard non-MRF units by achieving high noise immunity for applications to logic-based computing systems in deep sub-micron condition. Furthermore, it is found that stochastic logic, a low-cost form of number representation, can also efficiently simplify computations. By combining these two techniques, we present an improved DCT hardware circuit. The example eight-point one-dimensional DCT (1D DCT) system is simulated using 65 nm CMOS technology. Simulation results show that the proposed MRF design can achieve 13% higher noise immunity and 47% area saving, compared with the typical stochastic 1D DCT using classical Master-and-Slave architecture. While achieving the same error rate of 0.21, power consumption is reduced by 52%.

Tunable analog/RF circuit has emerged as a promising technique to address the significant performance uncertainties caused by process variations. To optimize these tunable circuits after fabrication, most existing post-silicon programming methods are developed by using real-valued performance metrics. However, when measuring a performance of interest on silicon, it is often substantially more expensive to obtain a real-valued measurement than a binary testing outcome (i.e., pass or fail). In this article, we propose a Gaussian Process Classification model to capture the binary performance metrics of tunable analog/RF circuits. Based on these models, post-silicon programming is cast into an optimization problem that can be solved by a novel Bayesian optimization algorithm. Moreover, measurement noises are further incorporated into our proposed post-silicon programming to produce a robust circuit. Two circuit examples demonstrate that the proposed approach can efficiently program tunable circuits with binary performance metrics while other conventional methods are not applicable.

As the circuit feature size continuously shrinks down, hotspot detection has become a more challenging problem in modern DFM flows. Developed deep learning techniques have recently shown their advantages on hotspot detection tasks. However, existing hotspot detectors only accept small layout clips as input with potential defects occurring at a center region of each clip, which will be time consuming and waste lots of computational resources when dealing with large full-chip layouts. In this paper, we develop a new end-to-end framework that can detect multiple hotspots in a large region at a time and promise a better hotspot detection performance. We design a joint auto-encoder and inception module for efficient feature extraction. A two-stage classification and regression flow is proposed to efficiently locate hotspot regions roughly and conduct final prediction with better accuracy and false alarm penalty. Experimental results show that our framework enables a significant speed improvement over existing methods with higher accuracy and fewer false alarms.

Layout hotspot detection is of great importance in the physical verification flow. Deep neural network models have been applied to hotspot detection and achieved great successes. The layouts can be viewed as binary images. The binarized neural network can thus be suitable for the hotspot detection problem. In this paper we propose a new deep learning architecture based on binarized neural networks (BNNs) to speed up the neural networks in hotspot detection. A new binarized residual neural network is carefully designed for hotspot detection. Experimental results on ICCAD 2012 Contest benchmarks show that our architecture outperforms all previous hotspot detectors in detecting accuracy and has an 8x speedup over the best deep learning-based solution.

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect.

The floating random walk (FRW) algorithm is an important method widely used in the capacitance extraction of very large-scale integration (VLSI) interconnects. FRW could be both time-consuming and power-consuming as the circuit scale grows. However, its highly parallel nature prompts us to accelerate it with FPGAs, which have shown great performance and energy efficiency potential to other computing architectures. In this paper, we propose a scalable FPGA/CPU heterogeneous framework of FRW using SDAccel. Large-scale circuits are partitioned first by the CPU into several segments, and these segments are then sent to the FPGA random walking one by one. The framework solves the challenge of limited FPGA on-chip resource and integrates both merits of FPGAs and CPUs by targeting separate parts of the algorithm to suitable architecture, and the FPGA bitstream is built once for all. Several kernel optimization strategies are used to maximize performance of FPGAs. Besides, the FRW algorithm we use is the naive version with walking on spheres (WOS), which is much simpler and easier to implement than the complicatedly optimized version with walking on cubes (WOC). The implementation on AWS EC2 F1 (Xilinx VU9P FPGA) shows up to 6.1x performance and 42.6x energy efficiency over a quad-core CPU, and 5.2x energy efficiency over the state-of-the-art WOC implementation on an 8-core CPU.

Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N3), and the computation complexity of prediction is O(N2), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits.

In this paper, we propose an efficient performance trade-off modeling method for analog circuit based on Bayesian Neural Network (BNN). First, we use a single BNN to simultaneously model multiple performances of interest (PoIs) of an analog circuit. This BNN model can be trained by using a novel automatic differential variational inference (ADVI) method with affordable computational cost. Next, the performance trade-off model can be extracted by embedding BNN into Bayesian optimization framework combined with a modified multi-objective evolutionary method. Since the correlations among different PoIs are implicitly encoded in the BNN model, the proposed method can capture the performance trade-off model efficiently and accurately. The numerical experiments demonstrate that compared to the state-of-the-art algorithms, the proposed method can achieve up to 2× runtime reduction without surrendering any accuracy.

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work.

Memory bandwidth has become a bottleneck that impedes performance improvement during the parallelism optimization of the datapath. Memory partitioning is a practical approach to reduce bank-level conflicts and increase the bandwidth on a field-programmable gate array. In this work, we propose a memory partitioning approach for multi-pattern data access. First, we propose to combine multiple patterns into a single pattern to reduce the complexity of multi-pattern. Then, we propose to perform data reuse analysis on the combined pattern to find data reuse opportunities and the non-reusable data pattern. Finally, an efficient bank mapping algorithm with low complexity and low overhead is proposed to find the optimal memory partitioning solution. Experimental results demonstrated that compared to the state-of-the-art method, our proposed approach can reduce the number of block RAMS by 58.9% on average, with 79.6% reduction in SLICEs, 85.3% reduction in LUTs, 67.9% in reduction Flip-Flops, 54.6% reduction in DSP48Es, 83.9% reduction in SRLs, 50.0% reduction in storage overhead, 95.0% reduction in execution time, and 77.3% reduction in dynamic power consumption on average. Meanwhile, the performance can be improved by 14.0% on average.

Compressive sensing (CS) is a novel signal processing technology to reconstruct the sparse signal at sub-Nyquist rate. Orthogonal matching pursuit (OMP) is one of the most widely used signal reconstruction algorithms. However, the least square problem (LSP) in OMP algorithm limits its performance. This paper presents a fast CS reconstruction algorithm implemented on field-programmable gate array (FPGA) using OMP. The proposed algorithm adopts an incremental QR decomposition (QRD) method to efficiently solve the LSP. The incremental QRD is further optimized to eliminate the square root operation to facilitate hardware implementation. The proposed architecture avoiding the complex square root unit mainly consists of some more basic computing units, where the computing process is broken down into several simple operations to map to the corresponding hardware for pipelining. The proposed implementation based on Xilinx Kintex-7 FPGA exploits the parallelism by a well-planned workload schedule and reaches an optimal tradeoff between the latency and frequency. The experimental results demonstrate that the proposed architecture can run at a frequency of 210 MHz with a reconstruction time of 238 μs for 36-sparse 1024-length signal, which improves the signal reconstruction speed by 1.43× compared to the state-of-the-art implementations.

In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event-multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.

In this paper, a novel multi-objective Bayesian optimization method is proposed for the sizing of analog/RF circuits. The proposed approach follows the framework of Bayesian optimization to balance the exploitation and exploration. Gaussian processes (GP) are used as the online surrogate models for the multiple objective functions. The lower confidence bound (LCB) functions are taken as the acquisition functions to select the data point with best Pareto-dominance and diversity. A modified non-dominated sorting based evolutionary multi-objective algorithm is proposed to find the Pareto Front (PF) of the multiple LCB functions, and the next simulation point is chosen from the PF of the multiple LCB functions. Compared with the multi-objective evolutionary algorithms (MOEA) and the state-of-the-art online surrogate model based circuit optimization method, our method can better approximate the Pareto Front while significantly reduce the number of circuit simulations.

In this paper, we develop a general pessimism reduction framework for design optimization of timing closure. Although the modified graph based timing analysis (mGBA) slack model can be readily formulated into a quadratic programming problem with constraints, the realistic difficulty is the size of the problem. A critical path selection scheme, a uniform sampling method with the sparse characteristics of the optimal solution, and a stochastic conjugate gradient method are proposed to accelerate the optimization solver. This modified GBA is embedded into design optimization of timing closure. Experimental results show that the proposed solver can achieve 13.82x speedup than gradient descent method with similar accuracy. With mGBA, the optimization of timing closure can achieve a better performance on area, leakage power, buffer counts.

Memory partitioning has been widely adopted to increase the memory bandwidth. Data reuse is a hardware-efficient way to improve data access throughput by exploiting locality in memory access patterns. We found that for many applications in image and video processing, a global data reuse scheme can be shared by multiple patterns. In this paper, we propose an efficient data reuse strategy for multi-pattern data access. Firstly, a heuristic algorithm is proposed to extract the reuse information as well as find the non-reusable data elements of each pattern. Then the non-reusable elements are partitioned into several memory banks by an efficient memory partitioning algorithm. Moreover, the reuse information is utilized to generate the global data reuse logic shared by the multi-pattern. We design a novel algorithm to minimize the number of registers required by the data reuse logic. Experimental results show that compared with the state-of-the-art approach, our proposed method can reduce the number of required BRAMs by 62.2% on average, with the average reduction of 82.1% in SLICE, 87.1% in LUTs, 71.6% in Flip-Flops, 73.1% in DSP48Es, 83.8% in SRLs, 46.7% in storage overhead, 79.1% in dynamic power consumption, and 82.6% in execution time of memory partitioning. Besides, the performance is improved by 14.4%.

Bayesian optimization methods are promising for the optimization of black-box functions that are expensive to evaluate. In this paper, a novel batch Bayesian optimization approach is proposed. The parallelization is realized via a multi-objective ensemble of multiple acquisition functions. In each iteration, the multi-objective optimization of the multiple acquisition functions is performed to search for the Pareto front of the acquisition functions. The batch of inputs are then selected from the Pareto front. The Pareto front represents the best trade-off between the multiple acquisition functions. Such a policy for batch Bayesian optimization can significantly improve the efficiency of optimization. The proposed method is compared with several state-of-the-art batch Bayesian optimization algorithms using analytical benchmark functions and real-world analog integrated circuits. The experimental results show that the proposed method is competitive compared with the state-of-the-art algorithms.

In this paper, a Bayesian optimization approach is proposed for yield optimization of analog and SRAM circuits. Gaussian process (GP) regression is employed to predict the yield over the design space with uncertainty information. An expected improvement acquisition function is constructed over the model and guides the optimization with a utility-based strategy. These techniques, as a whole, can significantly reduce the number of expensive yield estimations during the optimization procedure. Furthermore, the GP model encodes the observation uncertainties of noise-corrupted objectives, which enables an adaptive control over yield estimations. By ensuring high estimation accuracies for promising designs while tolerating higher variabilities for low-yield ones, the proposed method can significantly cut down the average computational cost of yield estimations without surrendering the accuracy of the final result. Experimental results show that, compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations without compromising optimization efficacy.

Automated analog circuit design is promising for increasing the design productivity and narrowing the time-tomarket, but is facing the bottleneck of tremendous design complexity. In this paper, a simulation-based optimization approach named smart-multiple starting point (MSP) is proposed for analog circuit synthesis. The proposed smart-MSP is based on the framework of MSP optimization, which is shown to be much more efficient than other global optimization methods like simulated annealing, genetic algorithm, particle swarm optimization, etc. Efficient techniques including heuristic-biased starting point selection, sparse regression and probabilistic TABU are developed in smart-MSP and make the algorithm quite smart in a way that the overall optimization process is self-adaptive by learning from the previous local searches and can efficiently produce optimal results to approximate the global optimum. Experiments have demonstrated that the proposed smart-MSP is 2.6-12.5× faster than the original MSP method, and is 1.3-2100× faster than other state-of-the-art methods.

Interlayer liquid cooling network has been considered as one of the effective cooling mechanisms for heat dissipation in three dimensional integrated circuits (3D ICs). In this paper, an optimization approach is proposed for 3D IC interlayer cooling network design with consideration of cooling energy minimization and thermal constraints. First, a channel patterning technique is proposed which adopts straight-channel patterns and corner-barrier patterns to efficiently reduce the temperature of hotspots in the chip. Second, an iterative channel pruning process is proposed for cooling network optimization that reduces the temperature gradient and cooling energy. Furthermore, algebraic multigrid-preconditioned generalized conjugate residual solver is applied for thermal simulation in this optimization process to achieve better computational efficiency. Experimental results have shown that the proposed optimization approach can produce optimal interlayer cooling networks with 11.3%-61.3% cooling energy savings and 49.3%-59.4% pumping pressure savings in comparison with the first place winner of 2015 computer-aided design contest at International Conference on Computer-Aided Design.

Yield 1 analysis of SRAM is a challenging issue, because the failure rates of SRAM cells are extremely small. In this article, an efficient non-Gaussian sampling method of cross entropy optimization is proposed for estimating the high sigma SRAM yield. Instead of sampling with the Gaussian distribution in existing methods, a non-Gaussian distribution, i.e., a joint one-dimensional generalized Pareto distribution and ( n -1)-dimensional Gaussian distribution, is taken as the function family of practical distribution, which is proved to be more suitable to fit the ideal distribution in the view of extreme failure event. To minimize the cross entropy between practical and ideal distributions, a sequential quadratic programing solver with multiple starting points strategy is applied for calculating the optimal parameters of practical distributions. Experimental results show that the proposed non-Gaussian sampling is a 2.2--4.1× speedup over the Gaussian sampling, on the whole, it is about a 1.6--2.3× speedup over state-of-the-art methods with low- and high-dimensional cases without loss of accuracy

Character projection is a promising technique to dramatically improve throughput of E-beam lithography. However, its effectiveness depends on how good the stencils are planned and optimized. Recently Kuang and Young proposed an efficient heuristic based on 2-D bin-packing for the stencil optimization. In this paper, we identified drawbacks in their approaches, and developed a better algorithm that reduces the shot numbers to less than half of theirs in average. The key point is introducing the merit frequency/area (f/A) to select candidate characters and proposing an accurate and efficient algorithm to estimate the occupied area of characters before placement. Experimental results verify the effectiveness of the proposed method.

End Cutting 1D layout design is a promising candidate for sub-10nm process nodes. Given a 1D layout with horizontal wires, cut redistribution technique is used for sliding the line-end cuts in order to align them vertically or resolve spacing conflicts. The aligned cuts can then be merged into a single shot of cuts. In this paper, we proposed a network flow based method for efficient cut redistribution and insertion. Normally, a pair of movable cuts could have three possible relations, left-of, right-of and merge-into. We observe that if the left-right-merge orderings of cuts are fixed, the cut redistribution can be formulated as a network flow problem, which can be solved efficiently. We also find that inserting cuts can resolve the spacing conflicts in some circumstances. This cut insertion strategy is introduced in our proposed method to reduce the spacing conflicts. Moreover, the complementary e-beam lithography for printing the cuts is also considered in this paper. Experimental results show that compared with a previous ILP-based method, our method can achieve a 200X speedup and competitive solution quality.

In this paper, a novel Asymptotic Probability Estimation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing a large number of replicated cells. The key idea is to approximate the failure rate of the entire system by solving a set of nonlinear equations derived from a general analytical model. An error refinement method based on Look-up Table (LUT) is further developed to improve numerical stability and, hence, reduce estimation error. Our numerical experiments demonstrate that compared to the state-of-the-art method, APE can reduce the estimation error by up to 45x without increasing the computational cost.

Conventional yield optimization approaches rely on accurate yield estimation for given design parameters, which would be computational intensive. In this paper, a novel Bayesian yield optimization approach is proposed for analog and SRAM circuits. An equivalent a problem is formulated via applying Bayes' theorem on the augmented yield problem. The yield optimization problem is converted to identifying the design parameters with maximal probability density conditioning on the event that the corresponding circuit is "pass". Gaussian kernel density estimation is employed to approximate the conditional probability, and a multi-start-point based EM-like algorithm is proposed to solve the equivalent problem efficiently Compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations with comparable optimization accuracy by avoiding repetitive yield estimations.

Starting from a set of starting points, the multiple-starting-point optimization searches the local optimums by gradient-guided local search. The global optimum is selected from these local optimums. The region-hit property of the multiple-starting-point optimization makes the multiple-starting-point approach more likely to reach the global optimum. However, for non-smooth objective functions, e.g., worst-case optimization, the traditional gradient based local search methods may stuck at non-smooth points, even if the objective function is smooth “almost everywhere”. In this paper, we propose a subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. Subgradients instead of traditional gradients are used to guide the local search of the non-smooth optimization. The Shor's R algorithm is used to accelerate the subgradient based local search. A two-stage optimization strategy is proposed to deal with the constraints in analog circuit optimization. Our experiments on 2 circuits show that the proposed method is very efficient for worst-case optimization. The proposed approach can achieve much better solutions with less simulations, compared with the traditional gradient based method, smoothing approximation method, smooth relaxation method and differential evolution algorithms.

Thermal control has become a great challenge for 3D-ICs due to the ever increasing power density and 3D integration. Among techniques to address the problem, fast thermal simulation approach is basically required to accurately characterize the runtime temperature variations of 3D-ICs. In this paper, we propose an accurate and fast leakage-aware thermal simulation approach for 3D-ICs with consideration of both heatsink cooling and microfluidic cooling. First, the proposed approach is based on a corrected linearized model for leakage power approximation, which is proved to be equivalent to the Newton-Chord method for solving nonlinear algebra equations. A convergence comparison is presented in this paper to show that such approach is more efficient than other methods for leakage-aware thermal simulation. Second, an aggregation-based algebraic multigrid (AMG) preconditioned iterative linear solver is adopted that greatly reduces the computation time for solving the linear equations during calculation, which makes the proposed approach even more efficient. Numerical experiments show that the proposed approach can achieve 8x-139x speedup in comparison with the state-of-the-art methods, and with almost negligible average temperature error no more than 0.025K and maximum temperature error no more than 0.095K.

We describe a novel methodology to validate vision-based autonomous driving systems over different circuit corners with consideration of temperature variation and circuit aging. The proposed work is motivated by the fact that low-level circuit implementation may have a significant impact on system performance, even though such effects have not been appropriately taken into account today. Our approach seamlessly integrates the image data recorded under nominal conditions with comprehensive statistical circuit models to synthetically generate the critical corner cases for which an autonomous driving system is likely to fail. As such, a given automotive system can be robustly validated for these worst-case scenarios that cannot be easily captured by physical experiments.

An efficient SVM-based hotspot detection method using spectral clustering is proposed in this paper. Firstly, we build graphs to represent both training patterns and test layouts. With spectral clustering, the training patterns and test layouts are adaptively decomposed into a set of small critical patterns. The small critical patterns from the training data sets are used to build the SVM models. The SVM models are then employed to check the decomposed features from the test layouts for hotspot detection. Compared with existing SVM-based hotspot detection methods, the proposed method can achieve higher accuracy with comparable number of false alarms and significant speedup.

The printability problem of chip making becomes challenging in advanced process nodes. At present, various lithography technologies such as multiple patterning (MP), directed self-assembly (DSA), electron beam (e-beam), and their combinations are being considered. In this paper, the corresponding layout decomposition problems for contact/via generation are studied. In particular, we investigate the simultaneous DSA template and e-beam throughput optimization. First, we present an exact method based on an ILP formulation. Then, a graph-based algorithm is developed. The co-optimization problem for DSA double patterning with e-beam is formulated as a minimum hitting set problem. A primal-dual based algorithm is then derived for solving the problem effectively. Experimental results show that compared with a two-stage method, our method can achieve around 20.6% throughput improvement and 18.7% template cost reduction.

End cutting 1D layout process is a promising candidate for sub-10nm process nodes. To be correctly manufactured, any pair of end cuts must be either merged/aligned or apart from each other with at least a minimum distance. This constraint adversely affects the manufacturability, especially when the end cuts have to be solely printed with the conventional lithography technology. To improve the manufacturability, recent works start to consider the constraint in early stages, such as physical design. In this paper, we propose a heuristic grid-based detailed routing algorithm for the end cutting 1D layout process. One important issue of the routing algorithm is how to represent the routing resources, especially for the end cuts. In the proposed algorithm, this issue is addressed by maintaining a directed routing graph. On the routing graph, new end cuts are initially located by a regular shortest path algorithm. Since the routing resources are correctly represented with the routing graph, the new end cuts are not in conflict with the existing end cuts. To further resolve the conflicts among the new end cuts, each segment of the wire is sequentially legalized. Experimental results indicate that compared with an intuitive two-stage method, the proposed algorithm can achieve higher solution quality with much less runtime.

Spectral graph sparsification aims to find an ultra-sparsified matrix which can be used as a good preconditioner for the original matrix. Low-stretch spanning tree could be constructed for this purpose. The relative condition number with the low-stretch spanning tree is bounded, which ensures the convergence of the PCG method with low-stretch spanning tree as preconditioner. Recently, spectral perturbation analysis is proposed to add a group of spectral critical edges to the spanning tree. The relative condition number can thus be further reduced. In this paper, we proposed a Krylov-subspace based spectral perturbation analysis to find the spectral critical edges. Compared with the traditional power-iteration-based approach, our proposed method can significantly improve the convergence of spectral perturbation analysis and thus accelerate the procedure of constructing the ultra-sparsified preconditioner.

As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.

Parallelizing the memory accesses in a nested loop is a critical challenge to facilitate loop pipelining. An effective approach for high-level synthesis on field-programmable gate array is to map these accesses to multiple on-chip memory banks using a memory partitioning technique. In this paper, we propose an efficient memory partitioning algorithm with low overhead and low time complexity for parallel data access via data reuse. We find that for most applications in image and video processing, a large amount of data can be reused among different iterations of a loop nest. Motivated by this observation, we propose to cache reusable data using on-chip registers, organized as register chains. The nonreusable data are then separated into several memory banks by a memory partitioning algorithm. We revise the existing padding method to cover cases occurring frequently in our method wherein certain components of partition vector are zeros. Experimental results have demonstrated that compared with the state-of-the-art algorithms, the proposed method is efficient in terms of execution time, resource overhead, and power consumption across a wide range of access patterns extracted from applications in image and video processing. As for the testing patterns, the execution time is typically less than one millisecond. And the number of required memory banks is reduced by 59.7% on average, which leads to an average reduction of 78.2% in look-up tables, 65.5% in flip-flops, 37.1% in DSP48Es, and therefore 74.8% reduction in dynamic power consumption. Moreover, the storage overhead incurred by the proposed method is zero for most widely used access patterns in image filtering.

A distance metric of patterns is crucial to hotspot cluster analysis and classification. In this paper, we propose an improved tangent space (ITS)-based distance metric for hotspot cluster analysis and classification. The proposed distance metric is an important extension of the well-developed tangent space method in computer vision. It can handle patterns containing multiple polygons, while the traditional tangent space method can only deal with patterns with a single polygon. It inherits most of the advantages of the traditional tangent space method, e.g., it is easy to compute and is tolerant with small variations or shifts of the shapes. The ITS-based distance metric is a more reliable and accurate metric for hotspot cluster analysis and classification. We also propose a hierarchical density-based clustering method for hotspot clustering. It is more suitable for arbitrary shaped clusters.

Parametric yield estimation is a critical task for design and validation of analog and mixed-signal (AMS) circuits. However, the computational cost for yield estimation based on Monte Carlo (MC) analysis is often prohibitively high, especially when multiple circuit performances and/or environmental corners (e.g., voltage and temperature corners) are considered. In this paper, a novel statistical method named correlation-aided yield estimation (C-YES) is proposed to reduce the computational cost for parametric yield estimation. Our proposed approach exploits the fact that multiple circuit performances over different environmental corners are often correlated. Hence, we can accurately predict the performance value at one corner from the simulation results for other performances and/or corners. Based upon this observation, instead of running a large number of MC simulations to cover all performances and corners, an efficient algorithm is developed to select a small set of the most “informative” simulations that should be performed for yield estimation. Our numerical experiments show that for parametric yield estimation with multiple circuit performances and environmental corners, C-YES achieves 6.5-9.3× runtime speedups over other conventional methods.

Random region covering is a global optimization technique that explores the landscape by introducing multiple random starting points to initiate the local optimization solvers. This study applies the random region covering technique to circuit design automation and proposes a theory to explain why this technique is efficient at searching for the global optimum. In addition to analyzing the efficiency of the random region covering algorithm, the theory gives a probability-based estimation of the goodness of the optimization result. To enhance the efficiency of the random region covering technique, this work evaluates the boundary of top performance regions and proposes a modified random region covering method that only performs the global optimization on the top design region. The results from a large number of mathematical experiments verify the proposed methodology. The optimized designs of a class-E power amplifier and a wide load range operational amplifier outperform both manual designs and other state-of-the-art optimization techniques.

Directed self-assembly (DSA) complemented with multiple patterning (MP) is an attractive next generation lithography (NGL) technique for contact-hole generation. Nevertheless, a high-quality DSA-aware layout decomposer is required to enable the technology. In this article, we introduce an efficient method which incorporates a set packing for generating DSA template candidates and a local search method. Besides, a multi-start strategy is integrated into the framework to prevent the local minima. Our framework encourages the reuse of existing coloring solvers. Hence, the development cost can significantly be reduced. In addition, for DSA multiple patterning where the number of masks is larger than two, we present an efficient iterative partition based method. Experimental results show that compared with the state-of-the-art work, our methods can achieve roughly 100× speedup for double patterning, and 78.8% conflict reduction with 5× speedup for triple patterning on the dense graphs.

The failure rate of static RAM (SRAM) cells is restricted to be extremely low to ensure sufficient high yield for the entire chip. In addition, multiple performances of interest and influences from peripherals make SRAM failure rate estimation a high-dimensional multiple-failure-region problem. This paper proposes a new method featuring a multistart-point sequential quadratic programming (SQP) framework to extend minimized norm importance sampling (IS) to address this problem. Failure regions in the variation space are first found by the low-discrepancy sampling sequence. Afterward, start points are generated in all identified failure regions and local optimizations based on SQP are invoked from these start points searching for the optimal shift vectors (OSVs). Based on the OSVs, a Gaussian mixture distorted distribution is constructed for IS. To further reduce the computational cost of IS while fully considering the influence of increasing dimensionality, an adaptive model training framework is proposed to keep high efficiency for both low- and high-dimensional problems. The experimental results show that the proposed method can not only approximate failure rate with high accuracy and efficiency in low-dimensional cases but also keep these features in high-dimensional ones.

Trajectory-based methods offer an effective methodology for generating the reduced-order models (ROMs) for nonlinear systems. These methods first sample on the state trajectories driven by the training inputs, then linearize and reduce the linearized systems around the sample points. However, these methods depend on an single global reduction subspace generated by combining all the projection subspaces of the sample points on the trajectories. In order to address this problem, a localized reduction technique has been proposed. This method weaves together a larger set of smaller localized ROMs for the trajectory samples. However, since these localized ROMs do not share the same coordinates, these localized ROMs cannot be interpolated to derive new ROMs. As a result, a large number of localized ROMs are needed to cover the necessary state space and guarantee adequate reduction accuracy. In this paper, we propose a new, efficient trajectory-based model order reduction algorithm for nonlinear systems via localized projection and global interpolation. We employ an efficient procedure to transform the smaller localized ROMs into a set of equivalent ROMs with nearly consistent global coordinate. The ROMs for the nonlinear systems are then obtained by globally interpolating the localized ROMs. Because we can perform interpolation between these localized ROMs, the required number of localized ROMs can be greatly reduced.

With the aggressive scaling of integrated circuit technology, analog performance modeling is facing enormous challenges due to high-dimensional variation space and expensive transistor-level simulation. In this paper, we propose a kernel density based sparse regression algorithm (KDSR) to accurately fit analog performance models where the modeling error is not simply Gaussian due to strong nonlinearity. The key idea of KDSR is to approximate the non-Gaussian likelihood function by using non-parametric kernel density estimation. Furthermore, we adopt Laplace distribution as our prior knowledge to enforce a sparse pattern for model coefficients. The unknown model coefficients are finally determined by using an EM type algorithm for maximum-a-posteriori (MAP) estimation. Our proposed method can be viewed as an iterative and weighted sparse regression algorithm that aims to reduce the estimation bias for model coefficients due to outliers. Our experimental results demonstrate that our proposed KDSR method can achieve superior accuracy over the conventional sparse regression method.

In this paper, we propose a novel Dual-Prior Bayesian Model Fusion (DP-BMF) algorithm for performance modeling. Different from the previous BMF methods which use only one source of prior knowledge, DP-BMF takes advantage of multiple sources of prior knowledge to fully exploit the available information and, hence, further reduce the modeling cost. Based on a graphical model, an efficient Bayesian inference is developed to fuse two different prior models and combine the prior information with a small number of training samples to achieve high modeling accuracy. Several circuit examples demonstrate that the proposed method can achieve up to 1.83× cost reduction over the traditional one-prior BMF method without surrendering any accuracy.

In this paper, we propose an efficient memory partitioning algorithm for parallel data access via data reuse. We found that for most of the applications in image and video processing, a large amount of data can be reused among different iterations in a loop nest. Motivated by this observation, we propose to cache these reusable data by on-chip registers. The on-chip registers used to cache the re-fetched data can be organized as chains of registers. The non-reusable data are then partitioned into several memory banks by a memory partition algorithm. We revise the existing padding method to cover cases occurring frequently in our method that some components of partition vector are zeros. Experimental results have demonstrated that compared with the state-of-the-art algorithms the proposed method can reduce the required number of memory banks by 59.8% on average. The corresponding resources for bank mapping is also significantly reduced. The number of LUTs is reduced by 78.6%. The number of Flip-Flops is reduced by 66.8%. The number of DSP48Es is reduced by 41.7%. Moreover, the storage overheads of the proposed method are zeros for most of the widely used access patterns in image filtering.

Dummy fill insertion is widely applied to significantly improve the planarity of topographic patterns for chemical mechanical polishing process in VLSI manufacture. However, these dummies will lead to additional parasitic capacitance and deteriorate the circuit performance. The main challenge of dummy filling algorithms is how to balance multiple objectives, such as fill amount, density variation, parasitic capacitance, etc. which is the aim of ICCAD 2014 DFM contest. Traditional dummy fill insertion methods are no longer applicable because they generate large amount of fills or take unaffordable time. In this paper, we propose a unified dummy fill insertion optimization framework based on multi-starting points and sequential quadratic programming optimization solver, where all objectives are considered simultaneously without approximation. Selecting the initial points smartly with prior knowledge, the proposed method can be effectively accelerated. Even without any prior knowledge, it can also reach high fill quality by random initial points with high scalability. The proposed algorithm is verified by ICCAD 2014 DFM contest benchmark, which shows better quality of dummy filling over the state-of-the-art algorithms.

In this paper, a novel Asymptotic Probability Approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient Hierarchal Subset Simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimates the overall failure rate of correlated rare failure events involving more than 20,000 independent random variables.

This paper presents a fast compressive sensing reconstruction algorithm implemented on FPGA using Orthogonal Matching Pursuit (OMP). The algorithm is optimized with QR decomposition to solve the least square problem and avoids the square root operations to facilitate the hardware implementation. The implementation results show that this design can run at a frequency of 100MHz and the proposed algorithm achieves 50% lower complexity than the other existed algorithms.

High-speed I/O link plays an important role in modern computer systems. In order to accurately estimate a small BER value in the order of 10-12, a large number of bits need to be transmitted, which results in expensive testing cost. In this paper, we exploit the correlation between the performance of high-speed I/O link under different corners/configurations to improve the accuracy of the estimated BER. A graphical generative model is used to represent the underlying correlations. This template provides a way to share information between different models, hence increases the modeling accuracy. Experimental results show that our method achieves up to 2x speed-up over the traditional method.

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost.

In this paper, we propose a novel spatial variation modeling method based on hidden Markov tree (HMT) for nanoscale integrated circuits, which could efficiently improve the accuracy of full-wafer/chip spatial variations recovery at extremely low measurement cost. Applying this method, HMT is introduced to set up a statistical model for coefficients after exploring the underlying correlated representation of the spatial variation in the frequency domain. Accordingly, two key inherent properties of the modeling coefficients, i.e., correlations and sparse presentations in the frequency domain, can be captured exactly and the modeling accuracy can be improved evidently. Then, maximum-a-posteriori estimation is applied to formulate the original problem as a convex optimization that could be solved efficiently and robustly. Numerical results based on industrial data demonstrate that the proposed method can achieve superior accuracy over other existing approaches including orthogonal matching pursuit, l1-norm regularization, and reweighted l1-norm regularization.

Efficiently optimizing large-scale, complex analog systems requires to know the performance tradeoffs for various analog circuit blocks. In this paper, we propose a radically new approach for analog performance tradeoff modeling. Our key idea is to broadly search the rich design knowledge from the Internet, and then mathematically encode the knowledge as high-dimensional performance tradeoff curves that are referred to as Pareto fronts in the literature. Toward this goal, several novel numerical algorithms, such as sparse regression and semi-infinite programming, are developed in order to construct the high-dimensional Pareto front model while guaranteeing its monotonicity. Our numerical examples demonstrate that the proposed modeling technique can accurately capture the high-dimensional Pareto fronts for large-scale analog systems (e.g., analog-to-digital converter) while most traditional methods are limited to low-dimensional Pareto front modeling of small circuit blocks without considering layout parasitics and manufacturing nonidealities.

As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and electron-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion${K}$-partition problem, where${K}$is the number of masks in multiple patterning. Stitch minimization and EBL throughput are considered uniformly by adding a virtual vertex between two feature vertices for each stitch candidate during the conflict graph construction phase. For${K} {=} 2$, we propose a primal-dual (PD) method for solving the underlying minimum odd-cycle cover problem efficiently. In addition, a chain decomposition algorithm is employed for removing all “noncyclable” edges. Furthermore, we investigate two versions of the PD method, one with planarization and one without. For${K} {>} 2$, we propose a random-initialized local search method that iteratively applies the PD solver. Experimental results show that compared with a two-stage method, our proposed methods reduce the EBL usage by 65.5% with double patterning and 38.7% with triple patterning on average for the benchmarks.

In this paper, we propose a post-layout waveform prediction method by System Identification (SI) based on the fact that the waveforms of pre-layout and post-layout are always correlated. Mathematical models are built to describe the relationships between the pre-layout and post-layout simulation results via SI techniques. The model parameters are calibrated by using the simulation results of the first few data points of pre-layout and post-layout stages. By taking the corresponding pre-layout simulation results as inputs of the calibrated models, the rest post-layout waveforms can thus be predicted as the output of the models. Several examples demonstrate the efficiency of the prediction, which helps the designers have a quick view of the post-layout waveforms in the design process.

As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and e-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion K-partition problem, where K is the number of masks in multiple patterning. Stitch minimization and EBL throughput are considered uniformly by adding a virtual vertex between two feature vertices for each stitch candidate during the conflict graph construction phase. For K = 2, we propose a primal-dual method for solving the underlying minimum odd-cycle cover problem efficiently. In addition, a chain decomposition algorithm is employed for removing all “non-cyclable” edges. For K > 2, we propose a random-initialized local search method that iteratively applies the primal-dual solver. Experimental results show that compared with a two-stage method, our proposed methods reduce the EBL usage by 64.4% with double patterning and 38.7% with triple patterning on average for the benchmarks.

Machine learning (ML) and pattern matching (PM) are powerful computer science techniques which can derive knowledge from big data, and provide prediction and matching. Since nanometer VLSI design and manufacturing have extremely high complexity and gigantic data, there has been a surge recently in applying and adapting machine learning and pattern matching techniques in VLSI physical design (including physical verification), e.g., lithography hotspot detection and data/pattern-driven physical design, as ML and PM can raise the level of abstraction from detailed physics-based simulations and provide reasonably good quality-of-result. In this paper, we will discuss key techniques and recent results of machine learning and pattern matching, with their applications in physical design.

Simulation of power girds has become increasingly computationally expensive. In this paper, we propose a Model Order Reduction (MOR) method for power grid circuits by extending the existing Aggregation-based MOR (AMOR) method. In the proposed method, besides resistors and capacitors, current sources are also aggregated to improve MOR efficiency. Moreover, pre-partition and parallelization techniques are employed to decrease the reduction time. Numerical results demonstrate that the reduced-order models can achieve up to 18× simulation speed-up over the original circuits without much loss of accuracy.

A critical-yet-challenging problem of analog/mixed-signal circuit validation in either pre-silicon or post-silicon stage is to estimate the parametric yield of the performances. In this paper, we propose a novel Bayesian model fusion method for efficient multivariate moment estimation of multiple correlated performance metrics by borrowing the prior knowledge from the early stage. The key idea is to model the multiple performance metrics as a jointly Gaussian distribution and encode the prior knowledge as a normal-Wishart distribution according to the theory of conjugate prior. The late-stage multivariate moments can be accurately estimated by Bayesian inference with very few late-stage samples. Several circuit examples demonstrate that the proposed method can achieve up to 16× cost reduction over the traditional method without surrendering any accuracy.

In this paper, we propose an efficient oscillation-diminishing cubic Hermite spline interpolation method for the table-based transistor model approximation. We use the cubic Hermite spline interpolation to ensure the continuity of the derivatives. Oscillation-diminishing techniques are proposed to reduce the oscillations (bumps) of interpolations such that both convergence and accuracy are significantly improved. Further, the oscillation-diminishing schemes do not rely on any real derivatives. Therefore, the proposed method can be used to build table models from measured data of the physical devices, where the real derivatives are not always available. In the proposed method, an adaptive approach is employed to generate the nonuniform interpolation grids such that the interpolation accuracy is guaranteed and the memory requirement is minimized. We also propose a novel combined exponential extrapolation method for off-state (leakage) current, which exactly follows the exponential-decay characteristic of that current. Test simulations on several classic industrial analog and mixed-signal circuits show that the proposed method can achieve high accuracy with lower computational cost compared with existing table-based model approximation methods.

Transient analysis of large-scale power delivery network (PDN) is a critical task to ensure the functional correctness and desired performance of today's integrated circuits (ICs), especially if significant transient noises are induced by clock and/or power gating due to the utilization of extensive power management. In this paper, we propose an efficient algorithm for PDN transient analysis based on sparse approximation. The key idea is to exploit the fact that the transient response caused by clock/power gating is often localized and the voltages at many other “inactive” nodes are almost unchanged, thereby rendering a unique sparse structure. By taking advantage of the underlying sparsity of the solution structure, a modified conjugate gradient algorithm is developed and tuned to efficiently solve the PDN analysis problem with low computational cost. Our numerical experiments based on standard benchmarks demonstrate that the proposed transient analysis with sparse approximation offers up to 2.2× runtime speedup over other traditional methods, while simultaneously achieving similar accuracy.

In this article we present a pairwise coloring (PWC) approach to tackle the layout decomposition problem for triple patterning lithography (TPL). The main idea is to reduce the problem to a set of bi-coloring problems. The overall solution is refined by applying a bi-coloring method for pairs of color sets per pass. One obvious advantage of this method is that the existing double patterning lithography (DPL) techniques can be reused effortlessly. Moreover, we observe that each pass can be fulfilled efficiently by integrating an SPQR-tree-graph-division-based bi-coloring method. In addition, to prevent the solution getting stuck in the local minima, an adaptive multi-start (AMS) approach is incorporated. Adaptive starting points are generated according to the vote of previous solutions. The experimental results show that our method is competitive with other works on both solution quality and runtime performance.

Optimization-simulation loop-based method is popular and efficient in design migration/reuse automation. However, it is only restricted to be used in block-level due to the complexity of current mixed-signal system. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topologies. It utilizes two stages of optimization processes to automatically resize and refine device dimensions in target technology. In the first stage, to avoid the costly simulation time without scarifying systematical functionality, only one block is represented in transistor level (TL), while other blocks are replaced with behavioral models. The multistart global optimization technique is applied to resize the TL block in systematic connection. This stage provides a good initial point for next system-level refinement. Moreover, for obtaining a process and parasitic closure solution, both parasitic and process variation effects are explored and used to constrain the schematic migration. A representative mixed-signal system, charge-pump phase-locked loop, is used to validate the proposed methodology. The experimental results show that the proposed methodology efficiently generates quality designs in target technology with much less simulation iterations, when comparing with recent available approaches.

Accurate yield estimation is one of the important yet challenging tasks for both pre-silicon verification and post-silicon validation. In this paper, we propose a novel method of Bayesian model fusion on Bernoulli distribution (BMF-BD) for efficient yield estimation at the late stage by borrowing the prior knowledge from an early stage. BMF-BD is particularly developed to handle the cases where the pre-silicon simulation and/or post-silicon measurement results are binary: either "pass" or "fail". The key idea is to model the binary simulation/measurement outcome as a Bernoulli distribution and then encode the prior knowledge as a Beta distribution based on the theory of conjugate prior. As such, the late-stage yield can be accurately estimated through Bayesian inference with very few late-stage samples. Several circuit examples demonstrate that BMF-BD achieves up to 10× cost reduction over the conventional estimator without surrendering any accuracy.

As the interconnect delay is becoming a larger fraction of the clock cycle time, the conventional global stalling mechanism, which is used to correct error in general synchronous circuits, would be no longer feasible because of the expensive timing cost for the stalling signal to travel across the circuit. In this paper, we propose recovery-based resilient latency-insensitive systems (RLISs) that efficiently integrate error-recovery techniques with latency-insensitive design to replace the global stalling. We first demonstrate a baseline RLIS as the motivation of our work that uses additional output buffer which guarantees that only correct data can enter the output channel. However this baseline RLIS suffers from performance degradations even when errors do not occur. We propose a novel improved RLIS that allows erroneous data to propagate in the system. Equipped with improved queues that prevent accumulation of erroneous data, the improved RLIS retains the system performance. We provide theoretical study that analyzes the impact of errors on system performance and the queue sizing problem. We also theoretically prove that the improved RLIS performs no worse than the global stalling mechanism. Experimental results show that the improved RLIS has 40.3% and even 3.1% throughput improvements compared to the baseline RLIS and the infeasible global stalling mechanism respectively, with less than 10% hardware overhead.

Through-silicon via (TSV) with flip-chip packaging is a technology that enables vertical integration of silicon dies, forming a single 3-D IC stack. A practical model for preplaced TSV assignment of 3-D nets is proposed for this technology. We prove that the general preplaced 3-D IC TSV assignment problem with more than two dies is NP-complete. An integrated algorithm that combines shortest path search, bipartite matching, min-cost max-flow calculation, and postprocessing is developed. Experimental results using actual testing silicon data demonstrate that our flow achieves good results with reasonable runtime when compared to other existing works.

While double patterning lithography (DPL) is still in active development, triple or even quadruple patterning has recently been proposed for the next technology node. In this paper, we propose a pairwise coloring (PWC) method to tackle the layout decomposition problem for general multiple patterning lithography (MPL). The main idea is to reduce the problem to sets of concurrent bi-coloring problems. The overall solution is refined iteratively by applying a bi-coloring method for pairs of color sets per pass. One obvious advantage of this approach is that the existing DPL techniques can be reused seamlessly. Any improvement of them can directly benefit to the MPL counterpart. Moreover, we observe that with the help of the SPQR-tree graph division method, each pass can be fulfilled in nearly linear time. In addition, to prevent the solution getting stuck in the local minima, a randomized initialization strategy is incorporated. The PWC method is executed certain number of times with different randomized initial solutions, out of which the best solution is selected as output. We have implemented our method for particular triple patterning lithography (TPL). The experimental results show that compared with two recently published methods for TPL, our method can reduce the number of conflicts up to 33.2% and 44.9% respectively.

SystemC, as a C++-based hardware description language, is used for system architecture design, large digital hardware, software, and their interaction. Its extension, SystemC-AMS, provides the capability of abstract modeling to deliver analog system-level simulation of “real-time” application scenarios. SystemC and SystemC-AMS help designers to analyze a whole mixed-signal system and further guide the circuit design to reduce the design cost. This paper presents SystemC (2.2.0) and SystemC-AMS (1.0 Beta2) modeling of a near-field communication (NFC) system working in passive mode, based on the proximity contactless identification cards ISO/IEC 14443 international standard. The NFC transceiver system includes reader and card analog blocks, digital blocks, and antennas. Problems caused by realistic imperfections are considered, simulated, and then solved by modifying the design at a system level, which is significant to high-level modeling. Systematic simulation is given to prove SystemC/SystemC-AMS is an accurate and efficient tool to model a heterogeneous mixed-signal system in an early-design stage.

A distance metric of patterns is crucial to hotspot cluster analysis and classification. In this paper, we propose an improved tangent space based metric for pattern matching based hotspot cluster analysis and classification. The proposed distance metric is an important extension of the well-developed tangent space method in computer vision. It can handle patterns containing multiple polygons, while the traditional tangent space method can only deal with patterns with a single polygon. It inherits most of the advantages of the traditional tangent space method, e.g., it is easy to compute and is tolerant with small variations or shifts of the shapes. Compared with the existing distance metric based on XOR of hotspot patterns, the improved tangent space based distance metric can achieve up to 37.5% accuracy improvement with at most 4.3x computational cost in the context of cluster analysis. The improved tangent space based distance metric is a more reliable and accurate metric for hotspot cluster analysis and classification. It is more suitable for industry applications.

In this paper, we propose an efficient Aggregating based Model Order Reduction method (AMOR) for many-terminal interconnect circuits. The proposed AMOR method is based on the observation that those adjacent nodes of interconnect circuits with almost the same voltage can be aggregated together as a "super node". Motivated by such an idea, we propose an efficient spectral partition algorithm in AMOR method to partition the nodes into groups with almost the same voltages. The reduced-order models are then obtained by aggregating the adjacent nodes within the same groups together as "super nodes" in AMOR method. The efficiency of AMOR method is not limited by the numbers of the terminals of the networks. Moreover, noticing that the aggregating procedure can be regarded as mapping the original problem into a coarse-grid problem in multigrid method, we propose a computation-efficient smoothing procedure to further improve the simulation accuracy of the reduced-order models. With such a strategy, the simulation accuracy of the reduced-order models can always be guaranteed. Numerical results have demonstrated that, without the smoothing procedure, the reduced-order models obtained by AMOR can still achieve higher simulation efficiency in terms of accuracy and CPU time than the reduced-order models obtained by the existing elimination based methods. With the smoothing procedure, the simulation accuracy of the reduced-order models can further be improved with several iterations.

Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for sequential circuit under clock scheduling. The sequential MSV assignment problem is first formulated as a convex cost dual network flow problem, which can be optimally solved in polynomial time assuming delay of each gate can be chosen in continuous domain. Then a mincut-based heuristic is designed to convert the unfeasible continuous solution into feasible discrete solution while largely preserving the global optimality. Besides, we revisit the hardness of the general discrete voltage assignment problem and point out some misunderstandings on the approximability of this problem in previous related work. Benchmark test for our algorithm shows 9.2% reduction in power consumption on average, in compared with combinational MSV assignment. Referring to the continuous solution obtained from network flow as the lower bound, the gap between our solution and the lower bound is only 1.77%.

Double patterning lithography, where one-layer layout is decomposed into two masks, is believed to be inevitable for 32nm technology node of the ITRS roadmap. However, post-routing layer assignment, which decides the layout pattern on each layer, thus having great impact on double patterning related parameters, has not been explored in the merit of double patterning. In this paper, we propose a post-routing layer assignment algorithm for double patterning optimization. Our solution consists of three major phases: multi-layer assignment, single-layer double patterning, and via reduction. For phase one and three, multi-layer graph is constructed and dynamic programming is employed to solve optimization problem on this graph. In the second phase, single-layer double patterning is proved NP-hard and existing algorithm is implemented to optimize single layer double patterning problem. The proposed method is tested on CBL (Collaborative Benchmarking Laboratory) benchmarks and shows great performance. In comparison with single-layer double patterning, our method achieves 73% and 27% average reduction for unresolvable conflicts and stitches respectively, with only 9% increase of via number. When double patterning is constrained on only the bottom two metal layers as in current technology, these numbers become 62%, 8% and 0.42%.

Integrated circuit (IC) design automation has traditionally followed a hierarchical approach. Modern IC design flow is divided into sequentially-addressed design and optimization layers; each successively finer in design detail and data granularity while increasing in computational complexity. Eventual agreement across the design layers signals design closure. Obtaining design closure is a continual problem, as lack of awareness and interaction between layers often results in multiple design flow iterations. In this work, we propose parallel cross-layer optimization, in which the boundaries between design layers are broken, allowing for a more informed and efficient exploration of the design space. We leverage the heterogeneous parallel computational power in current and upcoming multi-core/many-core computation platforms to suite the heterogeneous characteristics of multiple design layers. Specifically, we unify the highlevel and physical synthesis design layers for parallel cross-layer IC design optimization. In addition, we introduce a massively-parallel GPU floorplanner with local and global convergence test as the proposed physical synthesis design layer. Our results show average performance gains of 11X speed-up over state-of-the-art.

Clock skew scheduling is an effective technique in performance optimization of sequential circuits. However, with process variations, it becomes more difficult to reliably implement a wide spectrum of clock delays at the registers. Multidomain clock skew scheduling is a good option to overcome this limitation. In this paper, we propose a practical method to efficiently and optimally solve this problem. A framework based on branch-and-bound is carefully designed to search for the optimal clocking domain assignment, and a greedy clustering algorithm is developed to quickly estimate the upper bound of cycle period for a given branch. Experiment results on ISCAS89 sequential benchmarks show both the optimality and efficiency of our method compared with previous works.

Through-Silicon Via (TSV) is a technology that enables vertical integration of silicon dies forming a single 3D-IC stack. In this paper, a practical model is proposed for the TSV assignment problem of the stacked-die 3D nets. We present the first work in the literature to prove that the general 3D-IC TSV assignment problem with more than two dies is NP-complete. An efficient heuristic algorithm that combines Shortest Path, Bipartite Matching, Min-cost Max-flow and Integer Linear Programming is developed. Experimental results demonstrate that our flow achieves good quality of results (within 98% of the optimal solution) with reasonable run-time compared to related works.

Conventional clock skew scheduling for sequential circuits can be formulated as a minimum cycle ratio (MCR) problem, and hence can be solved effectively by methods such as Howard's algorithm. However, its application is practically limited due to the difficulties in reliably implementing a large set of arbitrary dedicated clock delays for the flip-flops. Multi-domain clock skew scheduling was proposed to tackle this impracticality by constraining the total number of clock delays. Even though this problem can be formulated as a mixed integer linear programming (MILP), it is expensive to solve optimally in general. In this paper, we show that, under mild restrictions, the underlying domain assignment problem can be formulated as a special MILP that can be solved effectively using similar techniques for the MCR problem. In particular, we design a generalized Howard's algorithm for solving this problem efficiently. We also develop a critical-cycle-oriented refinement algorithm to further improve the results. The experimental results on ISCAS89 benchmarks show both the accuracy and efficiency of our algorithm. For example, only 4.3% of the tests have larger than 1% degradation (3% in the worst case), and all the tests finish in less than 0.7 seconds on a laptop with a 2.1GHz processor.

A correlation-first bisection method is proposed for analyzing the robust stability distribution of linear analog circuits in the multi-parameter space. This new method first transfers the complex multi-parameter robust stability problem into nonlinear inequalities by the Routh criterion, and then solves them by interval arithmetic and new bisection strategy. The axis with strong relationship to the functions dominating the stability is bisected. Furthermore, the Monte Carlo method is adopted for the uncertain subdomains to increase the convergence speed of bisection methods as the cube number increases. The proposed method has no error in both stable and unstable areas, and high efficiency to determine the complex boundaries between the stable and unstable areas. Numerical results validate this new method.

To reduce chip-scale topography variation in chemical mechanical polishing process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the density-driven dummy fill problem as a standard linear program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. Furthermore, dummy fill can also change the interconnect coupling capacitance which might lead to a significant influence on circuit delay, crosstalk, and power consumption. In this paper, we develop a dummy fill algorithm that can be applied to solve both the traditional density-driven problem and the problem considering fill-induced coupling capacitance impact. The proposed algorithm is both efficient and with provably good performance, which is based on a fully polynomial time approximation scheme by Fleischer for covering LP problems. Moreover, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte Carlo based heuristic methods. Final experimental results demonstrate the effectiveness and efficiency of our algorithms.

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the profit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into four sub-problems. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based statistical static timing analysis (SSTA) approach is developed which is based on the generalized stochastic collocation method with the sparse grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy method is proposed to maximize profit considering both the sales revenue and the test cost by iteratively assigning each boundary to its optimal position. Third, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order to minimize the test cost, based on alphabetic tree. Last, a simple approach is presented to decide the optimal number of bins, which helps to complete the whole binning scheme with maximal profit. Experiments on all the ISCAS'89 sequential benchmarks with 65 nm technology show 10.68% profit improvement in average. Some comparisons with other methods suggest the advantage of our method. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.

This paper presents NanoHeat, a multi-resolution full-chip dynamic integrated circuit (IC) thermal analysis solution, that is accurate down to the scale of individual gates and transistors. NanoHeat unifies nanoscale and macroscale dynamic thermal physics models, for accurate characterization of heat transport from the gate and transistor level up to the chip-package level. A non-homogeneous Arnoldi-based analysis method is proposed for accurate and fast dynamic thermal analysis through a unified adaptive spatial-temporal refinement process. NanoHeat is capable of covering the complete spatial and temporal modeling spectrum of IC thermal analysis. The accuracy and efficiency of NanoHeat are evaluated, and NanoHeat has been applied to a large industry design. The importance of considering fine-grain temperature information is illustrated by using NanoHeat to estimate temperature-dependent negative-bias-temperature-instability (NBTI) effects. NanoHeat has been implemented and publicly released for free academic and personal use.

This paper describes a solution for global routing and track assignment of flip-chip I/O nets. Voronoi Diagram (VD) is used to partition the open routing space and the geometrical properties of VD graph are exploited to create global routing channels with capacity and congestion considerations. A network flow algorithm is used to achieve optimal global routing. The regularity of the flip-chip bump placement is observed and allows us to reduce the size of global routing channel graph by over 50% to speed up computation. A track assignment algorithm avoids crossing wires before completing the final route with a detailed router. Experiment results using actual silicon chip data demonstrate that our solution achieves good quality of results compared to an implementation used in a commercial tool.

Trajectory piecewise-linear macromodeling (TPWL) technique has been widely employed to characterize strong nonlinear circuits, and makes the reduction of the strong nonlinear circuits possible. The trajectory piecewise-linear macromodeling technique linearizes nonlinear circuits around multiple expansion points which are extracted from state trajectories driven by training inputs. However, the accuracy of the trajectory piecewise-linear macromodeling technique heavily relies on the extracted expansion points and the training inputs. It will lead to large error in simulation if state vector reaches regions far away from the extracted expansion points. In this paper, we propose an efficient transistor-level piecewise linearization scheme for macromodeling of nonlinear circuits. Piecewise linear models are first built for each transistor. The macromodel of the whole nonlinear circuit is then constructed by combining all the piecewise-linear models of the transistors together with appropriate weight functions. The proposed approach can cover remarkably larger state space than the TPWL method. By using the complete piecewise-linear models of the transistors, the constructed piecewise-linear models of the nonlinear circuits are capable of covering the whole state space of the nonlinear circuits. More importantly, model order reduction of the proposed transistor-level piecewise linearization macromodel is also possible, which makes the proposed method a potentially good macromodeling approach for model order reduction of nonlinear circuits.

Computational complexity has been the primary challenge of many very large scale integration computer-aided design (CAD) applications. The emerging multicore and many-core microprocessors have the potential to offer scalable performance improvements. How to explore the multicore resources to speed up CAD applications is thus a natural question but also a huge challenge for CAD researchers. This paper proposes a methodology to explore concurrency via nondeterministic transactional models, and to program them on multicore processors for CAD applications. Various run-time scheduling implementations on multicore shared-memory machines are discussed and the most efficient one is identified. The proposed methodology is applied to the min-cost flow problem which has been identified as the key problem in many design optimizations, from wire-length optimization in detailed placement to timing-constrained voltage assignment. A concurrent algorithm for min-cost flow has been developed based on the methodology. Experiments on voltage island generation in floorplanning have demonstrated its efficiency and scalable speedup over different numbers of cores.

In this paper, we present a novel statistical analysis approach for large power grid network analysis under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called varETBR for variational extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. varETBR calculates variational response Gramians by Monte-Carlo based numerical integration considering both system and input source variations for generating the projection subspace. varETBR is very scalable for the number of variables and is flexible for different variational distributions and ranges as demonstrated in experimental results. After the reduction, Monte-Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. Experimental results, on a number of IBM benchmark circuits [15] up to 1.6 million nodes, show that the varETBR can be 4500X faster than the Monte-Carlo method and is much more scalable than one of the recently proposed approaches.

Abstract—To reduce chip-scale topography variation in Chemical Me-chanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the dummy fill problem as a standard Linear Program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. In this paper, we develop a dummy fill algorithm that is both efficient and with provably good performance. It is based on a fully polynomial time approximation scheme by Fleischer [4] for covering LP problems. Furthermore, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte-Carlo based heuristic methods. Experimental results demonstrate the effectiveness and efficiency of our algorithms.

Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliability. Various aging effects, such as negative bias temperature instability, cause continuous performance and reliability degradation during circuit run-time usage. In this work, we present a statistical analysis framework that characterizes the lifetime reliability of nanometer-scale integrated circuits by jointly considering the impact of fabrication-induced process variation and run-time aging effects. More specifically, our work focuses on characterizing circuit threshold voltage lifetime variation and its impact on circuit timing due to process variation and the negative bias temperature instability effect, a primary aging effect in nanometer-scale integrated circuits. The proposed work is capable of characterizing the overall circuit lifetime reliability, as well as efficiently quantifying the vulnerabilities of individual circuit elements. This analysis framework has been carefully validated and integrated into an iterative design flow for circuit lifetime reliability analysis and optimization.

Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and many-core microprocessors have the potential to offer scalable performance improvement. How to explore the multicore resources to speed up CAD applications is thus a natural question but also a huge challenge for CAD researchers. Indeed, decades of work on general-purpose compilation approaches that automatically extracts parallelism from a sequential program has shown limited success. Past work has shown that programming model and algorithm design methods have a great influence on usable parallelism. In this paper, we propose a methodology to explore concurrency via nondeterministic transactional algorithm design, and to program them on multicore processors for CAD applications. We apply the proposed methodology to the min-cost flow problem which has been identified as the key problem in many design optimizations, from wire-length optimization in detailed placement to timing-constrained voltage assignment. A concurrent algorithm and its implementation on multicore processors for min-cost flow have been developed based on the methodology. Experiments on voltage island generation in floorplanning demonstrated its efficiency and scalable speedup over different number of cores.

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.

A novel circuit simulation methodology, incremental circuit SPICE analysis, is presented with the foundational circuit simulation algorithm. When a circuit in design is modified from one version to another, only the change in the circuit is simulated and analyzed. The approach is well applied into design process for circuit parametric modification and functionality verification. By reusing simulation result from successive version, the algorithm reduces the duplicated operations in simulation. The examples show the new approach increases simulation speed about 10 times over the traditional method.

In nanometer technologies, process variations possess growing nonlinear impacts on circuit performance, which causes critical path delays of combinatorial circuits variate randomly with non-Gaussian distribution. In this paper, we propose a novel clock skew scheduling methodology that optimizes timing yield by handling non-Gaussian distributions of critical path delays. Firstly a general formulation of the optimization problem is proposed, which covers most of the previous formulations and indicates their limitations with statistical interpretations. Then a generalized minimum balancing algorithm is proposed for effectively solving the skew scheduling problem. Experimental results show that the proposed method significantly outperforms some representative methods previously proposed for yield optimization, and could obtain timing yield improvements up to 33.6% and averagely 17.7%.

This paper presents a multiparameter moment-matching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process (TAP). It is referred to as a Parameterized Interconnect Macromodeling via a TAP (PIMTAP) algorithm. PIMTAP inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive. PIMTAP model yields the same form of the original state equations and preserves the passivity of parameterized RLC networks like the well-known method passive reduced-order interconnect macromodeling algorithm for nonparameterized RLC networks.

Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines the ellipsoid method and affine arithmetic. Affine arithmetic is not only used for keeping tracks of variations and correlations, but also helps to determine the sub-gradient at each iteration of the ellipsoid method. An example of designing a CMOS operational amplifier is given to demonstrate the effectiveness of the proposed method. Finally numerical results are verified by SPICE simulation.

In this paper, stochastic collocation algorithm combined with sparse grid technique (SSCA) is proposed to deal with the periodic steady-state analysis for nonlinear systems with process variations. Compared to the existing approaches, SSCA has several considerable merits. Firstly, compared with the moment-matching parameterized model order reduction (PMOR), which equally treats the circuit response on process variables and frequency parameter by Taylor approximation, SSCA employs homogeneous chaos to capture the impact of process variations with exponential convergence rate and adopts Fourier series or wavelet bases to model the steady-state behavior in time domain. Secondly, contrary to stochastic Galerkin algorithm (SGA), which is efficient for stochastic linear system analysis, the complexity of SSCA is much smaller than that of SGA for nonlinear case. Thirdly, different from efficient collocation method, the heuristic approach which may results in "rank deficient problem" and "Runge phenomenon", sparse grid technique is developed to select the collocation points in SSCA in order to reduce the complexity while guaranteing the approximation accuracy. Furthermore, though SSCA is proposed for the stochastic nonlinear steady-state analysis, it can be applied for any other kinds of nonlinear system simulation with process variations, such as transient analysis, etc.

The increasing effort on full-chip validation constrains design cost and time-to-market. A waveform comparison tool named WCOMP is presented to automate mixed-signal validation regression in memory design. Unlike digital waveform comparison tools, WCOMP compares mixed-signal waveforms for functional match instead of graphical match, which tally with the requirements of full-chip validation regression. Simulations with different regression runs, process parameters, voltages and temperatures can be functionally compared. The methods are proved to be effective in Intelreg Flash memory design.

This paper presents a multiparameter moment- matching based model order reduction technique for parameter- ized interconnect networks via a novel two-directional Arnoldi process. It is referred to as a PIMTAP algorithm, which stands for Parameterized Interconnect Macromodeling algorithm via a Two-directional Arnoldi Process. PIMTAP inherits the advan- tages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive, and preserves the passivity of parameterized RLC networks.

This paper aims to explore RLC equivalent circuit synthesis method for reduced-order models of interconnect circuits obtained by Krylov subspace based model order reduction (MOR) methods. To guarantee pure RLC equivalent circuits can be synthesized for the reduced-order models, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. Block structure preserving MOR methods such as SPRIM (Freund, 2004) and SAPOR (Su et al., 2004) have been well established. In this paper, an embeddable input-output structure preserving order reduction (IOPOR) technique was proposed to further preserve the structures of input and output incidence matrices in the reduced-order models. By combining block structure preserving MOR methods and IOPOR technique, an RLC equivalent circuit synthesis method RLCSYN (RLC SYNthesis) was developed. Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make RLCSYN more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.

A novel algorithm UDMDA for parametric yield optimization of IC is proposed in this paper. The algorithm integrates uniform design (UD) and mapping distance. An effective yet simple measurement of uniformity of a set of points, namely k-nearest neighbor, is suggested in the UD. Compared with the available methods, the proposed algorithm does not need any calculation of gradient and assumption of initial point. Furthermore, this algorithm has a high convergence rate and is not sensitive to the size of circuit. Therefore, it can be utilized to optimize the nominal performance as well as improve parametric yield. The efficiency of this algorithm is illustrated with two circuit examples

In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reduction approach can achieve smaller reduced order circuits with very high accuracy, especially for those circuits with strong singularities. Furthermore, to compute the basis function coefficient vectors, a fast Sylvester equation solver is proposed, which works more than one or two orders faster than the vector equation solver employed by Chebyshev reduction method. The proposed wavelet method is also compared with the frequency domain model reduction method, which may loose accuracy in time domain. Both theoretical analysis and experiment results have demonstrated the high speed and high accuracy of the proposed method.

With the development of IC technology, it becomes urgent to investigate model reduction method for interconnects with process variations. In this paper, a one-shot projection algorithm (OPM) is proposed to generate a projection matrix that is independent of statistically varying parameters. As a result, construction of the reduced system can be decoupled with the Monte Carlo analysis in either frequency domain or time domain. Therefore, without loss of accuracy, OPM can obtain a reduced system in much less CPU time compared with the previous perturbation scheme. Numerical results have demonstrated the advantages of the proposed OPM

Recently model order reduction techniques for second-order systems have obtained many research interests for the simulation of RCS interconnect circuits employing susceptance elements. In this paper, we propose a Block SAPOR (Block Second-order Arnoldi method for Passive Order Reduction) for Multi-Input Multi-Output RCS Circuits. The proposed Block SAPOR algorithm can simultaneously guarantee passivity and achieve higher accuracy than the first order reduction technique PRIMA. Most importantly, the reduced system matrices obtained by the proposed method can preserve the structure of the original system matrices. Such a nice property makes it possible to construct an equivalent RCS circuit for the reduced system.

In this paper, a novel wavelet method is proposed for noise analysis of nonlinear circuits. Compared with the existing algorithms capable of accessing circuit performance in the present of noise, the proposed method presents several merits. First, it fully accounts for nonlinearities. Second, it can handle signals with continuous frequency spectra. Third, by taking advantage of the properties of the wavelet bases, such as local compactness and multi-resolution, it holds high simulation speed and high accuracy. Furthermore, an adaptive scheme exists to automatically select the wavelet basis functions for a desired accuracy. All these merits make the novel wavelet method outperforms its previous techniques.

This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipation with optimal delay constraints or with a given delay penalty. We derive optimal solutions for both cases. These solutions can be used to efficiently estimate the power dissipation for long single wires in the interconnect designs.

The variational analysis has been employed in for order reduction of weakly nonlinear systems. For a relatively strong nonlinear system, this method will mostly lose efficiency because of the exponentially increased number of inputs in higher order variational equations caused by the individual reduction process of the variational systems. Moreover, the inexact inputs into the higher order variational equations indispensably introduce extra errors in the order reduction process. Inspired by the variational analysis, we propose a direct model order reduction method. The order of the approximate polynomial system of the original nonlinear system is directly reduced by one project space. The proposed direct reduction technique can easily avoid the errors brought by inexact inputs and the exponentially increased inputs. We show theoretically and experimentally that the proposed method can achieve much more accurate reduced system with smaller order size than the conventional variational equation order reduction method.

In this paper, we propose a novel time-domain based method, discrete singular convolution algorithm, for computing steady-state response in nonlinear circuit. Properties and advantages of discrete singular convolution method are discussed, compared with some other approaches. The accuracy and efficiency of this method are tested by the numerical experiments.

The recently-introduced susceptance element exhibits many prominent features in modeling the on-chip magnetic couplings. For an RCS circuit, it is better to be formulated as a second-order system. Therefore, corresponding MOR (model-order reduction) techniques for second-order systems are desired to efficiently deal with the ever-increasing circuit scale and to preserve essential model properties. We first review the existing MOR methods for RCS circuits, such as ENOR and SMOR, and discuss several key issues related to numerical stability and accuracy of the methods. Then, a technique, SAPOR (second-order Arnoldi method for passive order reduction), is proposed to effectively address these issues. Based on an implementation of a generalized second-order Arnoldi method, SAPOR is numerically stable and efficient. Meanwhile, the reduced-order system also guarantees passivity.

In this paper, we develop a wavelet collocation method with nonlinear companding for behavioral modeling of analog circuits. To construct the behavioral models, the circuit is first partitioned into building blocks and the input-output function of each block is then approximated by wavelets. As the blocks are mathematically represented by sets of simple wavelet basis functions, the computation cost for the behavioral simulation is significantly reduced. The proposed method presents several merits compared with those conventional techniques. First, the algorithm for expanding input-output functions by wavelets is a general-purpose approach, which can be applied in automatically modeling of different analog circuit blocks with different structures. Second, both the small signal effect and the large signal effect are modeled in a unified formulation, which eases the process of modeling and simulation. Third, a nonlinear companding method is developed to control the modeling error distribution, To demonstrate the promising features of the proposed method, a 4th order switched-current filter is employed to build the behavioral model.

Control of parasitic capacitance and minimization of layout mismatch are very crucial in the analog physical design automation. In this paper we study the techniques for modeling the distributed parasitic capacitance, modeling the parasitic parameter mismatch due to process gradient and modeling the inner stack routing mismatch. Based on the proposed models, a transistor folding technique and a dummy transistor insertion technique are developed to optimize the stack shape, control of parasitics and guarantee the generation of an Eulerian graph for a given diffusion graph.

Article Buffer insertion for clock delay and skew minimization Share on Authors: X. Zeng Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC and Department of Electronic Engineering, Fudan University, Shanghai 200433, China Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC and Department of Electronic Engineering, Fudan University, Shanghai 200433, ChinaView Profile , D. Zhou Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NCView Profile , Wei Li Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NCView Profile Authors Info & Claims ISPD '99: Proceedings of the 1999 international symposium on Physical designApril 1999 Pages 36–41https://doi.org/10.1145/299996.300015Published:12 April 1999 19citation887DownloadsMetricsTotal Citations19Total Downloads887Last 12 Months30Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access