Daniel Ritter 0001

dblp:82/8248 · DBLP profile ↗
← Back
24ranked-venue papers in the field
8as first author
20since 2021 · last 2026
0000-0001-6146-3365ORCID · verified

Domains — venue-derived; a paper can count in several

Database Systems & Data Management · 22 (6 first)Knowledge Engineering, Semantic Web & Information Systems · 1 (1 first)Business Process & Enterprise Data · 1 (1 first)
YearPublicationVenuePosition
2026 Efficient Parquet Parsing on FPGAs
Si Jun Kwon, Zsolt István, Daniel Ritter 0001, Norman May, Christian Färber
DaMoN3
2026 Exploring Dynamic Memory Allocation of CXL Memory Pools in Enterprise In-Memory Database Management Systems
Donghun Lee 0001, Minseon Ahn, Jaemin Jung, Norman May, Daniel Ritter 0001, Heekwon Park, Changho Choi, Yang-Seok Ki
EDBT6
2026 Unleashing Data Dependency-based Query Optimization
Daniel Lindner, Daniel Ritter 0001, Felix Naumann
EDBT2
2025 The Five-Minute Rule for the Cloud: Caching in Analytics Systems
Kira Duwe, Angelos-Christos G. Anadiotis, Andrew Lamb, Lucas Lersch, Boaz Leskes, Daniel Ritter 0001, Pinar Tözün
CIDR6
2025 Exploiting Locality in Flat Memory with CXL for In-Memory Database Management Systems
abstract
Memory tiering is an effective strategy for enhancing the memoryto-core ratio in modern compute servers.Intel's Flat Memory Mode (FLAT) represents a cutting-edge, hardware-managed memory tiering system for CXL memory, operating at cache-line (64B) granularity with yet unknown potential for database management systems.In this paper, we evaluate the performance of FLAT using OLAP workloads in SAP HANA, an in-memory database management system.Our findings demonstrate that flat memory outperforms directly attached CXL memory by leveraging data placement and exploiting locality.However, FLAT currently accepts only a 1:1 ratio between local and CXL memory.When the local memory capacity increases, FLAT operates in a mixed mode (MIXED) containing flat memory and additional dedicated memory with remaining local memory in a separate NUMA node.Our evaluation of MIXED shows that performance degradation depends on access patterns and the amount of exploited data locality when moving table data to flat memory or allocating heap memory in flat memory.To address the configuration complexity of two separate NUMA nodes in MIXED, we propose a new CONSOLIDATED mode that merges two NUMA nodes.Our evaluation shows that the consolidated mode results in negligible performance degradation, regardless of the ratio between dedicated memory and flat memory, and requires no software modifications at the application level.
Minseon Ahn, Thomas Willhalm, Donghun Lee 0001, Norman May, Daniel Ritter 0001, Oliver Rebholz
DaMoN6
2025 An Empirical Evaluation of Serverless Cloud Infrastructure for Large-Scale Data Processing
Thomas Bodner 0001, Theo Radig, David Justen, Daniel Ritter 0001, Tilmann Rabl
EDBT4
2025 Benchmarking Analytical Query Processing in Intel SGXv2
Adrian Lutsch, Muhammad El-Hindi, Daniel Ritter 0001, Zsolt István, Carsten Binnig
EDBT4
2025 GraphMatch: Subgraph Query Processing on Steroids
abstract
Recently, graphs are becoming increasingly interesting in the context of large language models and as overlays for commercial databases. Subgraph query processing is an especially challenging workload for graph analysis that is bottlenecked by slow set intersection performance on CPUs. Previous work has shown the viability of utilizing hardware acceleration for related domains like graph and relational join processing. We propose GraphMatch, a hardware-accelerated subgraph query processing system based on worst-case optimal joins (WCOJ). For efficient processing of various data and query graphs, we propose a novel set intersection algorithm, called MaxStep, that leverages hardware parallelism. GraphMatch combines MaxStep operators in a data flow architecture which efficiently solves multi-set intersections in subgraph query processing, superior to CPU-based approaches. GraphMatch achieves an average speedup of over 6.98x and 17.08x, compared to the state-of-the-art WCOJ-based systems GraphFlow and RapidMatch, respectively. On labeled graphs, GraphMatch outperforms the fastest subgraph query processing accelerator FAST by orders of magnitude.
Jonas Dann, Tobias Götz, Daniel Ritter 0001, Jana Giceva, Holger Fröning, Gustavo Alonso
Proc. ACM Manag. Data3
2025 CloudGlide: Deconstructing the Landscape of Cloud-Based Analytics
Michail Georgoulakis, Daniel Ritter 0001, Viktor Leis, Jana Giceva
Proc. VLDB Endow.2
2025 The HANA Native Query Engine for Lakehouse Systems
abstract
Modern enterprise applications and data warehouse systems move data into data lakes for economical and scalability reasons. Data is then stored in popular columnar file formats like Parquet which are optimized for writing using open table formats like Iceberg or Delta. This presents new challenges for existing database systems and their execution engines because excellent performance and scalability when accessing this data in complex analytical queries is expected while data is located in a remote data lake. In this work, we present how we adapted the HANA Cloud Database Engine for efficient processing of files in data lakes, which we call SQL-on-Files (SoF). We motivate this evolution by its relevance for Business Data Cloud, SAP's Lakehouse, we discuss the viability of general architecture choices like pushdown and direct access architectures, and give insights into our SoF design decisions towards scalable, analytical query processing around execution engine, optimizer and caching. Our evaluation of SoF shows benefits of direct access over pushdown architectures for a new warehouse benchmark with complex, analytical workloads.
Daniel Ritter 0001, Mihnea Andrei, Sukhyeun Cho, Maik Goergens, Taehyung Lee 0002, Norman May, Amit Pathak, Paul R. Willems
Proc. VLDB Endow.1
2025 CXL Memory Performance for In-Memory Data Processing
abstract
The Compute Express Link (CXL) standard enables new forms of memory management and access across devices and servers. Based on PCIe, it enables cache-coherent access to remote memory. This widens the design space for database systems by expanding the available memory beyond memory local to the CPU. Efficiently utilizing CXL-attached memory requires conscious decisions by data systems about data placement and management. In this paper, we provide an in-depth analysis of database operation performance with data interleaved across multiple CXL memory devices. We experimentally evaluate the memory access performance for basic access patterns, the performance impact of placing data across multiple CXL memory devices for in-memory column scans and in-memory B+tree operations, and the performance impact of placing data in CXL memory for an in-memory database system when running the analytical TPC-H workload. Our experiments show that access to CXL-attached memory does not have to penalize performance over local access, but careful workload-aware data management is required. Our TPC-H evaluation shows that placing table columns based on access frequencies allows storing over 80% of the table data in CXL memory with a performance of 85% of a local-memory-only solution.
Marcel Weisgut, Daniel Ritter 0001, Pinar Tözün, Lawrence Benson, Tilmann Rabl
Proc. VLDB Endow.2
2024 Responsible composition and optimization of integration processes under correctness preserving guarantees
Daniel Ritter 0001, Fredrik Nordvall Forsberg, Stefanie Rinderle-Ma
Inf. Syst.1
2024 An Examination of CXL Memory Use Cases for In-Memory Database Management Systems using SAP HANA
abstract
CXL-based disaggregated memory systems offer options to expand the memory beyond the limits of a single server via cache-coherent memory expansion cards or memory pools. Especially, In-Memory Database Management Systems (IMDBMSs) can benefit from alleviating two critical constraints: (1) limited memory capacity in a server and (2) long restart time during failover to reload data to memory. However, the usage and effectiveness of CXL memory in enterprise-scale IMDBMSs has yet to be validated. In this work---for the first time---we investigate dynamic memory expansion employing commercial CXL memory devices for IMDBMSs. Our detailed performance analysis reveals that the performance impact of higher latency and lower memory bandwidth impact depends on the memory access patterns of data structures (cf. (1)). Additionally, we present the feasibility of CXL shared memory between servers to improve restart times during failover (cf. (2)). Our evaluation shows the effectiveness of CXL memory integrated into the SAP HANA Cloud IMDBMS. OLTP workloads have a negligible performance degradation while OLAP workloads have a wide range of performance degradation. CXL shared memory shows a 40% reduction of the restart time for TPC-H SF10 and 84% potential reduction for TPC-H SF100.
Minseon Ahn, Thomas Willhalm, Norman May, Donghun Lee 0001, Suprasad Mutalik Desai, Daniel Booss, Navneet Singh, Daniel Ritter 0001, Oliver Rebholz
Proc. VLDB Endow.9
2024 POLAR: Adaptive and Non-invasive Join Order Selection via Plans of Least Resistance
abstract
Join ordering and query optimization are crucial for query performance but remain challenging due to unknown or changing characteristics of query intermediates, especially for complex queries with many joins. Over the past two decades, a spectrum of techniques for adaptive query processing (AQP)---including inter-/intra-operator adaptivity and tuple routing---have been proposed to address these challenges. However, commercial database systems in practice do not implement holistic AQP techniques because they increase the system complexity (e.g., intertwined planning and execution) and thus, complicate debugging and testing. Additionally, existing approaches may incur large overheads, leading to problematic performance regressions. In this paper, we introduce POLAR, a simple yet very effective technique for a self-regulating selection of alternative join orderings with bounded overhead. We enhance left-deep join pipelines with alternative join orders, perform regret-bounded tuple routing to find and validate "plans of least resistance", and then process the majority of tuple batches through these plans. We study different join order selection techniques, different routing strategies, and a variety of workload characteristics. Our experiments with a POLAR prototype in DuckDB show runtime improvements of up to 9x and less than 7% overhead for all benchmark queries, while outperforming state-of-the-art AQP systems by up to 15x.
David Justen, Daniel Ritter 0001, Campbell Fraser, Andrew Lamb, Nga Tran 0001, Allison Lee, Thomas Bodner 0001, Mhd Yamen Haddad, Steffen Zeuch, Volker Markl, Matthias Boehm 0001
Proc. VLDB Endow.2
2023 Data Pipes: Declarative Control over Data Movement
Lukas Vogel 0001, Daniel Ritter 0001, Danica Porobic, Pinar Tözün, Tianzheng Wang 0001, Alberto Lerner
CIDR2
2023 DASH: Asynchronous Hardware Data Processing Services
Norman May, Daniel Ritter 0001, Andre Dossinger, Christian Färber, Süleyman Sirri Demirsoy
CIDR2
2023 Elastic Use of Far Memory for In-Memory Database Management Systems
abstract
The separation and independent scalability of compute and memory is one of the crucial aspects for modern in-memory database systems (IMDBMSs) in the cloud. The new, cache-coherent memory interconnect Compute Express Link (CXL) promises elastic memory capacity through memory pooling. In this work, we adapt the well-known IMDBMS, SAP HANA, for memory pools by features of table data placement and operational heap memory allocation on far memory, and study the impact of the limited bandwidth and higher latency of CXL. Our results show negligible performance degradation for TPC-C. For the analytical workloads of TPC-H, a notable impact on query processing is observed due to the limited bandwidth and long latency of our early CXL implementation. However, our emulation shows it would be acceptably smaller with the improved CXL memory devices.
Donghun Lee 0001, Thomas Willhalm, Minseon Ahn, Suprasad Mutalik Desai, Daniel Booss, Navneet Singh, Daniel Ritter 0001, Oliver Rebholz
DaMoN7
2022 PipeJSON: Parsing JSON at Line Speed on FPGAs
abstract
JavaScript Object Notation (JSON) gained popularity as a data exchange and storage format. While recent advances on modern CPUs show an improved JSON parsing by using data parallelism with vector instructions, the rigid instruction set and limited pipelining of CPUs prevent parsing performance from reaching the practical limit of memory bandwidth.
Jonas Dann, Royden Wagner, Daniel Ritter 0001, Christian Färber, Holger Fröning
DaMoN3
2022 Cost-aware process modeling in multiclouds
Daniel Ritter 0001
Inf. Syst.1
2021 Formal foundations for responsible application integration
abstract
Enterprise Application Integration (EAI) constitutes the cornerstone in enterprise IT landscapes that are characterized by heterogeneity and distribution. Starting from established Enterprise Integration Patterns (EIPs) such as Content-based Router and Aggregator, EIP compositions are built to describe, implement, and execute integration scenarios. The EIPs and their compositions must be correct at design and runtime in order to avoid functional errors or incomplete functionalities. However, current EAI system vendors use many of the EIPs as part of their proprietary integration scenario modeling languages that are not grounded on any formalism. This renders correctness guarantees for EIPs and their composition impossible. Thus this work advocates responsible EAI based on the formalization, implementation, and correctness of EIPs. For this, requirements on an EIP formalization are collected and based on these requirements an extension of db-net, i.e., timed db-net , is proposed, fully equipped with execution semantics. It is shown how EIPs can be realized based on timed db-nets and how the correctness of these realizations can be shown. Moreover, the simulation of EIP realizations based on timed db-nets is enabled which is essential for later implementation. The concepts are evaluated in many ways, including a proof-of-concept implementation and case studies. The EIP formalization based on timed db-nets constitutes the first step towards responsible EAI.
Daniel Ritter 0001, Stefanie Rinderle-Ma, Marco Montali, Andrey Rivkin
Inf. Syst.1
2017 Patterns for emerging application integration scenarios: A survey
Daniel Ritter 0001, Norman May, Stefanie Rinderle-Ma
Inf. Syst.1
2016 Exception Handling in Message-Based Integration Systems and Modeling Using BPMN
abstract
Enterprise Integration Patterns (EIP) are a collection of widely used patterns for integrating enterprise applications and business processes. These patterns represent a “de-facto” standard for design decisions when integrating enterprise applications. For the specification of integration scenarios, the patterns’ control and data flow syntax and semantics have been expressed in the Business Process Model and Notation (BPMN). However, exceptions during message processing are left for further studies. In previous work, we specified common technical, exceptional situations in integration systems and derive exception types, for which we define a compliant representation in BPMN, resulting in general patterns for exception handling and compensation. In addition to the patterns, the Exception Flow was introduced, evaluated syntactically and semantically for representative integration scenarios. In this work, we complement these contributions by extending the exception strategies and patterns, and by adding an evaluation of pattern-based compilation from BPMN-based integration descriptions to an open source integration runtime system.
Daniel Ritter 0001, Jan Sosulski
Int. J. Cooperative Inf. Syst.1
2015 Integration Adapter Modeling
Daniel Ritter 0001, Manuel Holzleitner
CAiSE1
2014 DatalogBlocks: Relational Logic Integration Patterns
Daniel Ritter 0001, Jan Broß
DEXA (2)1