This demo presents viciLogic2.0, a scalable, distributed, online learning and prototyping platform for gold-standard, basic-to-advanced digital logic design and prototyping education. viciLogic2.0 uses a Xilinx PYNQ [1] reconfigurable System on Chip (SoC) cloud array, and locally-connected SoCs. Client and browser applications provide control and visualisation of the state of all user design signals in real time, within the automatically-allocated and configured remote programmable logic hardware. Each SoC includes an Ethernet-connected ARM-based server which facilitates FPGA resource selection, configuration and control, and remote user interaction. This enables the creation of responsive, interactive client local and browser applications, connected directly to hardware, and online technology enhanced learning applications.

This paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. The viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. The platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. This enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. The prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. The builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. The paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE).

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.

The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33×109spikes/second), and synthesis results using 65-nm CMOS technology demonstrate low cost area (0.587mm2) and power consumption (13.16mW @100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.

Learning in digital systems can be enhanced through applying a learn-by-doing approach on practical hardware systems and by using Web-based technology to visualize and animate hardware behavior. The authors have reported the Web-based Remote FPGA Lab (RFL) which provides a novel, real-time control and visualization interface to a remote, always-on FPGA hardware implementation. The RFL helps students to understand and reason about digital systems operation, using interactive animation of signal behavior in an executing digital logic system, at any level of the design hierarchy. The RFL supports the creation of real-time interactive digital systems teaching demos. The article presents student RFL usage data and survey data which highlight improved student engagement, learning and achievement. The article describes the RFL architecture, communication interface, Web page functionality, user access administration and database management. The article also describes the RFLGen program, developed to automate user design integration into the Xilinx ISE VHDL-based RFL project wrapper for creation of FPGA configuration bitstreams and RFL animations.

This work presents an Embedded Routing Database (ERDB), which contains the complete description of the inter-tile routing shapes available in various Xilinx FPGA tiles, and the mapping of Programmable Interconnection Point (PIP) bits within the FPGA configuration bit stream. ERDB provides the RC system with knowledge of its own architecture and facilitates RC systems in implementing autonomic (self-managing and adaptive) computing. ERDB also protects the integrity of the RC system and supports design Intellectual Property (IP) protection. The paper describes the automated generation of a size-optimised ERDB (3.7 MB memory footprint for the Virtex-5 LX50T device) and its application within the Secure Reconfiguration Controller (SeReCon), as a minimised FPGA fabric description for on-line verification of IP core's integrity during partial reconfiguration. Results demonstrate the feasibility and accuracy of the SeReCon/ERDB-based design (IP core) routing verification that, when applied to an example IP block, detects >99% of the configured PIPs.

This paper describes a scalable and extendable Remote Field Programmable Gate Array Laboratory (Remote FPGA) which can be used to enhance the learning of digital systems and FPGA applications. The web-based console provides an always-on, real-time, interactive control and visualisation interface to/from a bank of remote FPGAs. A Xilinx ISE project template enables integration of user HDL-based designs to execute on the Remote FPGA. Host-FPGA communication is supported using a register-based interface. Users can create real-time, interactive and visual demonstrators of digital systems components. The paper presents a demonstrator for a Finite State Machine (FSM) application, and illustrates the use of web-based control and visualisation for enhanced learning of FSM behaviour. The paper also presents a case study of the use of Remote FPGA in undergraduate teaching.

This paper presents ACROMUSE, a novel genetic algorithm (GA) which adapts crossover, mutation, and selection parameters. ACROMUSEs objective is to create and maintain a diverse population of highly-fit (healthy) individuals, capable of adapting quickly to fitness landscape change and well-suited to the efficient optimization of multimodal fitness landscapes. A new methodology is introduced for determining standard population diversity (SPD) and an original measure of healthy population diversity (HPD) is proposed. The SPD measure is employed to adapt crossover and mutation, while selection pressure is controlled by adapting tournament size according to HPD. In addition to selection pressure control, ACROMUSE tournament selection selects individuals according to healthy diversity contribution rather than fitness. This proposed selection mechanism simultaneously promotes diversity and fitness within the population. The performance of ACROMUSE is evaluated using various multimodal benchmark functions. Statistically significant results are presented comparing ACROMUSEs fitness and diversity performance to that of several other GAs. By maintaining a diverse population of healthy individuals, ACROMUSE responds to fitness landscape change by restoring better fitness scores faster than other GAs. Analysis of the adaptive operators illustrates that the key benefit of ACROMUSE is the synergy of the operators working together to achieve an effective balance between exploration and exploitation.

The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially Reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools. This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic front-end allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by “recipe” scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system. The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs.

No abstract available.

Two variants of biologically inspired cell model, namely eukaryotic (containing a nucleus) and prokaryotic (without a nucleus) are compared in this research. The comparison investigates their relative evolvability and ability to integrate external environmental stimulus to direct protein pattern formation within a single cell. To the authors' knowledge there has been no reported work comparing the relative performance of eukaryotic and prokaryotic artificial cells models. We propose a novel system of protein translocation for eukaryotic cells based on the process of nucleocytoplasmic transport observed in biological cells. Results demonstrate that eukaryotic cell models exhibit a higher degree of sensitivity to environmental variations compared with prokaryotes. Based on these results we conclude that the process of transporting proteins to and from the nucleus plays a key role in shaping eukaryotic cell plasticity.

As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. The current multi-player, partial-reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. This paper proposes the use of a secure reconfigurable controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. This paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.

This paper presents an Adaptive Genetic Algorithm (AGA) where selection pressure, crossover and mutation probabilities are adapted according to population diversity statistics. The creation and maintenance of a diverse population of healthy individuals is a central goal of this research. To realise this objective, population diversity measures are utilised by the parameter adaptation process to both explore (through diversity promotion) and exploit (by local search and maintenance of a presence in known good regions of the fitness landscape). The performance of the proposed AGA is evaluated using a multi-modal, multi-dimensional function optimisation benchmark. Results presented indicate that the AGA achieves better fitness scores faster compared to a traditional GA.

This paper details the hardware evolution of adaptive Spiking Neural Network (SNN) controllers, implemented on a network of cascaded Field Programmable Analogue Arrays (FPAAs). The fixed architecture, feed forward SNNs are trained using a Genetic Algorithm (GA). An obstacle avoidance simulated robotics controller application is chosen to test the FPAA reconfigurable hardware evolution platform. Evolved behaviours, resulting from FPAA-based SNN controllers, are compared with those obtained using software-based SNN implementations. Results presented indicate the emergence of effective behaviours and adaptation to environmental change.

This paper describes an approach to run-time management of reconfigurable hardware tasks executing under supervision of a Linux OS. The proposed system offers transparent integration of reconfigurable resources within the software design and execution flow. The implementation of the reconfigurable task manager architecture is described. Optimizations important for throughput between software and hardware tasks are presented. Mixed hardware-software AES and IDEA implementations on a Xilinx Virtex- H-Pro FPGA demonstrate and evaluate key points of the proposed approach.

In this paper a genetic algorithm has been developed to evolve a neural network (NN) implementation of a two input XOR function. This GA will subsequently be used to contrast the relative difficulties of implementing the XOR NN on FPGA's and FPAA's respectively. Two case studies are presented to demonstrate intrinsic evolution of the XOR network on reconfigurable analogue and digital devices. In both cases the GA evolves the synaptic weights and threshold values for an NN implemented on both field programmable gate array (FPGA) and field programmable analogue array (FPAA) hardware platforms

This paper describes an FPGA and distributed RAM architecture for an image classifier, implementing object classification stages of an object detection system. The system offers significant performance increase over current programmable DSP-based implementations. The paper shows that the considerable performance improvement using the FPGA solution results from the availability of high I/O resources and pipelined architecture. It also illustrates the suitability of an FPGA solution for tasks (such as real-time video processing) that have a large data throughput and require complex algorithmic manipulations. The system has been implemented using the RC1000-PP Virtex FPGA-based development platform and Handel-C hardware description language.