An improved implementation of clock synchronization of multiprocessor systems in the presence of malicious faults is proposed. The proposed hardware implementation for the reference clock selection has a lower gate complexity, smaller time delay, and greater flexibility than the previously published implementation. The improvement is achieved by replacing the sorter with a counting encoder and comparators and by introducing threshold generation logic with programmable registers. The scheme has a gate complexity of O(n) and a delay of O(log n), where n is the total number of inputs to a particular clock, and is programmable for different values of n and m, the maximum number of faults.>