Verifying an implementation produced from high-level synthesis is a challenging problem due to many complex design tasks involved in the design process. In this paper we present an architectural rule checking approach for high-level design verification. This technique detects and locates various design errors and verifies both the consistency and correctness of an implementation. Besides describing different rule suites, we also report a working environment for the architectural rule checking. Finally, we highlight the value of the proposed approach with a real-life design.

Presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly support a broad range of architectural design applications from datapath-dominated digital signal processing (DSP) to commodity ICs such as microprocessors/microcontrollers and control-dominated peripherals, utilizing multiphase clocking schemes, multiple threading, data-dependent delays, pipelining, and combinations of the above. The work presented in this paper is an enabling technology for high-level synthesis to go beyond traditional datapath-dominated DSP applications and to start becoming a viable and cost-effective design methodology for commodity ICs.

Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions.

Abstract { This paper describes the use of Uni ed System Construction tools under development at the University of Southern California. The goal of the project is to automate the construction of heterogeneous, applicationspeci c systems. Key elements of the USC system include multiprocessor synthesis, multi-chip datapath synthesis, memory-intensive synthesis, and multi-chip partitioning. The tools were applied to design of an image compression chip set, and results of using these tools are reported on here. Our results are comparable to manual designs reported in the literature. 1