Hyperspectral images (HSIs) are the images that have a high spectral resolution with hundreds of bands. HSIs are widely used in the precise identification and classification of the materials and surfaces. However, they have a low spatial resolution caused by the limited capacity of the sensors responsible for capturing the images. In view of this, the preprocessing techniques are used to increase the spatial resolution of the HSIs and enable greater precision in the subsequent processing stages. This letter presents the development of a hardware accelerator specially designed to process a pansharpening algorithm that fuses the hyperspectral and panchromatic images to produce a high spatial resolution HSI. The experimental results demonstrate that the processor is energy-efficient and can be used for onboard processing in a small spacecraft, such as the satellites.

The popularization of multimedia services has pushed forward the development of 2D/3D video-capable embedded mobile devices. Such devices require efficient energy/memory-management strategies to deal with severe memory/processing requirements and limited energy supply. Therefore, we propose a motion and disparity estimation (ME and DE) system—the most memory/processing demanding encoding steps—for the 3D High Efficiency Video Coding (3D-HEVC) standard. It was designed for low energy consumption, featuring a run-time adaptive memory hierarchy. The processing unit employs flexible coding order and optimizations to reduce the computational effort by exploring the inter-channel and inter-view redundancies. The memory hierarchy features window-based prefetching, data reuse, subsampling, and dynamic voltage scaling controlled by our depth-based dynamic search window resizing algorithm. Memory results demonstrate an average on-chip energy reduction of 79% in comparison to the widely used Level-C solution for a 45-nm technology. The proposed energy-aware ME and DE system dissipates 7.55 W while processing three HD 1080p views (video + depth) at 30 frames per second and presents a mean energy consumption of 0.107 J per access unit. To the best of our knowledge, this is the first work that proposes a real-time ME/DE system for the 3D-HEVC standard with an adaptive memory hierarchy.

Parallel applications are essential for efficiently using the computational power of a Multiprocessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. Moreover, synchronization is also a bottleneck due to sequential access to shared memory. We address this issue and introduce "Subutai", a hardware/software (HW/SW) architecture designed to distribute essential synchronization mechanisms over the Network-on-Chip (NoC). It includes Network Interfaces (NIs), drivers and a custom library of a NoC-based MPSoC architecture that speeds up the essential synchronization primitives of any legacy parallel application. Besides, we provide a fast simulation tool for parallel applications and a HW architecture of the NI. Experimental results with PARSEC benchmark show an average application speedup of 2.05 compared to the same architecture running legacy SW solutions for 36% overhead of HW architecture.

This paper presents a novel hardware-friendly Unidirectional Disparity-Search (UDS) algorithm for the 3D-HEVC. This algorithm explores the typical camera arrangements used in 3D-HEVC. UDS was evaluated in two operation points reaching a computational effort reduction from 32.7% to 61.8%, with a BD-Rate increase from 0.3123% to 0.4803%, when compared to TZS. Estimated hardware results showed memory-size and leakage-energy reductions of 66.7%, a dynamic-energy reduction from 34.5% to 62.1%, and an energy-consumption reduction from 32.7% to 61.8% in SAD calculations, when compared to TZS. To the best of the authors' knowledge, this is the first proposed DE algorithm that explores the 3D-HEVC typical camera arrangement.

This paper proposes a new technique for two-view camera pose estimation applied to vehicular monocular visual odometry. The proposed method is based on the resection-intersection concept using Gauss-Newton non-linear regression to minimize projection residuals. Different from other solutions, the proposed method does not suppose fixed positions of points during resection but rather takes into account the adjustment in the 3-D position of points when calculating the new camera pose increment. A simplified fast two-view triangulation method is used to mitigate the cost of intense 3-D point position recalculation. The method is integrated into a monocular visual odometry solution and tested on the KITTI public dataset. The final system does not use loop closing or key frame selection, and RANSAC is replaced by sequential backward selection. The resection-intersection method presents robustness to errors in initial camera pose and rapid convergence rate, reaching the final camera pose in up to three iterations in 65% of the cases. A single thread Python/OpenCV implementation of the monocular visual odometry system on an Intel Core i7 spent around 75 ms per frame, of which one third was used in the resection-intersection step. The achieved results presented better accuracy than all other published monocular odometry works in the KITTI benchmark, in a simple solution using only two consecutive frames for camera pose estimation.

This paper presents a low-power and high-throughput hardware design for the 3D-HEVC (Three Dimensional High Efficiency Video Coding) Depth Intra Skip coding tool. A strategy to reduce the computational effort was employed based on an analysis using the 3D-HEVC reference software. The proposed strategy consists of replacing the SVDC (Synthesized View Distortion Change) for the SAD (Sum of Absolute Differences) as the similarity criterion. This way, the number of arithmetic operations related with the similarity criterion is reduced over 71%, and a rendering process is avoided at the cost of only 0.21% increase in the BD-Rate. The hardware was described in VHDL and synthesized for ASIC technology. The synthesis results for the 45nm Nangate standard cells demonstrate that the architecture can process 60 UHD 2160p frames per second (five views) with a power dissipation of 19.57mW.

This paper presents a hardware design for the sub-sample interpolator used in FME (Fractional Motion Estimation) and MC (Motion Compensation) stages according to the VP9 and VP10 video-coding standards. The proposed architecture is able to save hardware resources through an optimized-filter organization whereas reaching high-throughput and low-power dissipation. The hardware design was described in Verilog and synthesized for ASIC technology. The synthesis results were generated for 45nm Nangate standard cells and demonstrate that the developed architecture is able to process 2160p@60fps videos with a power dissipation of 2.34mW focusing on a VP9-10 decoder.

Three-Dimensional (3D) integrated circuits (ICs) have emerged as a solution to attend the demand of high performance, low power and high density of the MultiProcessors Systems-on-Chip (MPSoCs). However, some important issues need to be observed in the interconnection device for 3D designs. In this paper we have presented the advantages of the 3D-HiCIT network-on-chip (NoC) when compared to other hierarchical topologies in terms of flexibility, scalability and performance. Considering all constraints of this new scenario of circuit integration, the proposed hierarchical 3D NoC verified in this work meets well with the reality of these designs, presenting gains in several aspects.

This paper presents an application-driven algorithm for Dynamic Thermal Management (DTM) for the High Efficiency Video Coding (HEVC). For efficient design of such a DTM policy, we perform an offline thermal analysis of an HEVC encoder and demonstrate the impact of different video sequences and different coding configurations on the processor temperature. Our thermal analysis is leveraged to develop an efficient application-driven DTM policy that performs temperature-aware coding along with an application-driven control of DTM knobs (e.g., frequency scaling) in order to meet the temperature constraints while still providing high video quality (i.e. PSNR loss <; 0.01dB). For accurate thermal analysis and evaluation, we deploy an infrared camera-based thermal measurement setup that, on the contrary to state-of-the-art setups, does not require adding any extra layer on top of the measured chip, thus allowing the camera to accurately capture the infrared emissions from the die.

This paper presents a resource optimized hardware solution to perform the H.264 8x8 inverse transform. Row/column decomposition is used, arithmetic units are re-used and the transpose memory is replaced by a shift register. The architecture is able to perform 8x8 integer transform calculation in 144 cycles with as few as 431 LUTs on a Xilinx virtex 6 FPGA for 16-bit resolution. To enable the module to process all inverse transforms in H.264, the number of LUTs is increased to 681. When used to calculate all transforms for H.264 videos, the design supports resolutions up to 1280x720@30fps when running at 84 MHz.

Systems-on-chip for multimedia applications present strict requirements for the memory subsystem regarding bandwidth and latency. Typically the CPU and several IPs are connected to a multi-client memory subsystem to access data in a shared memory channel. An arbiter manages accesses conflicts due to concurrent memory requests. In this paper it is proposed an intelligent arbitration algorithm able to classify clients at runtime, according to their access requirements. The arbiter state variables are adjusted at run-time, increasing the memory channel performance if compared to a non automated client scheduling. Simulated results showed an average latency improvement of 29.4% for a multimedia SoC.

The exigency for heterogeneous many-core systems has brought an exponential growth in the complexity of their interconnections. In this manner, other Network-on-Chip (NoC) alternatives are being sought to attend the requirements in terms of power consumption and performance. Nevertheless, several of these proposals present very complex architectures, with virtual channels, tables and extra controls. In this paper we propose the junction of two advantageous strategies: hierarchical topology with adaptability. The use of these two techniques is novel in the literature and it allows ensuring high performance even when the application has their communication rates altered. The gains in power and in performance are possible due to the use of low cost components in a hierarchical structure.

This paper presents an adaptive temperature optimization technique for the next generation video encoders. It exploits both application-specific knowledge (i.e. video encoding configurations) and video content properties in order to efficiently manage the temperature of advanced video coding systems at the software layer. For designing an efficient technique, we perform an extensive offline analysis to understand the impact of different video properties and configurations on the CPU thermal profiles when processing the next generation video encoder. Our temperature optimization technique performs an application-level prediction of the temperature trend followed by an application-level thermal management policy. The policy dynamically manages the temperature by performing an adaptive encoder configuration selection while providing minimum penalties in terms of bit rate and video quality. The experimental results show that our policy meets temperature constraints with negligible encoding performance loss. Moreover, when compared to state-of-the-art techniques, our policy provides a relatively reduced video quality loss while still meeting the temperature constraints.

This paper presents a fast mode decision algorithm for the HEVC intra prediction. A new evaluation order in the Coding Tree Block (CTB) allows the use of modes from low level PUs to be used as reference to the current PU decision. In this paper we use this idea to develop a fast intra mode decision algorithm that can be configured to run in two different complexity modes, relaxed and aggressive. Experimental results have shown that our algorithm achieved encoding time savings of almost 60% with negligible loss in the compression efficiency when compared to the full RDO based decision. Besides, our mode decision algorithm presented the best result in terms of time saving per compression efficiency when compared with all related works.

Multi-Processors Systems-on-Chip (MPSoCs) are demanding for high performance, low power and high density, and therefore, three-dimensional integrated circuits (3DIC) emerge as a solution to integrate these systems. In order to appropriately interconnect the layers of these systems in terms of flexibility and scalability, a Network-on-Chip (NoC) is typically employed. In this paper, we argue about the scenario of 3D designs, covering all important issues about this new concept. In agreement with all features discussed in this paper, we have proposed a hierarchical 3D topology that meets well the reality of these designs. Experimental results analyze different topologies and show the large benefits in area and power of our proposal.

This work proposes a hardware architecture for the Intra Frame Prediction of the emerging High Efficiency Video Coding (HEVC) standard. The architecture was designed considering all innovative features of the Intra Prediction included in the HEVC, i.e. all modes and all Prediction Units (PU) sizes. Performance and memory accesses are a problem in the HEVC intra prediction and hardware architecture designs are good alternative to solve these issues, especially when energy-efficient solutions are targeted. Buffers and internal memories were used in the designed architecture to decrease the number of external memory accesses. Two independent data paths processing eight samples in parallel and a deep and multiplierless pipeline were designed to increase the throughput. The architecture was synthesized using an IBM 65nm CMOS technology. The results have shown that the architecture is able to process 30 HD720p frames per second and 13 HD1080p frames per second when running at 500 MHz, reducing in 95% the accesses to the external memory.

Networks-on-chip has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip (MPSoC). Complex router architectures can be prohibitive for the embedded domain, once they dissipate too much power and energy. In this paper we propose a low power hierarchical network topology with GALS interfaces, allowing each cluster operates in a specific frequency. The clusters are composed by crossbar devices and the number of cores allocated for each cluster is defined considering floorplan information. Experimental results show that our strategy can reduce the power dissipation in up to 58% and the latency in up to 56% for the benchmarks analyzed when compared with a packet-switched mesh network-on-chip.

The ITU-T H.264 can be considered currently as the most efficient professional video coding standard. This codec combines distinct complex techniques in order to encapsulate raw video into efficient compressed streams. Unfortunately, the improved H.264 coding efficiency increases significantly the computational complexity, making real-time applications difficult to be achieved. Particularly the motion prediction is an important and complex algorithm used to remove temporal redundancy of image sequences. Considering that, we propose an optimized high performance small diamond topology zonal search motion prediction algorithm. The proposed method has been designed to operate with orthogonal linear vectors, which are specially aligned with 4:1 sub sampled memories organization reducing the number of operations and data manipulations. The proposed solution was implemented in the H.264 JM reference software obtaining results at least two times faster than other available fast algorithms with negligible quality losses.

In this work we present a high throughput hardware architecture for the H.264/AVC intra-frame encoder exploiting the parallelism of intra prediction, forward and inverse transforms and quantization. Since there is a strong data dependency between the intra prediction and the image reconstruction loop, the latency of this path is a key design issue in order to provide high performance coding. Considering that 77% of the total intra-encoding computation is spent in these modules, our architecture handles a 4-pixel wide intra prediction module and a 16-pixel wide reconstruction loop. Compared to the state-of-the-art our approach reduces by 47% the number of cycles to process a macroblock. Running at 150 MHz our architecture guarantees encoding of 61 HD1080p frames per second. The developed architecture requires 73.4 MHz to real-time encode HD1080p, which is a 46% reduction of the frequency requirement compared to the state-of-the-art.

Network-on-chip (NoC) designs are based on a compromise among latency, power dissipation, or energy, and the balance is usually defined at design time. However, setting all parameters, such as buffer size, at design time can cause either excessive power dissipation (originated by router under utilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, e.g., a portable phone downloads a new service. Large buffer sizes can ensure performance during the execution of different applications, but unfortunately, these same buffers are mainly responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of a reconfigurable router, where the buffer slots are dynamically allocated to increase router efficiency in an NoC, even under rather different communication loads. In the proposed architecture, the depth of each buffer word used in the input channels of the routers can be reconfigured at run time. The reconfigurable router allows up to 52% power savings, while maintaining the same performance as that of a homogeneous router, but using a 64% smaller buffer size.

MPSoCs systems are composed of heterogeneous cores, and for this reason, the cores can present different bandwidth, different clock domains or still they can require an irregular traffic behavior. When networks-on-chip (NoCs) are used to connect these cores, one very often needs some synchronization solution, and due to the mentioned problems, this might be required for synchronous or asynchronous NOCs. In this paper we show a network interface (NI) with a synchronizer wrapper solution. We verified its applicability for different channel widths and buffer depths of a NoC. These network interfaces were used to connect a H.264 decoder and the simulation results demonstrate that the wrapper provides a reliable synchronization solution, and does not compromise the latency of the network. These interfaces have been successfully implemented in a 0.18um CMOS technology.

The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamard and Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

The cores of a System-on-Chip (SoC) connected by Networks-on-Chip (NoCs) need interfaces to properly send and receive packets. However, in this interfacing, different situations can occur when heterogeneous cores are applied. Applications may require, for example, an irregular traffic behavior or present a large bandwidth variation. These situations may lead to problems in data synchronization. In this paper we show a simple and efficient synchronization solution, which although known in the literature, has not yet been applied to NoC-based systems scenario. Using a network interface as the synchronization mechanism, the proposed circuit handles data dependencies instead of letting each core solve the synchronization problems at higher levels. As case study, an H.264 video decoder was used to show the need and advantage of our approach. The proposed design is FIFO-based and can be applied when multiple packets from different sources need to be synchronized in a single destination. Simulations were performed to verify the functionality and efficiency of the synchronization solution. These interfaces were implemented in VHDL and synthesized using an 180 nm CMOS technology.

This work presents an intra frame prediction hardware architecture for H.264/AVC baseline/main profile encoder which performs real time processing of HDTV 1080p videos. It is achieved by exploring the parallelism of intra prediction and by reducing the latency for Intra 4times4 processing, which is the intra encoding bottleneck. Synthesis results on Xilinx Virtex-II Pro FPGA and TSMC 0.18 mum standard-cells indicate that this architecture is able to real time encode HDTV 1080p video operating at 110 MHz. Our architecture can encode HD1080p, 720p and SD video in real time at a frequency 25% lower when compared to similar works.

Although the H.264 Deblocking Filter process is a relatively small piece of code in a software implementation, profile results shows it cost about a third of the total CPU time in the decoder. This work presents a high performance architecture for implementing a H.264 Deblocking Filter IP that can be used either in the decoder or in the encoder as a hardware accelerator for a processor or embedded in a full-hardware codec. A developed IP using the proposed architecture support multiple high definition processing flows in real-time. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper presents a high throughput and low cost architecture for motion estimation using a sub-sampled diamond search algorithm (SDS). The quality of SDS was compared with full search through software implementations and the results are presented. The designed hardware considered a search area of 100times100 samples, with blocks of 16times16 pixels. The architecture was described in VHDL and mapped to a Xilinx Virtex-4 FPGA. Synthesis results indicate that SDS is able to run at 185.7 MHz, using only 3541 LUTs. This architecture can reach real time for HDTV (1920times1080 pixels) in the worst case, and it can process 120 HDTV frames per second in the average case.

This work presents the HP422-MoCHA, the first published hardware architecture that implements a full compliant H.264/AVC motion compensator for high profile 4:2:2. The hardware is composed by three main modules: Motion Vector Predictor, Memory Access and Sample Interpolator. The designed architecture was described in VHDL and mapped to a Xilinx Virtex-II PRO FPGA. This architecture reaches the throughput to decode HDTV Level 4 (1080p) @ 30fps.

RF test signals are a requirement for the implementation of effective BIST techniques in transceivers. In this work a method to encode a binary signal with the desired RF frequency is presented. The approach employs high-pass sigma delta modulators, in contrast to conventional low- pass or band-pass approaches, allowing signal generation close to the Nyquist limit of FS/2 (FS=sampling frequency). As a digital signal is used, only a 1-bit DAC is needed, reducing test costs. Practical results using a 3Gbps transceiver illustrate the performance achievable by the method.

In this paper we compare three non-rigid registration methods for atlas-based segmentation: B-splines, morphons and a combination of morphons and demons. To assess the quality of each method, we use a data set of four patients, containing for each patient the computed tomography (CT) image and a manual segmentation of the organs at risk performed by an expert of the head and neck anatomy. Non-rigid registration algorithms have been used to match the patient and atlas images. Each deformation field, resulting from the non-rigid deformation, have been applied on the masks corresponding to segmented regions in the atlas. The atlas based segmented masks have been compared to manual segmentations performed by the expert. The results show that the combined method (morphons + demons) achieves the best performances on this dataset resulting in an average improvement of 6% with respect to morphons and 18% with respect to B-spline.

This paper presents an architecture for implementing the H.264 Deblocking Filter with RGB output in FPGA, exceeding HDTV requirements when synthesized to a target FPGA. The goal of the design was to achieve the HDTV requirements, designing a deep pipelined architecture that makes a balanced use of the resources available in the target FPGA architecture. When synthesized to VirtexII-pro FPGA, the developed architecture used only 1800 logic cells and achieved 71 frames per second at 1080p HDTV resolution (1920x1080).

This paper discusses low cost RF signal generation for BIST, using only digital circuits. One major problem is the range of frequencies that can be achieved by any digital signal generator, since the Nyquist limit is the clock frequency divided by 2 (FS/2). The proposed method uses the images of the signal in order to reach frequencies beyond FS/2. Different digital signal generation techniques for RF and their limitations are addressed as well as their impact in the framework of analog RF BIST. Experimental results and comparisons are provided using a gigabit transceiver

In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources in order to minimize the test overhead. An RF sampler is used to observe spectral characteristics of the RF signal path during loopback operation. While able to improve the observability of the signal path, the method also allows faster diagnosis than conventional loopback tests, as the number of transmitted symbols can be greatly reduced. Practical results for a prototyped RF link at 860MHz are presented in order to demonstrate the relevance of the method

This paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations down to prototyping. The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.

This work tries to reuse programmable communication resources like a network-on-chip (NoC) in the acceleration of image applications. We show a mathematical model for the computation and communication pattern of two distributed motion estimation algorithms, full search block matching algorithm and multi-resolution block matching algorithm. Experimental results show that the use of the multi-resolution method reduces not only the computation time but also the traffic of messages on the NoC. This leads to a lower power consumption in the NoC during the processing time of each image. The studied examples show the importance of the link between algorithms and their mapping onto a programmable fabric, not only regarding computation, but facing communication as well

This paper presents a technique for automatic generation of image processing architectures based on artificial neural networks (NN) for real time vision applications in order to reduce the hardware design effort. The generated datapath can be reused with different functions. A high throughput is obtained with one output pixel being produced at each clock cycle for each input pixel, allowing VGA stream processing. NN used is MLP, trained by back-propagation. Function training is executed in a C++ software. Then VHDL code of the image processing IP core is automatically generated. Image processing systems using the generated IP cores were evaluated in FPGA, showing both good performance and suitability of the method

Multimedia applications need larger and larger bandwidth. The only way to face these demands is to provide more efficient compression algorithms, with the expense of computational complexity. The most efficient compression standard available today is the H.264/AVC. On the architectural point of view, an H.264 decoder can be seen as a system of six main modules: entropy decoder, inverse quantization, inverse transform, motion compensation, intraframe prediction and deblocking filter. These modules can be designed independently and enclosed in IPs, which could be used later to build an H.264 SoC. This paper presents an architecture design of intraframe prediction module. The system was completely built in VHDL language and prototyped over a Xilinx Virtex II Pro FPGA of 27,392 logic elements. The proposed architecture attained the required performance to decode HDTV video stream in realtime, i.e. 1920 times 1080 pixels at 30 frames per second, and used just 20% of the chip

This work analyzes, the mapping of applications onto generic regular Networks-on-Chip (NoCs). Cores must be placed considering communication requirements so as to minimize the overall application execution time and energy consumption. We expand previous mapping strategies by taking into consideration the dynamic behavior of the target application and thus potential contentions in the intercommunication of the cores. Experimental results for a suite of 22 benchmarks and various NoC sizes show that a 42% average reduction in the execution time of the mapped application can be obtained, together with a 21% average reduction in the total energy consumption for state-of-the-art technologies.

Complex applications implemented as systems on chip (SoC) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoC). Modeling applications involves capturing its computation and communication characteristics. Previously proposed communication weighted models (CWM) consider only the application communication aspects. This work proposes a communication dependence and computation model (CDCM) that can simultaneously consider both aspects of an application. It presents a solution to the problem of mapping applications on regular NoC while considering execution time and energy consumption. The use of CDCM is shown to provide estimated average reductions of 40% in execution time, and 20% in energy consumption, for current technologies.

A technique for noise figure evaluation, suitable for BIST implementation, is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of the noise figure in several test points of the analog circuit. The method is also able to benefit from SoC resources, like memory and processing power. The theoretical background and experimental results are presented in order to demonstrate the feasibility of the approach.

In this study we investigated event related-potential (ERP) component c247, which reflects the recognition process in two classes of subject: a sample with high risk (HR) for alcoholism and a sample of control subjects with low risk (LR). The results of this study suggest that the amplitude of the c247 to repeated pictures of common objects was decreased significantly as compared to the unrepeated pictures for the LR group, but the same was not observed in the HR group. For the matching stimulus we describe an application of an artificial neural network (ANN) technique together with a feature extraction, the wavelet transform, for the classification of ERPs. Two classes of ERP were used: HR for alcoholism and LR for alcoholism. The architecture of the ANN used in the classification is a three-layered feedforward network that implements the backpropagation of error learning algorithm. After training, the network with wavelet coefficients was able to correctly classify over 71% of the HR and LR class of ERP.

A low cost method for testing analogue RF signal paths suitable for BIST implementation in a SoC environment is described. The method is based on the use of a simple and low-cost one-bit digitizer that enables the reuse of processor and memory resources available in the SoC, while incurring little analogue area overhead. The proposed method also allows a constant load to be observed by the circuit, since no switches or muxes are needed for digitizing specific test points. Mathematical background and experimental results are presented in order to validate the test approach.

The building block of a network-on-chip (NoCs) is its router. It is responsible to switch the channels which forward the messages exchanged by the cores attached to the NoC, and the costs and performance of the NoC strongly depends on the router architecture. In this paper, we present RASoC, a router architecture intended to be used in the building of low area overhead NoCs for embedded systems. The difference among RASoC and current routers relies on its implementation as a parameterized VHDL model, which improve the reuse of RASoC in the synthesis of NoCs with different sizes, and allows the tuning of the NoC parameters in order to meet the requirements of the target application. The paper presents details of RASoC architecture, the structure of the VHDL model and some experimental results which show the scalability of the soft-core and its costs.

This work presents some results regarding the development of a BIST technique capable of noise figure evaluation. Noise figure is an important parameter in the specification and design of low noise systems, such as communications systems and biomedical instrumentation. A review of published techniques for noise figure evaluation is provided. A new technique aimed to estimate noise figure in a SoC environment is then proposed. The technique is based on the use of a simple and low cost noise generator. Simulation results are provided in order to make an initial evaluation of the feasibility of the proposed approach.

In this work a BIST method for linear analog circuits with very low cost and the smallest possible analog overhead area is presented. The method is suitable to be implemented in the SoC environment, as it allows the reuse of resources already available in the system, and it is essentialy digital. Theoretical background is provided, and experimental results demonstrate the advantages and limits of the proposed approach.

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

In this work, a low cost method to implement an analog BIST scheme for the system on chip environment is presented. The method is based on spectral analysis and it is entirely digital. A simple and low cost 1-bit digitizer is used to capture analog information without the need for an AD converter or oversampling techniques. It also allows partitioning of the analog circuit for test thanks to the low analog area overhead of the digitizer. The mathematical framework and a test example are presented, with practical results illustrating limitations and advantages of the proposed technique.

Presents a new automatic circular decomposition algorithm, which proceeds the separation of connected circular particles, in order to locate their center coordinates and estimate their radii. This new algorithm is based on the following supposition "if you are looking for circles you must assume that all objects in an image are circles, until you can prove they are not". In this work the authors compare this heuristic algorithm with the polygonal approximation based algorithm proposed by Kubo (1988) in their methods and results. Both of them are able to decompose connected blood cells with some differences: the proposed algorithm is implemented in 2 steps, while the polygonal approximation based method is divided in 4 steps and its input parameters present high sensitivity to noise.

We describe our research in the field of application specific instruction-set processors. We first show our approach to design integrated processors, and compare it to other approaches. We focus on the importance of the front-end compiler, which can lead to different optimization strategies. This approach is different from other published works, in the sense that the processor and all its architecture changes to optimize a system are defined only after the code it must execute is known, and not the other way around. We present the results of our system in some case studies, and we conclude by showing some results of a RISC used as a microcontroller.

This paper describes our current research in the field of systems design, trying to reach an Application Specific Integrated System (ASIS). Our target system is based on industry applications. We show the design approach to change presently developed boards using classical microcontrollers, migrating the Cisc architecture to an ASIP architecture. The studied examples show meaningful gains regarding the total area of the processor.

This paper describes some techniques currently under research to explore hardware-software tradeoffs during a system development. We show that the moving of SW operations to HW can be further improved if the source code is modified in order to increase the overall parallelism of the system. We then show the limits of this approach and a new RISC architecture under research to overcome this limitations.>