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Fernand Boéri

dblp:01/1562 · DBLP profile ↗
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11ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 5Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 67% Parallel and multicore computing · 33%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
SIMD
0.011993
OPSILA: A Vector and Parallel Processor · IEEE Trans. Computers 1993
Processor architecture and microarchitecture
vector processing
0.011993
OPSILA: A Vector and Parallel Processor · IEEE Trans. Computers 1993
Compilers and program optimization
vectorization
0.011993
OPSILA: A Vector and Parallel Processor · IEEE Trans. Computers 1993
YearPublicationVenuePosition
1993 Synthesis of dedicated SIMD processors
abstract
In this paper, a synthesis method of dedicated architectures is introduced. Its aim is to produce optimized systems derived from the algorithmic expression of a numerical application. The approach addresses the design of dedicated systems for applications that require high numerical computations. An efficient utilization of hardware resources is achieved through the use of vector processing with an SIMD implementation. The synthesis algorithm realizes simultaneously the design of SIMD structures and the generation of the microcode needed for implementing a software pipelining of operation of the input program.>
Michel Auguin, Fernand Boéri, C. Carrière, G. Menez
ASAP2
1993 Incremental synthesis of application domain specific processors
Michel Auguin, Fernand Boéri, C. Carrière, G. Menez
ICASSP (1)2
1993 OPSILA: A Vector and Parallel Processor
abstract
A multiprocessor machine with two operating modes and simple synchronization mechanisms is discussed. The operating modes are the vector single-instruction multiple-data (SIMD) mode and the parallel single program stream, multiple data stream (SPMD) mode. Synchronizations are reduced to the switching between these two modes. Mixing these two operating modes offers the programmer a comfortable programming environment: vector parallelization is performed by the compiler and the hardware, and, since SPMD parallelization requires mainly the partitioning of the entire set of data, the synchronizations are then often obvious.>
Fernand Boéri, Michel Auguin
IEEE Trans. Computers1
1992 Automatic generation of architectural models for designing dedicated VLIW signal processors
abstract
Some results of the CAPSYS method are presented. It is a new high-level synthesis method whose objective is to benefit from very long induction word (VLIW) compilation and digital signal processor (DSP) synthesis experiences to generalize the automatic processor design process. The major characteristic of this approach is to synthesize architecture in a global way. Instead of a single operative area, the synthesis considers a complete architecture. It permits one to take into account memory throughput, for instance, and, more generally, exchanges with the environment of the synthesized processor. The first part of the method, the generation of architectural models, is emphasized. This procedure furnishes a full spectrum of architectural decompositions (i.e. the number and the type of the functional units) from maximally parallel ones to fully serial ones. In each one, the synthesis algorithm creates an adequacy between the machine and the microcode. Results showing the influence of memory management on synthesized processors are given.>
G. Menez, Michel Auguin, Fernand Boéri, C. Carrière
ICASSP3
1992 A partitioning algorithm for system-level synthesis
abstract
The partitioning/scheduling/allocation algorithm developed for the CAPSYS method is presented. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizable knowledge-pool from the wider field of parallel processors, VLIW compiler design and high-level synthesis. Emphasis is placed on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. The proposed solution implements a software/hardware approach based on the list-scheduling heuristic.>
G. Menez, Michel Auguin, Fernand Boéri, C. Carrière
ICCAD3
1992 A comparison study of minimization methods of unit interconnection in VLIW processors
C. Carrière, Michel Auguin, Fernand Boéri, G. Menez
Microprocess. Microprogramming3
1990 From program to hardware: A parallel architecture compiler
Michel Auguin, Fernand Boéri, C. Carrière, G. Menez
Microprocessing and Microprogramming2
1988 Image processing on a SIMD/SPMD architecture: OPSILA
abstract
OPSILA, is a description given of a general-purpose parallel architecture with two different forms of parallelism: the well-known SIMD (single-instruction, multiple data shown), a synchronous form of parallelism; and SPMD (single program, multiple data stream), which is an asynchronous mode. It is shown that OPSILA is efficient for a wide variety of image algorithms including low and high level processing. The efficiency of OPSILA is demonstrated for the low-level algorithms, through the implementation of a set of typical operations: local (convolution), global (histogram), and geometric corrections.>
P. Duclos, Fernand Boéri, Michel Auguin, Gérard Giraudon
ICPR2
1987 Experience using a SIMD/SPMD multiprocessor architecture
Michel Auguin, Fernand Boéri, J. P. Dalban, A. Vincent-Carrefour
Microprocess. Microprogramming2
1982 Efficient multiprocessor architecture for digital signal processing
abstract
There is a continuing pressure of better processing performances in numerical signal processing. Effective utilization of LSI semiconductor technology allows the consideration of multiprocessor architectures. The problem of interconnecting the components of the architecture arises. In this paper we describe a control algorithm of the Benes interconnection network in a asynchronous multiprocessor system. A simulation study of the timeshared bus, of the omega network, of the Benes network and of the crossbar network gives a comparison of performances.
Michel Auguin, Fernand Boéri
ICASSP2
1979 Optimum quantizer algorithm for real-time block quantizing
abstract
This paper describes an algorithm which allows to find out the M-output level quantizer characteristics minimizing the distortion with respect to both the Mean-Squared-Error (MSE) and Mean-Absolute-Error (MAE) criterions. This algorithm can be used with any kind of signal amplitude distributions ranging from analytical probability density functions (pdf) to experimental 'density functions. In the particular case of known pdf like uniform, Gaussian, Laplacian and Gamma densities, it gives results which agree or are better than those previously published /2,4,5,6/. The same type of algorithmic procedure may also be used for block-of-samples quantization; in this case the statistics average must be replaced by the time average. In addition, the simplicity of the proposed algorithm allows to envisage a real-time, microprocessor based, block adaptive quantizer implementation in which the quantizer parameters are periodically updated and transmitted with each data block. This technique can be used, for instance, to optimally quantize the speech coding parameters derived from the low bit rates speech compression algorithm as described in [7].
Jean E. Menez, Fernand Boéri, Daniel J. Esteban
ICASSP2