The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates.>

Routing tables for communication networks can be designed using many different approaches, including table lookup, content-addressable memory (CAM), hashing, and tries. The authors compare these approaches in the context of custom VLSI implementation. For tables with a small number of entries and a large address space, CAMs can be very cost effective. If only RAM is available, it is shown that tries, of which simple table lookup is a special case, provide a useful architecture. Also considered is a new variation, table partitioning, which constitutes a useful compromise between the conventional CAM and a trie.>