With the maturity of CMOS technologies and their use in low-voltage analog applications, the accuracy of SPICE models is very important. Here, an extremely accurate yet simple form of the charge-sheet model is developed using a symmetric polynomial interpolation of the charge in the channel. This formulation of the drain current retains the same simplicity of the industry-standard surface potential MOSFET models based on the symmetric linearization method (SLM). But, unlike the SLM, it is developed without requiring the linearization of the charge in the channel, hence, the asymmetries and the nonlinearity are accurately accounted for. The model, although more accurate, has the same computational efficiency and easy implementation of the SLM. Finally, the equations of the currents and terminal charges can be worked out to have the same mathematical form as the SLM.

In this paper, we present two charge pump architectures for nonvolatile memories with dynamic biasing of the gate and the body voltages. By controlling the gate and the body voltage of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the following with a negligible voltage drop and large conductivity. The charge pumps were fabricated in the ST 130-nm digital standard CMOS technology. Compared to conventional charge pumps, larger output voltage and better power efficiency are achieved still retaining a simple two-phase clocking scheme. Measurements performed on four-stage and eight-stage charge pumps are provided.

High-resolution radars require the transmission and reception of extremely high-bandwidth pulses. The generation of such pulses is a challenging task, especially for low power portable applications. In this paper we present a new approach to face this problem. The proposed approach uses a standard negative impedance LC oscillator to generate fully-differential pulses in the 6 to 8GHz frequency range. This circuit does not require pulse-shape filtering, leading to a high power efficiency of the generation process. It can also be easily modified to generate quadrature pulses. It can be used both in ultra-wideband transmitters and correlation receivers, allowing for the implementation of quadrature modulation schemes.

A new charge pump circuit is presented: it is based on PMOS pass transistors with dynamic control of the gate and body voltages. By controlling the gate and the bulk of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Compared to conventional charge pumps, it exhibits a larger output voltage and better power efficiency still retaining a simple two-phase clocking scheme. The architecture is based on low-voltage transistors and the voltage drop among the device terminals does not exceed the supply voltage. Measurements performed on a 4-stage charge pump, fabricated exploiting a ST 130nm CMOS process, are provided.

This paper presents the successful design of a CMOS operational amplifier with enhanced immunity to electromagnetic interferences. Thanks to its strongly symmetrical topology, the amplifier exhibits an intrinsic robustness to interferences arising from a wide class of sources. Such a scheme, for the first time in the authors' knowledge, proves the effectiveness of symmetrical topologies to minimize the effects of electromagnetic interferences in operational amplifiers. The amplifier architecture is based on 2 identical stages: 2 fully differential source cross-coupled amplifiers with active loads. The circuit was fabricated in a 0.8 /spl mu/m n-well CMOS technology (AMS CYE process). Experimental results, in terms of EMI immunity, are presented and compared with a commercial amplifier. They show a low susceptibility to EMI conveyed both to the input and the power pins. The EMI effects on the proposed amplifier are reduced by more than one order of magnitude, compared to a commercial amplifier. Furthermore the amplifier overall measured performances are provided along with the corresponding simulation results.

The transport model in semiconductors is examined in the case where the effect of distributed gap states is significant like, e.g., in thin-film transistors. A solution scheme is derived for the two additional continuity equations accounting for the trapped charge such that, without loss of generality, the efficiency of the traditional method implemented in the existing device-analysis codes is kept. The dynamic effect of the trapped charge is then examined in the ac operation of a realistic thin-film device, including the analysis of the interelectrode capacitances.