Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from SIGIR 2026 / reviewers in the wild / expert

Jui Lin Yen

dblp:02/3323 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Coding theory · 100%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Hardware accelerators and domain-specific architectures · 35% Storage systems · 22% Processor architecture and microarchitecture · 21%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Coding theory
error-correcting codes		 0.011992
An Error-Correction Scheme for a Helical-Scan Magnetic Data Storage System · IEEE J. Sel. Areas Commun. 1992
Coding theory › error-correcting codes
reed-solomon codes		 0.011992
An Error-Correction Scheme for a Helical-Scan Magnetic Data Storage System · IEEE J. Sel. Areas Commun. 1992
Storage systems
magnetic storage		 0.011992
An Error-Correction Scheme for a Helical-Scan Magnetic Data Storage System · IEEE J. Sel. Areas Commun. 1992
Reconfigurable computing and FPGAs › FPGA arithmetic
distributed arithmetic		 0.011983
A Pipelined Distributed Arithmetic PFFT Processor · IEEE Trans. Computers 1983
Hardware accelerators and domain-specific architectures › signal processing accelerator
FFT accelerator		 0.011983
A Pipelined Distributed Arithmetic PFFT Processor · IEEE Trans. Computers 1983
Processor architecture and microarchitecture › computer arithmetic
pipelined arithmetic		 0.011983
A Pipelined Distributed Arithmetic PFFT Processor · IEEE Trans. Computers 1983
Hardware accelerators and domain-specific architectures › signal processing accelerator
FFT processor		 0.011975
A Parallel Radix-4 Fast Fourier Transform Computer · IEEE Trans. Computers 1975
Hardware accelerators and domain-specific architectures
signal processing accelerator		 0.011975
A Parallel Radix-4 Fast Fourier Transform Computer · IEEE Trans. Computers 1975

Methods — techniques the papers use, named apart from their topics

interleaving · 0.0error statistics · 0.0radix-4 FFT · 0.0
YearPublicationVenuePosition
1992 An Error-Correction Scheme for a Helical-Scan Magnetic Data Storage System
abstract
An error-correction scheme for a helical-scan magnetic recording system is presented. The system consists of a commercial VHS video cassette recorder with the front-end electronics adapted for high-speed digital recording. Error statistics have been collected and show a bursty error recording channel both within each track and from track-to-track. The proposed error-correction scheme uses interleaved Reed-Solomon codes. The interleaving function consists of a two-level interleaver performing track interleaving and byte interleaving. An efficient interleaving implementation is presented.>
Christopher R. Hawthorne, Elvino S. Sousa, Alberto Leon-Garcia, Jui Lin Yen
 IEEE J. Sel. Areas Commun.4
1983 A Pipelined Distributed Arithmetic PFFT Processor
abstract
Previous experience in implementing the prime factor Fourier transform (PFFT) showed that it was much more difficult to do than the FF because of its complicated structure. In most FFT implementations the "butterfly" structure is the basic arithmetic element implemented. It is much simpler than the equivalent PFFT unit.
Paul Chow, Zvonko G. Vranesic, Jui Lin Yen
 IEEE Trans. Computers3
1975 A Parallel Radix-4 Fast Fourier Transform Computer
abstract
The organization and functional design of a parallel radix-4 fast Fourier transform (FFT) computer for real-time signal processing of wide-band signals is introduced.
Michael J. Corinthios, Kenneth C. Smith, Jui Lin Yen
 IEEE Trans. Computers3