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R. M. Brown

dblp:03/1986 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 66% Integrated circuit design · 29% Storage systems · 4%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture		 0.011964
The CSX-l Computer · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design › sequential circuit design
binary counter		 0.011955
Some Notes on Logical Binary Counters · IRE Trans. Electron. Comput. 1955
Integrated circuit design
digital logic		 0.011955
Some Notes on Logical Binary Counters · IRE Trans. Electron. Comput. 1955
Processor architecture and microarchitecture › register file
register file design		 0.011964
The CSX-l Computer · IEEE Trans. Electron. Comput. 1964
Storage systems › data representation › data encoding
gray code		 0.011955
Some Notes on Logical Binary Counters · IRE Trans. Electron. Comput. 1955

Methods — techniques the papers use, named apart from their topics

instruction repertoire design · 0.0
YearPublicationVenuePosition
1988 Handprinted symbol recognition system
R. M. Brown, T. H. Fay, C. L. Walker
 Pattern Recognit.1
1964 The CSX-l Computer
abstract
A brief description of the logical structure and the instruction repertoire of a short word length (16 bits) computer is given. The unorthodox features which are discussed are 1) a variable-length addressing procedure, 2) a common multi-accumulator and index register structure, and 3) the identical processing of data and addresses.
R. M. Brown, Richard D. Jenks, J. E. Stifle, R. L. Trogdon
 IEEE Trans. Electron. Comput.1
1955 Some Notes on Logical Binary Counters
abstract
The properties of binary counters which utilize non-transient storage elements for the count information are presented. The four possible sets of logical connections between the two storage elements necessary for each stage are described. The binary numbers represented in the storage elements are shown to be the actual count in one set of elements and in the other set a Gray code representation of twice the actual count. Examples of bi-directional counters are given.
R. M. Brown
 IRE Trans. Electron. Comput.1