The integration of the Wireless Sensor Networks (WSNs) technology in the Internet world is one of the biggest challenges to enable the Internet of Things (IoT) vision. In order to really benefit of such kind of integration the IPv6 addressing method and communication protocols adopted in the IoT must be modified to match the WSNs scenario. This adaptation has been standardized with the name of IPv6 over Low power Wireless Personal Area Networks (6LoWPAN). In this paper the first adaptation of the SPEED geographic routing algorithm in a 6LoWPAN scenario is presented and its experimental validation in a real testbed is shown as compared with the AODVprotocol. Avoiding route creation time and showing reduced memory occupation, load balancing and flow shaping properties SPEED is an effective solution to support packet routing in 6LoW-PAN networks.

A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network-on-chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous processes inside the eFPGAs or locally accelerated by the usage of dedicated microprocessor coprocessors. Each eFPGA on the system can be independently programmed and share logic with the others eFPGAs by intra-communication channels. The architecture is highly scalable since the eFPGA number can be controlled and the reconfigurable platform communication channels are based on a configurable NoC. The silicon area required by the system is 26mm2 in a 90 nm CMOS process. 10x speed ups have been measured on a MP3 playler mapping example.

A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.