This paper presents a comprehensive analysis of the impact of CNT fabrication imperfections on the performance of multichannel Carbon Nanotube FET (CNFET) -based devices. In particular, we introduce a methodology for stochastically estimating the impact of spacing between adjacent tubes and the impact of its variation. This enables accurate prediction of the reduction in drive current due to the removal of tubes, the increase in spacing between adjacent tubes, and variations in tube diameter and spacing. In multichannel CNFETs, when the number of channels (CNTs) is greater than eight, our experiments show that variations in tube diameter and inter-tube spacing result in less than 8% performance variation. Monte Carlo simulation results, however, show that the removal of tubes increases variation in IONfrom 13% to 26% due to larger variation in inter-tube spacing. The presented realistic analysis and the proposed methodology can be extremely useful in variation-tolerant CNFET-based circuit design.

Carbon Nanotube FET (CNT-FET) is a promising candidate for the construction of future integrated circuits. However the presence of metallic tubes negatively affects delay, leakage power, and yield of such circuits. In this paper we compare four different CNT-FET configurations - shared tube, parallel tubes, transistor stacking, and tube stacking. In the presence of 10% metallic tubes, stacking configurations have potential to as much as double the yield for 4.1-4.4X delay penalty under iso-input capacitance and 3-7X lower leakage power compared to the non-stacked configurations. Analytical model and Monte Carlo simulation results for various logic gate sizes clearly indicate that an architecture that utilizes an appropriate combination of all four configurations is required to enable a better trade-off between delay, leakage power, and yield in the presence of metallic tubes.

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30 of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.

Measurements on a prototype chip, implemented in a 150nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that 2X reduction in current variation is achievable across extremes of both process and temperature.

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.

As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual Vt partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict sub-threshold leakage power of such systems. In this paper, we present a sub-threshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18 mm CMOS confirms that the mean error of the model to be 4%. Comparisons of this model to two other existing models that do not take within-die threshold voltage variation into account are also presented.

This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

Examines the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18 /spl mu/m single-V/sub t/ and 0.13 /spl mu/m dual-V/sub t/ logic process technologies. Investigates its dependencies on channel length, target V/sub t/, temperature and technology generation. Shows that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V/sub t/ at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V/sub t/ values are low. A model is given that relates different transistor leakage components to full-chip leakage current, and is validated through test-chip measurements across a range of RBB values.

Article Share on Scaling of stack effect and its application for leakage reduction Authors: Siva Narendra Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile , Vivek De Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile , Dimitri Antoniadis Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MAView Profile , Anantha Chandrakasan Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MAView Profile , Shekhar Borkar Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 195–200https://doi.org/10.1145/383082.383132Online:06 August 2001Publication History 140citation1,436DownloadsMetricsTotal Citations140Total Downloads1,436Last 12 Months24Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors Share on Authors: James Tschanz Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Siva Narendra Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Zhanping Chen Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Shekhar Borkar Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Manoj Sachdev Department of ECE, University of Waterloo, Canada Department of ECE, University of Waterloo, CanadaView Profile , Vivek De Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 147–152https://doi.org/10.1145/383082.383121Online:06 August 2001Publication History 39citation804DownloadsMetricsTotal Citations39Total Downloads804Last 12 Months50Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We demonstrate that, there is an optimum reverse body bias, unique to any technology generation, that minimizes the standby leakage power consumption of an IC design implemented in that technology.We also show: (1) the optimum reverse body bias value reduces by -2X per technology generation, and (2) the maximum achievable leakage power reduction by reverse body biasing diminishes by -4X per generation under constant field technology scaling scenario.Optimum point occurs as a result of reduction in subthreshold leakage and an increase in junction band-to-band tunneling leakage with applied reverse bias.Therefore, new junction engineering techniques to reduce the bulk band-toband tunneling leakage current component across the junction are needed to preserve the effectiveness of reverse body biasing for standby leakage control in future technologies.

Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks. This algorithm can be applied at all levels of a circuit hierarchy, where the internal blocks can represent transistors, cells within an array, or entire modules. This methodology will give an upper bound for the sleep transistor size required to meet any performance constraint.