The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rdparty analog/mixed-signal IP? Or is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table would analog designers of Bob Pease's generation sit: the IP provider or the chip company? Or are their skills redundant for the 65 nm analog design challenges?

A new fully differential multiple differences instrumentation amplifier (MDIA) with voltage controllable gain is presented. This new instrumentation amplifier (IA) topology is based on a new fully differential multiple differences amplifier cell or FDMDA. Based on this fully differential analogue cell, a new fully differential multiple input instrumentation amplifier with variable gain is proposed. This new IA topology offers three differential inputs with a voltage-controlled differential linear transconductor in the amplifier's feedback loop to control its differential voltage gain. This gain can be continuously tuned within a gain decade range by an analogue controlling voltage V/sub g/. Two equal feedback resistors R/sub g/ set the gain decade variation range, allowing gains between 15 and 60 dB. Simulation results of the developed structure are presented and discussed and some applications of this multiple input amplifier are referred, namely in the processing of several differential voltage analogue sensor signals.

I/Q mismatches are common in radio receivers, which apply quadrature demodulation schemes. Numerous methods have been developed to estimate and correct these errors for narrow-band signals. In this paper a wideband correction method is introduced. First the frequency-dependent I/Q mismatches are estimated by local test signal injection. Then a digital filter is constructed to correct them. With this method, a significant amount of image rejection over a broad bandwidth can be achieved as demonstrated by high-level simulations.

This paper proposes a 4-fold multistage Switched-Capacitor (SC) interpolation filter with 5 MHz passband and 54 MHz output sampling rate for NTSC/PAL digital video signal processing systems. The circuit implements an impulse sampled halfband interpolation with 23- and 7-tap FIR filtering in 1stand 2nd-stage respectively for achieving a linear-phase response. A novel area-efficient technique including symmetrical-coefficient-sharing and spread-reduction is proposed in this transversal SC circuit embedding minimized mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation. This filter is designed with optimized speed of the analog components in 0.35 /spl mu/m CMOS technology and expected to consume about 2 mm/sup 2/ active area and 90 mW at 3.0 V supply.

Systems containing both analog and digital functions have been investigated with the purpose of realizing mixed-signal integrated circuits with higher levels of functionality and integration. In most cases, such mixed-signal systems are inherently multirate because of the different sampling rates employed at various stages of the system. The multirate concepts have been used for traditional applications, such as subband coding and narrowband filter design. Some unconventional applications of multirate signal processing are also emerging, both for converting between analog samples and digital words, and for realizing processing functions in an easier and more economical way than would be possible using purely digital or analog techniques. This paper reviews fundamental multirate concepts, discusses some developments in this area of integrated multirate analog-digital systems, and outlines some possible future directions for research and application.

A new, algorithm-driven methodology is introduced for the synthesis of data conversion systems. It employs a combination of symbolic signal flow graph techniques to generate a canonical representation of the algorithm description, together with pattern recognition techniques, to determine the appropriate functional building blocks for the converter architecture and knowledge-based rules to instantiate such building blocks by electrical subcircuits. By allowing the synthesis process to move to higher levels of abstraction the proposed methodology provides a computer-based framework for the systematic and uniform treatment of various types of conversion systems, including the search for new conversion algorithms and/or new implementation architectures.

This paper describes the design, experimental characterization and behavior modeling of a homogeneous set of building blocks necessary to construct in analog hardware feed-forward artificial neural networks. A novel synapse architecture is proposed using a quasi-passive D/A (digital-to-analog) converter followed by a four-quadrant analog-digital multiplier, its main advantages are 1) increased signal input range; 2) improved area/weight resolution ratio; 3) on-chip refreshing of the weight value; and 4) serial loading the weight bits. The neurons are built using MOS (metal-oxide semiconductor) transistors operating in the saturation region and exploiting the inherent quadratic characteristics. Experimental results obtained from a demonstration prototype chip realized in a 1.2 mum double-poly, double-metal CMOS (complimentary MOS) technology show good agreement with the design specifications. A simple application of the proposed building blocks is illustrated based on the mixed-signal simulation of the corresponding behavior models constructed from the experimental characterization data.

A knowledge-based approach for the automatic symbolic characterization of SC circuits is presented considering the effect of non-ideal finite gain operational amplifiers. This includes conventional filtering structures above second order as well as generalized multirate structures with switching waveforms performing multiple sampling-discharge operations per clock period.

The optimization of high-speed pipelined ADCs employing self-calibration techniques to achieve high-resolution is discussed. Different assignments of resolution-per-stage are explored taking into account such physical limitations as thermal noise and matching accuracy in the capacitor arrays. The impact of the selected pipeline configuration in the self-calibration requirements as well as in the feasibility of the active components is analyzed. A design example is presented to demonstrate the relevant conclusions.

New techniques for realizing CMOS logarithmic analog-to-digital (A/D) converters employing pipeline and algorithmic architectures are described. This is achieved by replacing the operations of subtraction/addition and multiplications in their linear counterparts by simple scaling operations in the logarithmic domain. Logarithmic pipeline A/D converters are more appropriate for high-frequency applications whereas logarithmic algorithmic A/D converters are particularly suitable for compact, low-cost designs. Examples are given to illustrate the proposed techniques.

Signal flow graphs (SFG's) are a powerful technique to analyze switched-capacitor (SC) circuits in a way that provides in-depth information about their operation and direct access to the corresponding symbolic z-transfer functions. Due to lengthy and error-prone symbolic manipulations this is manually manageable for simple first- or second-order circuits, but becomes unpractical for manipulating higher-order circuits which can not be decomposed into first- and second-order ones. Hence, there is an important need to provide designers with a computer-aided tool for the SFG symbolic analysis of a broad class of SC filtering networks, as described in this paper. Rule-based techniques are employed to capture from arbitrary circuit schematic and timing diagrams the corresponding symbolic SFG leading to the automatic generation of the associated z-transfer function. Symbols can then be instantiated to numerical values to obtain measurable data on a variety of performance indicators such as total capacitor area and capacitance spread as well as the resulting nominal frequency response and its variability against component errors. This is illustrated considering a variety of examples of SC filtering networks including, besides the more traditional filters, both finite and infinite impulse response decimators.>

We present in this paper two high-speed current comparators which are fully compatible with digital CMOS technology, occupy little silicon area and dissipate low power. Experimental results are presented to demonstrate the performance of these circuits.>

We describe a high-precision calibrating system where the code error voltages of a low-resolution binary-weighted capacitor-array DAC, measured against the precise code voltage references generated by a single-capacitor pulse-counting DAC, are digitized and corrected using a small subbinary-weighted capacitor-array. Computer simulation results are given to demonstrate the operation of the proposed system and the benefits that can be gained by employing gain- and offset-compensated stages.>

This paper describes digitally-controlled analogue signal processing and conversion techniques based on a logarithmic current attenuator building block fully compatible with digital CMOS technology, and whose accuracy depends solely on the matching of transistors. Application examples given to illustrate the proposed techniques include logarithmic analogue-to-digital and digital-to-analogue conversion and automatic gain control, functions commonly used in various communications and instrumentations applications.>

A methodology for automatic generation of data conversion topologies from algorithms is described. Based on the symbolical manipulation of the corresponding analog-digital graph representation, the analog and digital graph partitions are first translated into a set of functional building blocks and a state machine, respectively. The final conversion system topology is determined by instantiating the identified functional blocks with the appropriate circuits available in a library and generating the corresponding sizing rules.>

Switched-current (SI) circuits are proposed for realizing decimation and interpolation filtering functions with both finite impulse response (FIR) and infinite impulse response (IIR). An efficient switching is discussed which improves the performance of the proposed SI multirate circuits affected by settling time errors of the memory cells.>