This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.

Semiconductor nanowires have attracted considerable attention during the last decade and are considered as an alternative path to extend the road for scaled semiconductor devices. The interest is motivated by the improved electrostatic control in the cylindrical geometry and the possibility to utilize heterostructures in transistor design. Currently, nanowire transistors have been realized both in III-Vs and in group IV materials employing top-down as well as bottom-up technologies. In this review, we give an overview of the field and, in particular, we summarize state-of-the-art for III-V nanowire devices. It is demonstrated that the growth and processing technologies are maturing and that devices with good transistor characteristics are being fabricated by a combined bottom-up and top-down approach. Also, the first radio-frequency (RF)-implementations are reviewed and discussed.