Thermal management becomes a huge challenge for modern IC designers, especially when chips go 3-D. Vertical slit field-effect transistor (VeSFET) technology provides an alternative thermal-friendly design choice. VeSFET-based chips not only have a much lower power density but also a better vertical thermal conductivity than their CMOS counterparts. For a VeSFET chip with ten stacked dies, the temperature increase is only 30% of that for CMOS-based chip. Assuming the same scaling trend for CMOS and VeSFET, VeSFET 3-D chips can postpone the appearance of dark silicon by three technology nodes compared with CMOS implementations. For VeSFET-based designs, different topologies of transistor arrays may result in different thermal behaviors. We perform thermal characterization of two-transistor array topologies.

In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases-chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We compare the designs implemented with a commercial low power CMOS library and corresponding VeSFET libraries. VeSFET-based designs demonstrate significant power reduction as compared to the CMOS-based designs at the same performance.

Medium volume VeSFET-based ASICs can fill the gap between high cost microprocessors and low performance FPGAs. Circuits can be customized onto pre-manufactured VeSFET canvases by properly designed interconnects. In this paper, we propose chain canvases, a family of VeSFET canvases for which CMOS-oriented EDA tools can be easily adapted. Footprint area, wire length, via usage, performance and power are compared between chain canvas- and basic canvas-mapped benchmarks. Experimental results show that chain canvas-mapped circuits outperform those mapped to basic canvases.

In this presentation feasibility of Vertical Slit Transistor Based Integrated Circuits (VeSTICs) is evaluated. VeSTICs paradigm has been conceived as a response to the rapidly growing complexity of the traditional CMOS-based approach to challenges posed by the nano-scale era. This paradigm has been constructed using notion of a strict layout regularity imposed on VeSTIC layouts. The central element of the proposed vision is new junction-less Vertical Slit Field Effect Transistor (VeSFET) with twin independent gates. It is expected that VeSTICs will enable much denser, much easier to design, test and manufacure ICs, as well as, will be 3D-extendable and OPC-free. (More exhaustive description of this paradigm one can find at: http://vestics.org).

In this paper, we study circuits implemented using high-density arrays composed of vertical slit field effect transistors. This layout style could dramatically increase transistor density and, therefore, reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks, pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.

In this paper, we study circuits implemented using high-density arrays composed of Vertical Slit Field Effect Transistors. This layout style could dramatically increase transistor density and therefore reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit-level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.

Sub-wavelength lithography uses light waves that have a longer wavelength than the feature size that is being printed. Image distortions are an inevitable consequence of this situation, even after resolution enhancement techniques have been applied. This paper studies in detail how the image distortion in a fabricated IC can impact test and critical-area yield loss. Particularly, lithography simulation is performed on the desired pattern to predict the printed (distorted) pattern. The impact on critical-area yield loss is studied using both the desired pattern and the printed pattern. Similarly, the impact on test is studied using inductive fault analysis on both the desired pattern and the printed pattern. Even under the assumption of the best process conditions, experiment results indicate that the difference in misdirected test effort can be as large as 8.0% and the difference in the critical-area yield calculations is about 3.4% for a large design. The more accurate analysis requires a runtime increase of 5X on average.

In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate, transistor-array-based layout. Interconnects on all metal layers are strictly parallel and can be manufactured by an optical proximity correction free process. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced.

Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. So far only small building blocks have been presented. This paper investigates for the first time the use of independent double gate transistors in 16 bit ripple carry and parallel prefix adders. New adder circuits and the trade-off between area reduction, delay and power consumption are presented. Area and transistor count reduction by one third can be achieved.

In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate transistor-array-based layout. Interconnects on all metal layers are uni-directional and can be manufactured by an OPC-free process [4]. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced.

In this presentation new, unorthodox (i.e. ITRS incompatible), IC design/manufacturing paradigm is proposed. This paradigm has been conceived as a response to the rapidly growing complexity and increasing number of stumbling blocks posed by the nano-scale IC era. It has been constructed using notion of a strict layout regularity imposed on IC layout. Such restriction is seen as a remedy for dramatic increase of litho cost and complexity expected to be major issues for the below-32-nm products. Such regularity has been discussed in the past for IC interconnects. Focus of this talk is on active devices. The central element of the proposed vision is Vertical Slit Field Effect Transistor (VeSFET). It is shown that Vertical Slit Transistor based integrated circuits (VeSTICs) may enable much denser, much easier to design, test and manufacure, as well as, easily 3D-extendable and OPC-free ICs. The proposed paradigm has been developed assuming that it must reuse CMOS-based desig/manufdacturing infrasrtuctur and expertise that does exist today.

Moore’s law has been a foundation of modern electronics, sustained primarily by scaling. But can this continue despite the serious problems of litho, variability, device physics, and cost? This panel looks at several possibilities. Perhaps Moore’s law will muddle through, as it has so far, with a combination of tools, process, and design. But even if technically possible, Moore’s law is in practice driven by economics, and economics might turn against further scaling. Also, we’ve all seen how performance of single cores has topped out, despite scaling. Might this be a fundamental problem with planar technologies, prompting the need to go 3-D to get further performance increases? Or might CMOS itself give way to other technologies, allowing Moore’s law yet another respite? Compare and contrast for yourself these four very different visions of the future of your job, your industry, and your personal gadgets.

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.

Advancements in IC manufacturing technologies allow for building very large devices with billions of transistors and with complex interactions between them encapsulated in a huge number of design rules. To ease designers' efforts in dealing with electrical and manufacturing problems, regular layout style seems to be a viable option. In this paper we analyze regular layouts in an IC manufacturability context and define their desired properties. We introduce the OPC-free IC design methodology and study properties of cells designed for this layout style that have various degrees of regularity.

Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used to estimate these distributions. In this paper, we propose a strategy to accurately estimate DDSDs for shorts in metal layers using production IC test results

The excessive interconnection delay and fast increasing development cost, as well as complexity of the single-chip integration of different technologies, are likely to become the major stumbling blocks for the success of monolithic system-on-chips. To address the above problems, this paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2.5-D) integration scheme. Using this scheme, a VLSI system is implemented as a three-dimensional stacking of monolithic chips. A cost analysis framework was developed to justify the 2.5-D integration scheme from an economic point of view. Enabling technologies for the new integration scheme are also reviewed.

Diagnosis algorithms for integrated circuits (ICs) are typically developed and evaluated using a limited number of logic-level models of defect behaviors. However, it is well-known that real IC defects exhibit behavior well outside these models. Consequently, the utility of IC diagnosis methodologies may be uncertain. A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects. Specifically, we have proposed a simple yet powerful strategy using a small circuit and a set of bounded deformations (i.e., defects) for measuring the effectiveness of diagnosis techniques. Evaluation of several simple and commercial diagnosis algorithms indicates that this form of diagnosis benchmarking is viable.

Excessive on-chip wire length and fast increasing fabrication cost have been the main factors impairing the effectiveness of monolithic system-on-chip. We investigate a die stacking based system integration strategy (2.5D system integration) to address these problems. The new scheme is design-tools-enabled rather than technology-driven. We developed a layout design framework, which is able to floorplan, place and route a VLSI design into stacked chips. Our results show that this new scheme has a potential to outperform its monolithic equivalent.

Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.

We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for voltage tests. Due to the implicit enumeration of bridge sites, no layout extraction or precomputed stuck-at fault dictionaries are required. The bridge identification is easily refined using additional test pattern results when necessary. We present results for benchmark circuits and four common fault models (wired-AND, wired-OR, dominant, and composite), evaluate the diagnosis against other possible fault types, and summarize the quality of our results. 1.

Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more difficult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself. At the same time, key diagnostic tasks that include defect localization are still solved using primitive models of the IC's defects. This paper explores the use of "fault tuples" in diagnosis. Fault tuples can accurately mimic the complex misbehavior of DSM ICs at the logic level, enabling practical diagnosis of large circuits. Initial assessment of the use of fault tuples in diagnosis is performed based on a case study involving one specific category of polysilicon spot defects. Obtained results indicate that fault tuples may enhance diagnosis significantly.

Nanometer IC technologies are on the horizon. They promise a lot. They will cost a lot as well. Therefore, we need to ask today: How may the billions of dollars, which we will need to spend on nanometer-fablines, affect IC design domain? This paper attempts to address the above question by analyzing design-manufacturing interface. The partial answer is derived from a simple transistor cost model proposed in the body of the paper.

Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing chip size. To address this problem instead of placing all systems components in one layer (i.e. in 2-D space) one can use a stack of single layer monolithic ICs (called here a 2.5-D integrated IC). To assess the potential benefits of such a 2.5-D integration schema this paper compares wire length distributions, obtained for 2-D and 2.5-D implementations of benchmark circuits. In the assessment two newly developed floorplanning and placement tools were used. Significant reductions in both total wirelength and worst-case wirelength was observed for the systems implemented as 2.5-D ICs.

This paper introduces a method that enables the diagnosis of embedded memories via test response compression and automatic bitmap recognition. The proposed method has been tested via simulation with various memory specifications, fail patterns and test algorithms; it has also been implemented in a 0.18 /spl mu/m CMOS test chip.

This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of memories with various specifications, fail patterns and test algorithms. The proposed method has been implemented in 0.18 /spl mu/ CMOS IC.

As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation.

This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC's which suggest that the diversity of patterns does not significantly increase with increasing chip size.

This paper describes an algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of industrial size ICs with non-Manhattan geometry. Illustrative examples of the proposed algorithm, implemented by using design rule checker operations, are presented. It is shown that the extraction of the critical area for realistic size VLSI circuits designs can be done in an acceptable time.

Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/manufacturability tradeoff analysis. The basis for such an analysis, in which the relationship between a product's clock frequency and wafer productivity is modeled, is described in detail. New applied yield models are discussed as well.

This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important tasks is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well.

For pt. I see ibid., p. 550-6 (1998). This paper illustrates via examples problems at the design-manufacturing interface that exist in the IC industry today, and the ability of the YAN/PODEMA framework in solving these problems. The need for further development of the framework is also emphasized.

We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the information stored within the pattern and position of the pattern instance. We also show preliminary results of analysis of the state-of-the-art ICs which suggest that the diversity of patterns does not significantly increase with the increase of chip size.

Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Application of current signatures in die selection and defect diagnosis is discussed as well.

This paper investigates the important question of whether or not Iddq-only fails are "bad" and should be rejected during testing. The analysis is based on the Sematech experiment results and employs current signature-based testing.

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.

Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Application of current signatures in die selection and defect diagnosis is discussed as well.

The SEMATECH "Test Methods Evaluation" study, Project Number S-121, is an experiment to determine the relative merits of several test methodologies often used by SEMATECH member companies and other IC manufacturers. Conclusions drawn from the experiment thus far have indicated that each test methodology uniquely detects defects. This experimentation and analysis would not have been possible outside a consortium setting such as SEMATECH. Its conclusions may affect other major segments of the industry, including ATE manufacturers, CAD vendors, and academia. This paper gives a brief overview of the experiment and summarizes its findings.

Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region.

Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG's), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a predetermined number of arbitrary input vectors. We show that this result holds for test sets derived based on structural and functional methods, and based on the conventional and multiple observation time testing strategies. Furthermore, we derive the conditions under which synchronizing sequences are preserved under retiming. We show that a structural synchronizing sequence for a circuit drives any of its corresponding retimed circuits to an equivalent state. In addition, we show that functional synchronizing sequences are preserved under retiming by adding a prefix sequence of a predetermined number of arbitrary input vectors. The impact of retiming on ATPG complexity and test-set preservation under retiming suggest a new approach for enhancing the performance of structural, sequential ATPG's. Experimental results show that high fault coverages can be achieved on high-performance circuits optimized by retiming with much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

A sound IC design methodology must be supported by adequate manufacturability assessment tools. These tools should assist a designer in predicting IC manufacturing cost in as early a design stage as possible. In this paper a yield model is proposed that takes as input a standard cell netlist and produces as output a yield estimate without performing placement and routing. This yield model has been successfully used to predict the interconnect yield of standard cell designs that were implemented with two place and route tools. The proposed yield model can be used as a crucial component in the objective function of a circuit synthesis tool as well as in technology mapping optimization.

Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.

This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be used to identify hard-to-test portions of designs, and therefore to devise more cost-effective DFT techniques.

While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. Without major changes in the CMOS technology, it has been shown that the scaling of devices has significant impact on the effectiveness of Iddq testing. The sensitivity of Iddq testing to individual device parameters is studied. It is explained how Iddq testing becomes increasingly ineffective in the scaled product with respect to most parameters and can be improved with others.

In this paper we demonstrate that performing I/sub DDQ/ testing against a single threshold current value does not make sense. In place of the single current threshold we propose the "current signature". A die's current signature takes into account the relative measured level of current on all applied I/sub DDQ/ vectors. Preliminary results of current signature applications are discussed as well.

In this paper we demonstrate an Inductive Contamination Analysis (ICA)-based methodology for complete fault characterization of standard cell libraries. Such a characterization has applications in accurate assessment of defect coverage, contamination diagnosis, gate-level delay characterization and test generation.

The research reported in this paper has been conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation algorithms, which can lead to extremely long test generation times. The retiming transformation is used to create families of circuits which have the same sequential depth and number and length of cycles, but a significantly different percentage of valid states. It was observed for three different sequential test pattern generators that the increase in complexity of test pattern generation is related to a new circuit attribute, termed density of encoding, and not to the sequential depth or number and length of cycles-i.e., those circuit parameters to which the complexity of test pattern generation has traditionally been attributed.

Abstract| Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault eciency attained.In this paper, we show that retiming preserves testability with respect to a single stuck-at fault test set by adding a pre x sequence of a pre-determined number of arbitrary input vectors.Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

This paper proposes a new simulation-based fault modeling methodology. The methodology-an extension of Inductive Fault Analysis-uses the contamination-defect-fault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions. The application of this methodology (called Inductive Contamination Analysis) is demonstrated by development of SRAM fault models.

This paper provides an overview of design/test/CAD silicon cost-related issues.All major factors contributing to the rapid growth of manufacturing costs are explained and a simple cost model is introduced to assess possible impact of cost growth on the VLSI arena.

This paper analyzes the feasibility of MCMs using active silicon substrates with built-in resting circuitry. It identifies the domain of applicability of such MCMs and points to limitations of the "Known Good Die" approach.

Traditionally, the majority of testing methodologies have been based on the application of ever more powerful testers-designed acid fabricated to test ever faster and more complex ICs. Such a product-driven and tester-focused testing paradigm has been on one hand technically successful but on the other hand has fueled a dramatic increase in testing costs. Hence, the question: "is it possible to increase testers' performance maintaining at the same time testing costs on an acceptable level?" seems to be a key in predicting the future of IC testing.

Estimating the reject ratio for integrated circuits is an important problem to a test engineer. Using information about the decrease in reject ratio with increasing test length, the test engineer can estimate the test length necessary to achieve a desired product quality goal. This paper suggests a method for estimation of reject ratio for random testing of combinatorial circuits that takes into account differing individual fault probabilities. The authors also suggest some ways of estimating the fault probabilities. They then demonstrate the method on an example and compare results to previous work.>

A new approach to IC diagnosis, based on realistic defect modelling, has been recently proposed. Algorithms have been devised to generate 'good' diagnostic test sets. In this paper, the authors demonstrate that high levels of diagnostic resolution can be obtained for CMOS random logic, especially when abnormal I/sub DDQ/ current measurements are monitored in addition to circuit output voltages.>

Summary Testing has always been an inherent calmponent of electronics. Therefore it should be viewed as a very successfully evolving field deserving a sizable portion of the credit usually given to design and manufacturing for the spectacular progress of the entire electronics area. Why, then, is it necessary to question and analyze the quality of testing education? Is testing really suffering because inadequate attention has been paid by the academic institution to testing related engineering ancl theoretical problems? The answer for the above question seems to be yes. But the primary reason for this situation should not be attributed to academia alone. Industry also seems to be responsible for the inadequate production of high quality researchers and engineers who can effectively cope with complicated testing issues of modern electronic systems. The essence of the above problem is in the compartmentalization of the testing field, which, while convenient from administration point of view, promotes an inefficiency in communication between the various parties forming the testing community. These communication bottlenecks have led to the formation of contradicting views of the testing field.

The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.

This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.

Summary form only given. It is pointed out that current testing is and will increasingly become attractive as a main technique for testing static CMOS circuits. BIC (built-in current) testing can provide testing qualities achievable with other testing techniques. It is suggested that future testing approaches geared toward high-quality and/or reliability-oriented testing procedures will be formed using a combination of voltage and current testing methodologies.>

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of directly expressing many of the likely CMOS faults, was still able to generate a set of effective test patterns. Current monitoring, however, by virtue of its more accurate model and less stringent detection criterion, was able to generate tests of measurably higher quality. It is concluded that the selection of one technique over the other becomes a cost tradeoff. Current testing produced test patterns that were consistently more effective in detecting bridging faults. This higher quality comes at higher start-up costs aid higher costs per chip design.>

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented.>

Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n).>

The authors proposed the use of functional testing for the extraction of IC manufacturing defect characteristics. It is demonstrated, using an SRAM (static random-access memory) example, that such extraction is feasible if an appropriate methodology for the interpretation of testing results is applied. The methodology allows for the extraction of information about process disturbances and abnormalities causing IC malfunctions. In this methodology the Monte Carlo fault modeling technique, combined with circuit simulation, was applied to build a defect fault vocabulary. The simulation experiment conducted by using this methodology demonstrated that a spectrum of signatures can be created to represent process disturbances. It was also shown that such a spectrum of signatures can be sensitive enough to changes in the defect densities.>

A testing methodology which applies built-in current sensors to detect abnormal currents in the power buses of functional blocks of CMOS ICs is proposed, that significantly improves the quality of VLSI circuit testing. A summary of simulation results and design experiments is presented to demonstrate the feasibility and to illustrate the applicability of the approach. The results suggest that built-in current testing could be a very powerful tool for overcoming basic bottlenecks in VLSI testing, providing very inexpensive testing, high-quality built-in testing, or on-chip concurrent reliability testing for high-quality fault-tolerant systems.>

In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or are not explicitly covered at all. It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open. It is also shown that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults. The analysis of the behavior of a CMOS transistor with a floating gate indicates it acts as a weakly 'on' active load, and therefore an open gate cannot be detected by stuck-fault testing but could be detected by monitoring the static current through the power buses.>

Built-in current (BIC) testing involves the monitoring of power bus currents in a VLSI circuit, as a means of detecting processing defects in the circuit. The design and performance of a prototype BIC sensor for static CMOS are discussed. It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process. The presented design met all basic requirements: it was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution. The main disadvantage of the described design, however, was a substrate current caused by the structure of the bipolar transistor.>

Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the tutorial an overview of the actual mechanisms causing processing defects, and the defects' electrical manifestations will be discussed. It will be demonstrated that inadequate insight into the physics of processing defects and the manufacturing process may lead to inefficient testing of actual VLSI circuits.

In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both during the design process and during the manufacturing process. This framework is general enough to bridge the gap between the traditional concepts of parametric and catastrophic yield. We provide a classification of causes of yield loss which is essential for efficient yield estimation. Finally, we relate yield to manufacturing costs which provides a common denominator for the discussion of the manufacturing process efficiency.

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.

IC chips or manufactured wafers run through selection processes at various stages of the fabrication process. Typically, the most important is the selection performed on IC dice which are tested directly on manufacturing wafers. This paper deals with the problem of the optimal assignment of the upper and lower selection thresholds applied for selecting dice during the wafer measurements. The tolerance assignment is defined as a statistical optimization problem, where the optimization objective function is a measure of the manufacturing profit. In the paper a method for computing a solution of this optimization problem is proposed, and an example of the industrial application of this method in the Computer-Aided Manufacturing (CAM) area is given.

Information about the random behavior of the IC manufacturing process can be applied for IC and process design tasks. In this paper a methodology for modeling random fluctuations of IC manufacturing process is proposed. A simulator of a complete bipolar manufacturing process called FABRICS, is described. A few applications illustrating advantages of the proposed statistical process modeling method are discussed.