A technique determines the optimal window width for orbiting rod transmission studies in positron emission tomography (PET). Windowing reduces noise in orbiting rod transmission studies. Lines-of-response (LOR) which intersect the rods generate primarily true coincidence events. LOR which pass far from the rods generate random and scatter events. Since the angular position of the orbiting rods is known in real-time, LOR which produce mostly noise are gated off. When optimally determined, the rod window width maximizes the noise equivalent counts (NEC) collected in the transmission study. Transaxial rod projection profiles of trues, randoms, and scatter produce NEC versus window width plots. For the ECAT EXACT line of PET systems and a 20-cm water cylinder, optimal is five LOR wide.

This paper presents a fast procedure to generate physical (capacitance, resistance, RC) constraints and timing weights for timing driven physical design.When the capacitance of the nets and the resistance/RC delay of the source-sink segments of the layout are not bigger than the corresponding constraints, the timing requirements can be met.The main results are: a) a fast procedure with linear run-time in the number of pins in the design, b) controlling wire delay due to wire resistance, c) fast interaction between physical design and timing analysis for timing and hirability control.

A special multistack structure and optimization technique to partition, place, and wire the data-path macros in the form of the multistack structure are described, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: to fit the circuits within the chip boundary; to ensure data-path internal wirability; as well as external stack wirability to the other circuits; and to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high-density data path chips.>

As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible. This paper describes a special multi-stack structure, optimization techniques and algorithms to partition, place and wire the data-path macros in the form of the multi-stack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). The overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wireability, including stack to random logic wireability, and (3) to minimize wire lengths for wireability and timing. A tool for automatic multi-stack optimization has been implemented and applied successfully to layout some high density data-path chips.

A method is presented for floorplanning data-path chips by a technique of multi-terrain partitioning with integrated global wiring to partition the objects into terrains, followed by multistack placement and standard-cell placement. Requirements on terrain size, terrain shape, wirability, and timing are considered. Results obtained for some chip designs are presented.>

In this paper we consider the problem of optimal wiring of VLSI circuits. The topological placement of the circuit elements (macros) on the chip is assumed to have a special hierarchical structure, i.e., to be a slicing floorplan, represented by a binary (slicing) tree. Instead of the usual objective of minimum wire length, we consider the problem of minimizing the overall area of the wired floorplan. For the case of a single multiterminal net connecting n macros, we obtain a wiring algorithm of complexity O(nd), where d is the depth of the slicing tree. The case of several multiterminal nets is still under investigation.

We present a global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. The worst-case run-time for an arbitrary slicing tree (totally skewed) is O(M /sup 2/ N). When the floorplan is represented by a balanced slicing tree, the run-time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and is used for chip designs. Experiments on both real and randomly generated designs show that the hierarchical router performs equally well as a flat global router in terms of wire length and wireability handling, but much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger-size problems).

We present a global wiring algorithm used in a top-down physical design environment, i.e. macros are laid out only after global wiring is done, and wires are allowed to pass through macros (wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. Given a balanced slicing tree representation of the floorplan, the worst-case running time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and has been used for actual chip design. Experiments showed that the hierarchical router performs better than a flat maze type router in wireability handling, equally well in wire length, and much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger sized problems).