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Ghislaine Thuau

dblp:07/5738 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 93% Integrated circuit design · 7%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis		 0.021988
Optimized Layout of MOS Cells · IEEE Trans. Computers 1988
Systematic and optimized layout of MOS cells · DAC 1985
Electronic design automation
physical design		 0.021988
Optimized Layout of MOS Cells · IEEE Trans. Computers 1988
Systematic and optimized layout of MOS cells · DAC 1985
Electronic design automation › physical design
cell layout		 0.011985
Systematic and optimized layout of MOS cells · DAC 1985
Integrated circuit design
digital circuit design		 0.011988
Optimized Layout of MOS Cells · IEEE Trans. Computers 1988

Methods — techniques the papers use, named apart from their topics

topological synthesis · 0.0
YearPublicationVenuePosition
1993 A Unified Framework for Describing and Verifying Hardware Synchronous Sequential Systems
Ghislaine Thuau, Bachir Berkane
 Formal Methods Syst. Des.1
1988 Optimized Layout of MOS Cells
abstract
A design method using both logical optimization and optimized topological arrangements is described. Starting from a minimized Boolean function, a synthesis of an optimized well-structured network is obtained. The most original aspect of this approach is a transistor merging procedure leading to a nonseries-parallel network while maintaining a systematic layout. An extension to the synthesis of several functions relies on transistor mergings between functions and allows comparisons with a PLA implementation. Gains in both area and performance are obtained.>
Ghislaine Thuau, Gabriele Saucier
 IEEE Trans. Computers1
1985 Systematic and optimized layout of MOS cells
abstract
The logical synthesis methods are dependant technology and must be strongly connected to the topological design. We present here a logical and topological synthesis method for complex MOS cells leading to a systematic, optimized and easy to interconnect layout.
Gabriele Saucier, Ghislaine Thuau
 DAC2