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L. J. Vidunas

dblp:08/10972 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.021984
An automated system for testing LSI memory chips · DAC 1984
Delay test generation · DAC 1977
Electronic design automation › hardware verification and test › test generation › fault test generation
delay fault test generation		 0.011977
Delay test generation · DAC 1977
Electronic design automation › hardware verification and test
test generation		 0.011977
Delay test generation · DAC 1977
Electronic design automation › hardware verification and test
memory testing		 0.011984
An automated system for testing LSI memory chips · DAC 1984

Methods — techniques the papers use, named apart from their topics

automated testing · 0.0
YearPublicationVenuePosition
1984 An automated system for testing LSI memory chips
H. D. Schnurmann, L. J. Vidunas, R. M. Peters
 DAC2
1977 Delay test generation
E. R. Hsieh, Robert A. Rasmussen, L. J. Vidunas, W. T. Davis
 DAC3