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Massimo Sivilotti

dblp:08/4016 · also Massimo A. Sivilotti · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 4

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 34% Emerging computing paradigms · 34% Integrated circuit design · 21%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
neuromorphic computing
0.011992
Silicon Auditory Processors as Computer Peripherals · NIPS 1992
Integrated circuit design
analog and mixed-signal circuits
0.011992
Object-Based Analog VLSI Vision Circuits · NIPS 1992
Integrated circuit design › analog and mixed-signal circuits › analog VLSI
analog VLSI circuits
0.011992
Object-Based Analog VLSI Vision Circuits · NIPS 1992

Methods — techniques the papers use, named apart from their topics

analog VLSI · 0.0object-based representation · 0.0
YearPublicationVenuePosition
1993 Silicon auditory processors as computer peripherals
abstract
Several research groups are implementing analog integrated circuit models of biological auditory processing. The outputs of these circuit models have taken several forms, including video format for monitor display, simple scanned output for oscilloscope display, and parallel analog outputs suitable for data-acquisition systems. Here, an alternative output method for silicon auditory models, suitable for direct interface to digital computers, is described. As a prototype of this method, an integrated circuit model of temporal adaptation in the auditory nerve that functions as a peripheral to a workstation running Unix is described. Data from a working hybrid system that includes the auditory model, a digital interface, and asynchronous software are given. This system produces a real-time X-window display of the response of the auditory nerve model.
John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie
IEEE Trans. Neural Networks4
1992 Object-Based Analog VLSI Vision Circuits
Christof Koch, Binnal Mathur, Shih-Chii Liu, John G. Harris, Massimo Sivilotti
NIPS6
1992 Silicon Auditory Processors as Computer Peripherals
John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie
NIPS4
1990 A digital neural network architecture for VLSI
abstract
An approach to solving the two most serious shortcomings of previous artificial neural network implementations is discussed. A flexible architecture that permits the realization of arbitrary network topologies and dimensions is presented. Furthermore, the performance of this architecture is independent of the size of the network and permits the processing of typically 100000 patterns per second. The key innovation is the representation of neuron activations and synaptic weights as stochastic functions of time, leading to efficient implementations of the synapses. High densities of synapses per silicon area, exceeding even analog implementations, have been achieved. Finally, the neuron activations are represented digitally, as are the synaptic computations, thereby permitting fabrication of digital neural network architectures using a variety of standard, low-cost semiconductor processes. A pair of general-purpose chips (SU3232 and NU32) that permit post facto construction of neural networks of arbitrary topology and virtually unlimited dimensions is presented
Max Stanford Tomlinson Jr., Dennis J. Walker, Massimo Sivilotti
IJCNN3