Brain Computer Interfaces (BCI) can provide severely impaired users with alternative communication paths, by means of interpretation of the user's brain activity. Among BCI operating paradigms, SSVEP is largely exploited for its potentially high throughput and reliability. In this paper, two novel SSVEP processing algorithms are presented, focused on calibration-free operation and computational efficiency, targeted for development of BCI embedded modules. A comparison with other popular SSVEP signal processing algorithm (MEC, AMCC, CCA) is also made; results demonstrate the feasibility and effectiveness of the proposed solutions.

Currently, commercially available standard-cell libraries are often unstructured set of cells, suitable for several optimization criteria: speed, power, leakage and area consumption. Exploiting a large number of items makes the synthesis process and the library maintenance quite demanding. By smartly selecting a reduced set of cells, such efforts can be reduced, without critically affecting performance. This paper presents a library-reduction strategy which allows for selecting an arbitrarily small subset of cells, also taking into accounts for the features of the actual synthesis tool. Compaction procedure could be driven by one chief criterion (e.g., orienting compacted library at small area, low-power consumption, high speed circuitry). Library compaction is tuned by means of a large set of benchmark circuits, in order to produce results suitable for general-purpose circuit design. In this paper, the compaction strategy is illustrated, and influence of compaction on circuit synthesis and performance is discussed over a wide range of cases, including different technology nodes and silicon foundries. With respect to full-size library synthesis, performance do not appreciably degrades, and in several cases actually improves. Synthesis time decreases and library maintenance and characterization tasks can be significantly reduced. By analyzing and comparing actual contents of several reduced libraries, general criteria for the design of low cell-count libraries can also be inferred.

Recently,radio frequency identification(RFID) systems have gained popularity in manufacturing units, inventory, and logistics, as they represent an inexpensive and reliable solution for automatic identification. Moreover, RFID transponders are expected to become a key element in the ubiquitous computing scenario. Tags will likely be used to collect sensors data, enabling noninvasive environment monitoring. Low-cost passive UHF transponders are expected to play a major role in this context, due to extended read range capabilities. Within a passive tag, power harvested from the field irradiated by the reader during the communication should operate both digital control circuitry and potential sensing devices. Exploiting ultra-low power tag circuitry would provide sensing sections with higher energy, thus improving measurement performance. In this paper, the design of a novel circuit is presented, which implements the baseband processor of a UHF-RFID tag in compliance with the ISO 18000-6B protocol. Regardless of protocol selection issues, several power saving strategies are devised, both at the system and circuit levels, suitable for passive transponder implementation. Near-threshold operation has been exploited to attain ultra-low power consumption while keeping fair performance. A set of standard cells has been designed, suitable for the power-limited specific application. The proposed solution has been successfully checked by means of a physical implementation on CMOS 0.18$ \mu{\hbox {m}}$technology. Test chips have been characterized in terms of voltage and frequency operating range and power consumption figure has been extensively analyzed. Measurement results fully support the selected design approach: the baseband processor dissipates only 440 nW average power when operated at 800 kHz and 0.6 V. This extremely-low power consumption enables high-performance ubiquitous computing.

In this paper, the development of a prototypal wireless sensor platform is described, aimed at assisting elderly people and people with disabilities in their daily living activities at home. The wireless sensor network is embedded into a more general home control and monitoring network, from which it can borrow remote communication and supervision facilities, enhancing versatility and reliability. A wearable sensor has been developed, capable of smart recognition of abnormal gait and falls. Effective algorithms have been devised, to make the device suitable for low-power hardware implementation. After initial prototyping phases (based on microcontrollers and FPGA) VLSI synthesis has been carried out, to estimate actual silicon area and power consumption. Then, extensions of the approach have been foreseen, accounting for multiple sensor management. An example of a low cost embedded heartbeat monitor is discussed.

Cheap passive radio frequency identification (RFID) tags operating in ultra high frequency (UHF) bands are fostering innovation in several field such as building access control, goods tracking, supply chains management and automatic product checkout. RFID transponders can also be coupled to tiny sensors, enabling non invasive monitoring of environmental and personal parameters. To ensure the privacy of highly sensitive data, encryption and authentication capabilities should be embedded in RFID devices, in a fashion compatible with tight power budgets of wireless devices. In this contribution, a baseband-processor is introduced, which complies with ISO 18000-6C (EPC Class1 Gen2) protocol and integrates AES primitives aimed at secure data transmission. Performance of passive RFID devices is limited by the available power, harvested from the incoming radiation. Power-saving strategies are devised, both at the system and the circuit levels. A set of standard cells has been designed, suitable for near-threshold voltage operations. Physical implementation on CMOS 0.18um technology has been carried out and the chip has being fabricated.

Typically, commercially available standard-cell libraries consist of a large set of items, including cells optimized with respect to speed, area or power consumption. A large number of cells makes the synthesis process and the library maintenance quite demanding. By using a reduced set of properly-selected cells, such efforts can be reduced, without critically affecting performance. This paper introduces an innovative library-reduction strategy, based on a evolutionary algorithm, which allows for selecting an arbitrarily small subset of cells. Library compaction is strictly related to the features of the actual synthesis tool, and is tuned by means of a large set of benchmark circuits, so that it produces results suitable for general-purpose circuit design. Different technologies were accounted for, analyzing dependence of the area, time and power figures on the library cell count. Performance, with respect to full-size library synthesis, do not appreciably degrades, and in several cases actually improves. Synthesis time decreases and library maintenance and characterization tasks can thus be significantly reduced.

Recently RFID (Radio-Frequency IDentification) systems have gained popularity in manufacturing units, inventory, logistics, as they represent an inexpensive and reliable solution for automatic identification. RFID tags are expected to become a key element in the future ubiquitous computing scenario. Low-cost passive (i.e. featuring no batteries) tags are supposed to play a major role in this context. UHF tags, in particular, allow for extended read ranges. Performance of such devices, however, is limited by the available power, extracted from the incoming radiation. In this paper, the design of a novel circuit is presented, which implements the digital controller of a UHF-RFID tag in compliance with the ISO 18000-6B protocol. Powersaving strategies are devised, both at the system and the circuit levels. A set of standard cells have been designed, suitable for the power-limited specific application. Physical implementation on CMOS 0.18 ìm technology has been carried out and the chip is being fabricated. Functional checks have been successfully performed by means of an FPGA-based prototype.

A 3-D general-purpose device simulator is presented, and issues related to its geometrical flexibility and computational efficiency are discussed. Triangular-based prismatic elements are used as building blocks for the discretization of device equations, providing a reasonable tradeoff between simplicity and geometrical flexibility. Suitable numerical techniques, including a 'local-solution' algorithm, have been implemented in order to improve the computational efficiency of the code. A general treatment has been devised to handle floating-gate devices, which allows the program to cope with complex structures, such as a dual EPROM structure. Three-dimensional and two-dimensional simulation results are compared.>

An algorithm allowing the automatic generation of a mesh and accounting for the main physical features of the problem is presented. The adaptivity is provided by a refinement strategy which preserves the characteristics of the initial grid, inserting nodes only in the regions where the solution deviates from a linear behavior. A geometrical interpretation in terms of a monitor surface is given, and various different approaches to the problem are discussed. The efficiency of the algorithm is enhanced by a local solution scheme, which uses previously computed values of all the unknown quantities as boundary conditions for the newly generated nodes. A few examples illustrate the performance of the algorithm.>

A discretization scheme is applied to the hydrodynamic model for semiconductor devices that generalizes the Scharfetter-Gummel method to both the momentum-conservation and the energy-conservation equations. The major advantages of the scheme are: (1) the discretization is carried out without neglecting any terms, thus providing a satisfactory description of such effects as velocity overshoot and carrier heating; and (2) the resulting equations lend themselves to a self-consistent solution procedure similar to those currently used to solve the simpler drift-diffusion equations. Two-dimensional steady-state simulations of an n-channel MOSFET and of an n-p-n BJT (bipolar junction transistor) have been carried out by means of an improved version of the program HFIELDS. Carrier-temperature plots have been obtained with a reasonable computational effort, demonstrating the efficiency of this technique. The results have been compared with those obtained with the standard drift-diffusion model and significant differences in the electron concentration have been found, especially at the drain end of the MOSFET channel.>

In this paper we propose a sensitivity-analysis technique for device design. By this method, we determine the linearized variations of the device terminal characteristics following some change either in the impurity distribution, or in device geometry, such as channel length and oxide thickness. This technique has been implemented in our general-purpose two-dimensional device-analysis program (HFIELDS) and proved to be very efficient, as only the assembly of the RHS and one back-substituton is required in order to achieve the final result. It is believed that the present method can be profitably used for both deterministic and statistical device design.