In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.

For the modeling of interconnect in three-dimensional packagings, this paper proposes a method based on the electric field integral equation (EFIE) with cylindrical conduction mode basis functions (CMBF). The bases are defined to describe arbitrary skin and proximity effects, and partial impedances are obtained from the formulation of the EFIE with CMBF's. Examples of several 3-D interconnects verify that the proposed method is efficient in speed and memory.

Power integrity simulation for system-on-package (SoP) based modules is a crucial bottleneck in the SoP design flow. In this paper, the multi-layer finite difference method (M-FDM) augmented with models for split planes has been proposed as a fast and accurate frequency domain engine. Results demonstrating the accuracy and scalability of the method have been presented. In particular, the algorithm was employed to the analysis of a realistic 6 layer package with ~ 200k nodes.

Physical layout generation of RF embedded passive design is not an easy task since the response of a given layout is tightly coupled with the response of the individual components and the effect of interconnect parasitics. In this paper we propose a methodology for automatic layout generation of embedded passive RF circuits. We make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages of the methodology to obtain the desired goals. Full-wave EM simulations is completely out of the design loop, so our methodology significantly reduces the design time for RF embedded passive circuits. The proposed approach has been used successfully to generate layout for band-pass filters of varying sizes.

We present a method for fast analysis of signal and power integrity based on a recently developed multilayered finite difference method (M-FDM). In order to accurately model multilayered planar structures, which are three dimensional, M-FDM combines two-dimensional models for power/ground planes using a multilayered unit cell approach. In this way, noise coupling can be considered not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. For a cosimulation of signal and power integrity, transmission line models also need to be included. The interaction between the signal transmission and power distribution modes is taken into account using a modal decomposition technique. An equivalent circuit model becomes available based on this finite difference approximation as well. Based on this network representation, second order effects such as fringe and gap fields can be included in M-FDM using equivalent circuit models for these fields. This results in a very accurate method that can be used for fast analysis of signal and power integrity in arbitrary package and board designs having any stack-up configuration and number of layers.

This paper describes a methodology for performing system level signal and power integrity analyses of SiP-based systems. The paper briefly outlines some new modeling and simulation techniques that have been developed to enable the proposed methodology. Some results based on the application of this methodology on test systems are also presented.