Demo Data from SIGIR 2026 / reviewers in the wild / expert
Colin R. Edwards
dblp:09/2079
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 1978
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 94% Integrated circuit design · 6% | |
| Theoretical computer science
1 paper |
Logic in computer science · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 3 | 1978 | A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods · IEEE Trans. Computers 1978 Author's Reply · IEEE Trans. Computers 1976 The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis · IEEE Trans. Computers 1975 |
Electronic design automation › logic synthesis
threshold logic synthesis |
0.0 | 2 | 1976 | Author's Reply · IEEE Trans. Computers 1976 The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis · IEEE Trans. Computers 1975 |
Electronic design automation › logic synthesis
boolean function decomposition |
0.0 | 1 | 1978 | A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods · IEEE Trans. Computers 1978 |
Electronic design automation › logic synthesis
combinational logic synthesis |
0.0 | 1 | 1978 | A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods · IEEE Trans. Computers 1978 |
Electronic design automation › logic synthesis › boolean function analysis
boolean function classification |
0.0 | 1 | 1975 | The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis · IEEE Trans. Computers 1975 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1975 | The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis · IEEE Trans. Computers 1975 |
Integrated circuit design › digital circuit design › threshold logic
threshold logic gate |
0.0 | 1 | 1975 | The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
author reply · 0.0symmetry recognition · 0.0rademacher-walsh transform · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1978 | Some Improved Designs for the Digital Summation Threshold Logic (DSTL) GateabstractSome computer-generated improved designs for the digital summation threshold logic gate, first described by Hurst, are presented. These designs require considerably fewer logic elements than the original designs and have improved gate-delay parameters. The improved designs are shown to have delay times comparable to those of the ‘bifurcated’ gates of Reddy and Swamy, whilst enjoying a more elegant structure. Some implementations for these circuits are given. Colin R. Edwards |
Comput. J. | 1 |
| 1978 | A Digital Synthesis Procedure Under Function Symmetries and Mapping MethodsabstractA new mathematically based method of synthesis for combinational digital networks is presented, based upon the recognition of symmetry patterns in the functions being synthesized. The design procedure is structured such that at each stage of the synthesis a relevant gate assembly is indicated, which leaves a simplified "remainder" function to be synthesized at the next stage of the realization. This decomposition procedure optimally uses gates with a fan in of two, but post-synthesis reconfiguration for amalgamation into larger fan-in gates is available. Colin R. Edwards, Stanley L. Hurst |
IEEE Trans. Computers | 1 |
| 1976 | Author's ReplyabstractI wish to thank C. K. Yuen for calling attention to a previous paper on the application of the Rademacher-Walsh transform to threshold logic synthesis [1]. Colin R. Edwards |
IEEE Trans. Computers | 1 |
| 1975 | The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic SynthesisabstractFive operations are defined in the Rademacher-Walsh transform domain. It is shown that these operations allow Boolean functions to be classified in a very concise way. The result of applying this classification to Boolean functions of up to fourth order indicates that threshold functions play an important part in the composition of Boolean functions. A synthesis method is developed for the synthesis of any Boolean function using, as a basic element, an "optimized universal threshold logic gate." This gate overcomes the analog threshold tolerancing problems encountered in other threshold gate designs and is readily fabricated in an integrated circuit form. The use of this gate in logic design is expected to provide a considerable cost-saving over conventional methods. Colin R. Edwards |
IEEE Trans. Computers | 1 |
| 1972 | The logic of Boolean matricesabstractA Boolean matrix algebra is described which enables many logical functions to be manipulated simultaneously. The algebra is similar to conventional matrix algebra and its structure includes a topological description of logic circuits. The matrices are readily manipulated by the digital computer. Colin R. Edwards |
Comput. J. | 1 |