In type 1 diabetes, diurnal activity routines are influential factors in insulin dose calculations. Bolus advisors have been developed to more accurately suggest doses of meal-related insulin based on carbohydrate intake, according to pre-set insulin to carbohydrate levels and insulin sensitivity factors. These parameters can be varied according to the time of day and their optimal setting relies on identifying the daily time periods of routines accurately. The main issues with reporting and adjustments of daily activity routines are the reliance on self-reporting which is prone to inaccuracy and within bolus calculators, the keeping of default settings for daily time periods, such as within insulin pumps, glucose meters, and mobile applications. Moreover, daily routines are subject to change over periods of time which could go unnoticed. Hence, forgetting to change the daily time periods in the bolus calculator could contribute to sub-optimal self-management. In this paper, these issues are addressed by proposing a data-driven model for identification of diabetes diurnal patterns based on self-monitoring data. The model uses time-series clustering to achieve a meaningful separation of the patterns which is then used to identify the daily time periods and to advise of any time changes required. Further improvements in bolus advisor settings are proposed to include week/weekend or even modifiable daily time settings. The proposed model provides a quick, granular, more accurate, and personalized daily time setting profile while providing a more contextual perspective to glycemic pattern identification to both patients and clinicians.

[Formula: see text] is a primary marker of long-term average blood glucose, which is an essential measure of successful control in type 1 diabetes. Previous studies have shown that [Formula: see text] estimates can be obtained from 5-12 weeks of daily blood glucose measurements. However, these methods suffer from accuracy limitations when applied to incomplete data with missing periods of measurements. The aim of this article is to overcome these limitations improving the accuracy and robustness of [Formula: see text] prediction from time series of blood glucose. A novel data-driven [Formula: see text] prediction model based on deep learning and convolutional neural networks is presented. The model focuses on the extraction of behavioral patterns from sequences of self-monitored blood glucose readings on various temporal scales. Assuming that subjects who share behavioral patterns have also similar capabilities for diabetes control and resulting [Formula: see text], it becomes possible to infer the [Formula: see text] of subjects with incomplete data from multiple observations of similar behaviors. Trained and validated on a dataset, containing 1543 real world observation epochs from 759 subjects, the model has achieved the mean absolute error of 4.80 [Formula: see text] mmol/mol, median absolute error of 3.81 [Formula: see text] mmol/mol and [Formula: see text] of 0.71 ± 0.09 on average during the 10 fold cross validation. Automatic behavioral characterization via extraction of sequential features by the proposed convolutional neural network structure has significantly improved the accuracy of [Formula: see text] prediction compared to the existing methods.

This paper presents a very low power/area design for the advanced encryption standard (AES) based on an 8-bit data path. The average measured core power on a 0.13-μm CMOS using a 100-kHz clock and a core voltage of 0.75 V is 692 nW. The core area is 21 000 μm2and the latency is 356 cycles. This design further challenges the low-resource end of the design space and is the first reported submicrowatt design for the AES; it has significant power-latency-area performance improvements over the previous state-of-the-art application-specific IC (ASIC) implementations.

This paper presents a practical realization of a secure passive (battery-less) RFID tag. The tag consists of an off the shelf front end combined with a bespoke 0.18 mum ASIC assembled as a credit card sized prototype. The ASIC integrates the authors' ultra low power novel AES design together with a novel random number generator and a novel protocol which provides both security and privacy. The analysis presented shows a security of 64-bits against many attack methods. Both modeled and measured power results are presented. The measured average core power consumed during continuous normal operation is 1.36 muW.

Two designs have been presented for high throughput pipelined implementation using field-programmable gate arrays (FPGAs) of the advanced encryption standard (AES). Both are believed to be faster than the existing FPGA designs and achieve throughputs of 30 and 28 Gbps. The fastest design achieves a throughput, for either encipher or decipher, in excess of 30 Gbps using a Xilinx Spartan-III part and allows key changes every 120 cycles. A second design achieves a throughput of 28 Gbps using a Xilinx Virtex-II part and supports both key and encipher/decipher changes every clock cycle. In order to achieve this, careful floor planning and a novel pipelined key expander were developed together with modifications to the MixColumns and composite field implementation of the SubBytes operation. Such an architecture has application for servers supporting multiple AES secure channels and can support, in a multi-channel environment, any feedback mode, including cipher block chaining. Previous pipelined designs have not shown this capability.

This paper presents a very low area design for the advanced encryption standard (AES) capable of functioning in three of its feedback modes to provide flexible support for its use as a stream cipher. The architecture is based around an 8-bit application specific instruction processor (ASIP) and includes UARTs to support asynchronous serial I/O. The entire design fits within the smallest Xilinx Spartan-II FPGA (XC2S15), occupying 174 slices and two block memories. The design achieves a throughput of 2.3 Mbps with a 70MHz clock in OFB, CTR and CFB modes. The size is approximately 27% smaller than a comparable RC4 design