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Udaya A. Ranawake

dblp:09/4683 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 46% Electronic design automation · 23% Parallel and multicore computing · 23%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
parallel algorithms
0.011994
PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
High-performance computing › parallel numerical algorithms
parallel monte carlo
0.011994
PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
High-performance computing
scientific computing systems
0.011994
PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › technology computer-aided design
semiconductor device simulation
0.011994
PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

monte carlo method · 0.0finite difference method · 0.0dynamic load balancing · 0.0
YearPublicationVenuePosition
1995 BEOWULF: A Parallel Workstation for Scientific Computation
Thomas L. Sterling, Daniel Savarese, Donald J. Becker, John E. Dorband, Udaya A. Ranawake, Charles V. Packer
ICPP (1)5
1994 PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator
abstract
We present PMC-3D, a parallel three-dimensional (3-D) Monte Carlo device simulator for multiprocessors. The parallel algorithm is an extension of the standard Monte Carlo device simulation model in 3-D, in which the particle dynamics generated from the stochastic Monte Carlo method are solved simultaneously with Poisson's equation on a 3-D mesh using finite differences. Due to the large computational requirements of 3-D device simulation, it is necessary to parallelize both the Poisson solver and the Monte Carlo simulation phase of the device simulator. The parallel algorithms were implemented on a 1024-node distributed memory nCUBE multicomputer and a 4-mode shared memory Ardent multiprocessor. We validate the accuracy of our implementations by generating the static characteristics of a MESFET and present test results on the fixed and scaled speedups obtained on the two types of parallel computers. Improvements in performance are observed utilizing dynamic load balancing for the distributed memory case.>
Udaya A. Ranawake, Carl Huster, Patrick M. Lenders, Stephen M. Goodnick
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1